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Multi-national industrial and energy company METLEN Energy & Metals S.A. of Athens, Greece — which operates the only vertically integrated bauxite, alumina and primary aluminium production unit in the European Union (EU) with privately owned port facilities — has announced a long-term commercial agreement for the supply of about 25% of the annual gallium production from its planned production facility in Greece...

Wolfspeed Inc of Durham, NC, USA — which makes silicon carbide (SiC) materials and power semiconductor devices — has appointed Andy W. Mattes to its board of directors...

This is hackxpansion, it is powered by the RP2354B, has a 2" 240x320 LCD, and a ≈6h battery life while in use. It has two modules slots by default, and I'm currently working on a back attachment (last photo) which add two more slots, but I think the postal company lost one of my packages that had the parts for it😭 The modules connect with a 2x7 2.54mm header, this way you don't even need to make a pcb to create new modules, just use a pref board, and you can just plug in dupont cables directly into the device. Each module has two resistors, which when connected each become the top resistor of a voltage divider, a 12bit ADC measures the resulting voltages, and loads the correct driver for that module. The firmware is written in rust, in a way so that writing new drivers and apps is really easy, and can be done in external crates. Each app can depend on drivers, and only be loaded into the app list, if all their requirements are met. I tried porting a NES emulator, but there doesn't exist an emulator written in rust currently that actually performs well on this hardware, I got an average of 12FPS in Super Mario Bros. I've collabed with Hack Club, and I will be running a program where if you are a teen 13-18(inclusive) and design 4 modules, you get funding to make these modules and get one of these consoles for free. The program will start on Aug 3 and end on Aug 31. If you want to participate [RSVP] now! (https://meko.fillout.com/hackxpansion). Repo Website(docs WIP) submitted by /u/K0eg [link] [comments]

Based on BrainChip’s Akida neuromorphic engine, the AKD1500 edge AI coprocessor is now available in a compact M.2 2230 (22×30 mm) form factor. The card features a B+M key edge connector for use with Raspberry Pi 5 and compatible host systems, enabling fanless, plug-and-play AI acceleration without redesigning existing power or cooling systems.

Operating from a 3.3-V supply, the AKD1500 M.2 card connects through a two-lane PCIe Gen2 host interface. The coprocessor integrates 32 neural processing units (NPUs) and delivers up to 800 effective GOPS (INT4) for edge AI inference. It also includes 1 MB of dual-port on-chip memory and consumes a typical 250 mW at 400 MHz.

The event-based digital architecture delivers ultra-low-power acceleration for standard neural network models and supports on-device learning, enabling applications to adapt without a cloud connection or full model retraining. Models are developed and optimized using BrainChip’s MetaTF software flow with TensorFlow/Keras and PyTorch front ends before deployment to the card.

The AKD1500 M.2 card with a B+M key connector is priced at $129 and is available for purchase directly from BrainChip.

AKD1500 M.2 product page 

BrainChip Holdings 

The post Edge AI coprocessor adopts M.2 form factor appeared first on EDN.

Advantech is launching a portfolio of servers based on AMD EPYC 9006 SP8 processors to support next-generation AI infrastructure. Servers, such as the SKY-924E5F, provide the scalability and reliability required for AI, high-performance computing (HPC), networking, and mission-critical industrial workloads.

EPYC 9006 series server CPUs feature up to 128 Zen 6 or Zen 6c cores, 256 threads, and 2-nm process technology, delivering up to a 20% average performance improvement over the previous generation and up to a 20% performance-per-watt improvement. These processors enable more virtual machines, higher throughput, and improved system efficiency. With up to 128 PCIe Gen6 lanes per CPU, CXL 3.1 memory expansion, and support for DDR5-8000MHz and MRDIMM-12800MHz, the EPYC-powered servers provide balanced compute, memory, and I/O performance.

The edge servers support GPU-accelerated AI workloads and AFA-ready high-density E1.S/E3.S NVMe SSD storage. The lineup includes the following models:

• SKY-642E5, 4U MGX GPU server for large-scale AI acceleration
• SKY-722E5, 2U DC-MHS server with DC-SCM capability for modular data center and edge AI deployments
• SKY-712E5, 1U DC-MHS server with HHHL and FH-3/4L expansion card compatibility for high-density enterprise edge and cloud workloads
• SKY-822E5, 2U short-depth DC-SCM modular server accommodating 2–3 dual-slot GPU cards for space-constrained edge data centers
• SKY-924E5F, 2U 4-node front-access server for distributed edge computing
• ASMB-982 and ASMB-832, server boards for flexible, expandable system designs

A timeline for server availability was not provided at the time of this announcement. Learn more about the Advantech + AMD EPYC 9006 platform here.

Advantech

The post Advantech AI servers leverage AMD EPYC appeared first on EDN.

Optimized for physical AI, AMD’s Ryzen AI Embedded X100 series processors combine CPU, GPU, and NPU resources on a single embedded SoC. With up to 16 AMD Zen 5 CPU cores, an integrated GPU, power-efficient NPU, and unified memory, the processors handle perception, reasoning, and real-time control workloads in robotics, industrial automation, aerospace and defense, and other embedded systems.

AMD says the series delivers up to 2.1× higher multithreaded CPU performance, 1.7× higher graphics performance, and 3.5× higher AI token generation with 1.4× faster time-to-first-token than Intel Core Ultra Series 3 processors. The company also says the processors provide up to 3× higher peak FP32 performance than the NVIDIA Jetson T5000 and an average 1.7× faster beamforming for cardiac ultrasound than the NVIDIA RTX 4000 Ada.

The Ryzen AI Embedded X100 series supports an open software stack with Linux, the AMD ROCm GPU software stack, the Xen Hypervisor, and AI frameworks including PyTorch, ONNX, and TensorFlow. AMD also provides tools to migrate CUDA codebases to ROCm.

Production availability of the Ryzen AI Embedded X100 series is expected in Q4 2026. Learn more about the processors on the product page or in AMD’s technical blog.

Advanced Micro Devices 

The post Ryzen processors power physical AI workloads appeared first on EDN.

Advanced Energy’s AIH03ZPFC power factor correction (PFC) converter delivers 1100 W of output power in a half-brick form factor. The board-mount module achieves up to 97.3% peak efficiency and a power density of 380 W/in³. According to the company, this represents a 2.3% improvement in efficiency and a 44% increase in power density over its previous-generation PFC devices.

The AIH03ZPFC integrates features that enhance functionality in a small half-brick design, including internal inrush limiting, digital PMBus control and monitoring, and auxiliary power support for external housekeeping functions. These capabilities make the converter well suited for industrial, medical, defense, and telecommunications systems with demanding size and efficiency requirements.

The AIH03ZPFC provides a 390-VDC output with 1% load regulation, maintains a unity power factor across an 85-VAC to 264-VAC input range, and requires no power derating under low-line conditions.

Baseplate contact cooling supports operation from -20°C to +100°C, with startup at temperatures as low as -40°C. The encapsulated half-brick package measures 2.4 × 2.3 in. (61 × 58.4 mm) and has an installed height of 0.52 in. (13.3 mm).

AIH03ZPFC product page

Advanced Energy Industries

The post Half-brick converter packs high power density appeared first on EDN.

Cadence says its AuraStack AI Super Agent is the industry’s first agentic AI platform for PCB and advanced packaging design. Running on the company’s Allegro AI Studio and accelerated by NVIDIA Blackwell GPUs and NVIDIA CUDA-X libraries, the platform coordinates domain-specific AI agents across planning, implementation, and tightly integrated multiphysics analysis. AuraStack joins Cadence’s ChipStack, InnoStack, and ViraStack AI Super Agents, extending the company’s agentic AI portfolio across IC design, advanced packaging, and PCB design.

Built on the same architecture as Cadence’s ChipStack AI Super Agent, AuraStack combines agentic AI with simulation and optimization tools to automate design exploration, implementation, and signoff. An AI-driven multiphysics foundation concurrently models electrical, thermal, and mechanical behavior to support earlier design optimization.

According to Cadence, AuraStack can accelerate time to market by up to 2× and increase productivity by up to 15× while identifying system issues earlier in the design process to help reduce costly respins. It also enables system-level co-optimization with advanced packaging technologies, including CoWoS, to improve product performance and manufacturability.

Cadence plans to make the AuraStack AI Super Agent available in 2026.

AuraStack product page 

Cadence

The post AI platform unifies PCB, advanced packaging workflows appeared first on EDN.

As the automotive industry shifts toward software-defined vehicles (SDVs), with features and updates delivered via software, vehicle electrical/electronic (E/E) architectures are evolving. These architectures are moving away from traditional flat and domain-based designs, in which separate control units for each function were the norm, to zonal architectures that group vehicle functions based on various criteria, such as physical location, application group, and other functional criteria in zone electronic control units (ECUs).

In a zonal architecture, each zone of a vehicle, such as front, rear, or cabin, has a high-performance controller managing local devices and communicating with other controllers over high-speed networks. This approach is faster to update, easier to scale, less complex, and even cheaper, but it also presents new technical challenges for automakers to overcome. The good news is that innovative microcontroller (MCU) solutions can help tackle those challenges.

Key challenges in the shift to zonal architectures

Zonal architectures offer clear benefits of reducing wiring complexity and consolidating compute resources.

However, each zone controller in an SDV must handle a wide range of tasks, from low-level real-time control of sensors and actuators (such as sensing braking pressure, steering angle, or controlling window-lift motors) to high-level data processing tasks (including controlling advanced safety systems or vehicle dynamics or running local AI models to process sensor data). This means the ECUs in a zonal design require compute capabilities that can handle both time-sensitive and compute-intensive workloads concurrently.

Maintaining freedom from interference among functions is a key challenge. Zonal designs consolidate diverse functions, from safety-critical functions such as braking to non-critical functions such as body control on a single ECU with shared compute and communication resources. Without proper safeguards, a fault in one function could disrupt others.

To prevent this, robust isolation mechanisms such as hardware-enforced separation are needed. Ideally, these features should be embedded in the hardware design rather than software implementation to minimize the impact on performance, behavior, or safety.

In-vehicle networks also need rethinking. Modern SDVs generate massive amounts of data from sensors and devices, including cameras, LiDAR, and radar, to support advanced driver-assistance and autonomous-driving features. The vehicle network must ensure that this data is delivered in a predictable and time-sensitive manner.

Traditional in-vehicle networks such as CAN, LIN, and FlexRay struggle to meet these demands at the scale of the modern SDV. Moreover, Ethernet is increasingly used in vehicles for its advantages in performance, reliability, and connectivity options, and at the same time, many legacy devices in the vehicle still use CAN or LIN.

To ensure network performance and avoid communication bottlenecks, next-gen vehicle controllers should include native support for Ethernet and CAN networking on-chip. A well-architected MCU will also enable sufficient control and acceleration features to reduce latency and ensure predictable message delivery, ultimately resulting in deterministic communications at the vehicle level.

Next-generation automotive MCUs need to adopt improved, low-latency architectures and design philosophies to overcome key challenges in the shift to zonal architectures. (Source: NXP Semiconductors) Making updates secure, easy, and fast

A hallmark of SDVs is the ability and the need to receive secure over-the-air (OTA) updates throughout the vehicle’s life. This contrasts with traditional vehicle designs with dozens of ECUs for which updates are complex, time-consuming, and often performed only in service environments.

For an SDV built on a zonal E/E architecture, software updates can be pushed to a selected number of controllers that can be responsible for the software of an entire region of the vehicle, such as the front zone or the rear chassis zone. To support these frequent updates with minimal downtime, embedded nonvolatile memory (eNVM) needs to be upgraded as well to a more versatile option with much faster write speeds and higher endurance.

How modern MCUs lay the foundation for next-gen SDVs

Next-generation automotive MCUs need to adopt improved, low-latency architectures and design philosophies to overcome these challenges. Rather than relying on a homogeneous architecture, the implementation of heterogeneous cores optimized by functions is required.

The NXP S32K5 MCU, for example, integrates different kinds of CPU cores complemented by various accelerators for dedicated functions such as AI/ML, signal processing, and network acceleration, enabling designers to assign the right function to the right core. Furthermore, a dedicated low-power engine is available for simple tasks, such as periodic wakeups and sensor monitoring, which can help optimize battery life in electric vehicles.

The integration of multiple functions of mixed criticality warrants robust mechanisms to ensure freedom from interference. The S32K5 lives up to this challenge by implementing features such as XRDC, an in-house NXP IP for isolation and resource allocation in hardware from pin to core.

Moreover, dedicated network accelerators need to be implemented for CAN2CAN (communication between CAN networks) and CAN2ETH (communication between CAN and Ethernet networks) acceleration to ensure deterministic and low-latency architectures.

In addition, integrating an Ethernet switch with fast data-routing capabilities ensures that the latest-generation Ethernet vehicle architectures can achieve latency requirements with minimal CPU load.

With an embedded MRAM as the eNVM, the S32K5 offers write speeds that are 15× faster than conventional eFlash. Write without erase and endurance of 1M write cycles of MRAM helps optimize costs, simplify software development, and minimize downtime for the frequent OTA updates expected in an SDV architecture.

Building the foundation for next-gen SDVs

Zonal architectures are emerging as a necessity for next-gen vehicles because they align with the needs of SDVs. They concentrate compute, reduce complexity, and enable new, software-driven experiences. With the latest generation of MCUs as the building blocks, automakers now have more tools to develop zonal vehicle architectures to deliver the high performance, reliability, and flexibility required by next-gen vehicles.

The post Accelerating the shift to next-gen SDVs with zonal MCUs appeared first on EDN.

Self-heated Darlingtion transistor pair linearly senses airflow using just two wires for both power in and signal out.

Suppose we take a common TO-92 transistor and heat it to a constant temperature differential above ambient.  The power input required to keep it there will be determined by its thermal impedance ZT relative to the surrounding air. This suggests it might be handy for air flow measurement.  Maybe even moreso if it needed only a simple two-wire connection for both (phantom) power supply from, and signal delivery to, the supporting electronics.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Please see the Related content listings below for a more detailed treatment of the subject.  Figure 1 graphs the resulting power vs air speed relationship.  Unfortunately, it’s badly bent.

Figure 1 This graph logs power dissipated vs air speed of a TO92 held at a constant 31oC above ambient. Pw = 31/ZT.

Figure 2 shows a practical thermostat circuit to achieve and maintain the delta-T while outputting a signal predictably related to Pw.  It utilizes a Darlington sensor transistor pair (Q1 and Q2) to compensate for ambient temperature and convert the resulting nonlinear Pw curve into a linearized airflow readout.  Its current mode, phantom-power output is compatible and convenient for the long cable runs often seen in airflow measurement applications.

Figure 2 This circuit implements a phantom-powered Darlington anemometer with a 40-140 mA current mode output.  Adjust R10 to calibrate 40 mA (zero fpm), and R11 to calibrate 140 mA (250 fpm). The adjustments interact so some iteration may be necessary.  Sorry ‘bout that.

Q1 serves as the self-heated sensor with Q2 providing ambient temperature compensation.  Opamp A2 runs a feedback loop that forces a constant Vbe differential between Q1 and Q2.  This establishes a constant 31oC temperature differential between Q1 and ambient.  It does this (with the help of Darlington current gain) by forcing Q1’s current draw (I) through R3 to drive Q1’s power dissipation (Pw) to follow the Figure 1 curve of heat-vs-air flow.

Okay so far.  But how does compensation for Figure 1’s nonlinearity happen?   Well, happily the function of Q1’s Pw vs collector current I isn’t linear either.  In fact Pw = 5vI – I2R3.  That quadratic I2 term is the key.  It creates the lovely linearizing curve shown in Figure 3.

Figure 3 This graph logs Q1 power dissipation vs  collector current.  Pw = 5vI – I2R3.

The 2nd-order curvature of fig. 3 irons out (most of) the bend in Figure 1 and results in a linear 33 to 125 mA current draw over the 0 to 250 fpm flow rate range. Although the match isn’t perfect, when converted to the 40 to 140 mA by opamp A1 and output transistor Q4, the realized output is a calibrated readout of air speed that differs from ideal by less than +/- 5% from 0 to 250 fpm, as shown in Figure 4.

Figure 4 This graph logs anemometer output vs airspeed. FPM = 2.5(Iout – 40mA).

Note that most (~90%) of the output current is actually drawn by inverted regulator U1 as it maintains a constant 5v across the (thirsty) thermal transistors.  All that’s left for A2 and Q4 is to conduct several mA of shim current to establish and maintain calibration, which barely gets Q4 warm.  U1, however, can be called on to dissipate about three quarters of a watt and thus should be bundled in a TO220 or similar package.

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

Related Content

• Self-heated Darlington transistor pair comprises new air flow sensor
• Linearized portable anemometer with thermostated Darlington pair
• Nonlinearities of Darlington airflow sensor and VFC compensate each other
• Improve thermal airflow sensor PSRR with just two resistors
• A groovy apparatus for calibrating miniature high sensitivity anemometers

The post Phantom-powered solid-state linear airflow sensor appeared first on EDN.

Ather Energy has begun rolling out Pothole+ Alerts to customers with Gen 2 and above scooters, including the Ather 450 Apex, 450X and Rizta Z. The feature alerts riders to potholes, broken road patches, uneven roads and speed breakers ahead while navigating, using road intelligence built from data generated by Ather’s connected scooter fleet.

Announcing the rollout on X, Ather Co-founder and CEO Tarun Mehta said the feature has been nearly nine years in the making. “The challenge was never the idea. It was the data,” Mehta wrote, noting that Ather’s growing connected fleet has now generated the scale of road intelligence needed to make the feature a reality.

Every Ather scooter is equipped with onboard compute and connectivity, enabling the company to build large datasets over time and develop software-driven features for its customers. According to Mehta, Pothole+ Alerts is one of the strongest examples of how Ather is leveraging connected vehicle data to enhance the riding experience.

When using navigation, riders will receive alerts for potholes, broken road sections, uneven surfaces and speed breakers ahead. Notifications are displayed on the scooter dashboard and can also be heard through the scooter, the Ather Halo smart helmet or any compatible Bluetooth headset, allowing riders to stay informed without taking their attention off the road.

The rollout reflects Ather’s continued focus on building connected features powered by real-world riding data. Mehta added that Pothole+ Alerts is just the beginning, with the company planning to build more rider experiences on top of its growing road intelligence dataset.

The post Ather Energy Begins Rollout of Pothole+ Alerts to Gen 2 and Above Scooters appeared first on ELE Times.

Skyworks Solutions Inc of Irvine, CA, USA and Qorvo Inc of Greensboro, NC, USA have announced the expected executive leadership team for the combined company, effective upon completion of the pending transaction...

This project has been born because I have been trying to develop an ESC (hardware and firmware) on my own. While the most challenging part has been the firmware (being myself a hardware guy), the most frustrating part has been not finding a flexible hardware platform to develop upon. On the internet many interesting and well-designed ESC boards can be found, but all have something missing; a small feature, a small detail, I was never fully satisfied. So I designed one: STARDRIVE SHIELD This is a project with the goal of creating a NUCLEO-64 compatible shield to be used as a flexible platform to develop and test ESC firmware, but also for educational purposes. To do so, I included as many features as possible. These features are not mandatory, but they can be implemented (or not) in the firmware (e.g. SPI, I2C, CAN, HALL) or configured through the hardware interface (e.g. overcurrent protection, 6 or 3 PWM). In this way, the STARDRIVE SHIELD grants flexibility to the developer and it is adapt to various needs. I designed it to be compatible with Nucleo-G474 and Nucleo-F446. Compatibility with other boards has to be verified. The STARDRIVE SHIELD is built around the STDRIVE101 gate driver and BSZ099N06LS5 MOSFETs. It presents 3 low sides shunt resistors and 3 relative INA240A2 current sense amplifiers. With STARDRIVE SHIELD you can implement from 6 step to FOC motor control algorithms. Electrical Characteristics Inprut Voltage Vin = 12 - 48 V Maximum DC current Idc,max = 20 A Hardware Characteristiscs Three phase gate driver STDRIVE101 Configurable 3PWM or 6PWM through the DIP switch Overcurrent protection can be enabled or disabled through the DIP switch. Vds protection configurable with resistor divider (disabled by default) BSZ099N06LS5 MOSFETs JST connectors to implement: I2C (e.g. for magnetic encoder such as AS5046) SPI (e.g. for magnetic encoder such as AS5047P) CAN HALL sensors (some BLDC motors have embedded Hall sensors) 3 NTC temperature sensors 10k Potentiometer to use as throttle signal (or whatever you want) 3 GPIO driven LEDs (1 Red, 1 Blue, 1 Green) 1 FAULT LED (RED) CAN RX and TX LEDs Power Good LEDs here the github repo: https://github.com/themarcolab/Stardrive-Shield.git Let me know your opinion! Especially if you spot a mistake or you have any constructive feedback. submitted by /u/marco_lab [link] [comments]

For second-quarter 2026, gallium nitride (GaN) power IC and silicon carbide (SiC) technology firm Navitas Semiconductor Corp of Torrance, CA, USA has reported revenue of $10.5m, down on $14.5m a year ago but up 22% on $8.6m last quarter, and at the upper end of the $9.5–10.5m guidance range...

When people talk about AI hardware, the conversation usually begins with the AI accelerator. That is understandable. GPUs, custom AI accelerators, CPUs, and high-performance compute dies are the most visible symbols of the AI era. They are also where much of the leading-edge semiconductor investment is focused.

Advanced logic nodes, extreme transistor density, high-performance standard-cell libraries, and sophisticated design methodologies are all essential to scaling AI compute. But an AI accelerator alone does not create AI infrastructure.

A modern AI system is not one chip, one fab, one node, or one technology family. It’s a physical system built from many semiconductor ecosystems converging through packaging, substrates, interconnect, power delivery, cooling, reliability engineering, and manufacturing scale. And that distinction matters.

The AI era is not only pushing logic scaling. It’s forcing the semiconductor industry to rethink how different fab outputs—logic, memory, analog, power, compound semiconductor devices, photonics, MEMS, and mature-node control silicon—come together as one physical infrastructure platform. In other words: AI infrastructure is becoming a multi-fab physical realization stack.

This is the missing link in many AI hardware discussions.

The visible part: Leading-edge logic

The most visible part of AI hardware is the leading-edge logic die. This includes GPUs, CPUs, AI accelerators, network processors, and custom compute engines. These devices depend on advanced process technology, dense routing, high-performance transistors, complex power grids, and increasingly sophisticated design automation.

But the logic die is only the center of computation; it’s not the full system. The accelerator may execute the matrix operations, tensor workloads, inference engines, training loops, and dataflow schedules, but its usefulness depends on everything around it.

• How fast data can reach it
• How close memory can be placed
• How efficiently power can be delivered
• How heat can be removed
• How signals can escape the package
• How optical or electrical I/O can scale
• How the package can be manufactured and yielded
• How the system can be tested, qualified, and deployed

This is why AI hardware is no longer just a logic-node conversation. The accelerator is the most visible object, but the infrastructure stack, outlined below, is the real product.

1. Memory fabs: HBM becomes part of the compute architecture

AI compute is deeply memory constrained. The value of an accelerator depends not only on peak compute performance, but on how effectively it can access data. This is why memory fabs are central to AI infrastructure.

DRAM, NAND, and especially high-bandwidth memory (HBM) are no longer secondary components in the system. HBM has become part of the AI compute architecture itself. The location, bandwidth, thermal behavior, power profile, and package integration of memory directly affect system-level performance. This changes the role of packaging.

Advanced packaging platforms such as CoWoS, interposers, bridges, and other high-density integration methods are not merely ways to place chips together. They are mechanisms for bringing logic and memory into a physical relationship that conventional board-level integration cannot support.

The memory fab produces the memory device, but the AI system requires memory to be integrated into a bandwidth-dense, thermally stable, mechanically reliable, and yieldable package. That is physical realization.

2. Analog and mixed-signal fabs: The hidden interface layer

AI hardware may appear digital from the outside, but every real system depends on analog and mixed-signal functions. Interfaces, clocking, sensors, converters, retimers, voltage regulators, power management ICs, monitoring circuits, and control loops often come from process technologies very different from leading-edge logic.

These functions are not always glamorous, but they are essential. They help manage signal integrity, power sequencing, telemetry, control, protection, timing, and communication between the digital compute die and the rest of the system. This is one reason mature-node and specialty-node capacity remains important.

Not every device in an AI system belongs on the most advanced logic node. Many functions are better implemented on older, more stable, more cost-effective, or more specialized processes. AI infrastructure therefore depends on both leading-edge and non-leading-edge semiconductor manufacturing. The system is advanced because the pieces work together, not because every piece is manufactured on the smallest node.

3. Power semiconductor fabs: Energy delivery becomes a scaling limiter

AI systems are power-hungry. As accelerators, memory stacks, switch chips, and rack-level systems scale, power delivery becomes one of the central limits. This pulls power semiconductor fabs directly into the AI infrastructure discussion.

Power conversion, voltage regulation, current delivery, board-level power architecture, rack-level distribution, and data-center energy efficiency are now deeply connected to semiconductor scaling. Technologies such as silicon power devices, GaN, SiC, advanced voltage regulators, and power management ICs all become part of the AI hardware stack.

The challenge is not simply generating more compute. The challenge is delivering usable power to the compute fabric with acceptable loss, noise, heat, and reliability. This is where chiplet and package architecture become tightly coupled to power architecture.

The industry can no longer treat power delivery as a board-level afterthought. For high-current AI systems, power is a physical design problem across die, package, substrate, board, rack, and facility. A compute die may come from a leading-edge logic fab, but the system cannot scale unless the power ecosystem scales with it.

4. Compound semiconductor fabs: Efficiency, RF, and high-performance physical interfaces

Compound semiconductor technologies such as GaN, SiC, GaAs, and related material systems are also part of the broader AI infrastructure stack. They are important for high-efficiency power conversion, RF systems, high-frequency communication, and specialized physical interfaces. While they may not sit inside the main AI accelerator, they support the physical infrastructure around advanced compute.

This matters because AI systems are becoming more energy- and communication-limited. As data centers scale, the efficiency of power conversion, the quality of high-speed links, and the ability to move signals across packages, boards, racks, and facilities become increasingly important. Compound semiconductor devices can play a role in those parts of the system.

Again, this reinforces the broader point: AI infrastructure is not a single-fab product. It’s a convergence of many semiconductor technologies.

5. Photonics fabs: Data movement becomes optical

AI scaling is also stressing electrical interconnect. As systems grow from single accelerators to multi-chip modules, boards, racks, clusters, and data centers, data movement becomes a dominant challenge. Electrical I/O remains essential, but optical communication is becoming increasingly important for bandwidth, distance, energy efficiency, and system architecture.

This brings photonics fabs into the AI infrastructure stack. Silicon photonics, lasers, modulators, detectors, waveguides, optical transceivers, and eventually co-packaged optics (CPO) all represent a different manufacturing and integration ecosystem from conventional logic.

But photonic devices alone do not solve the problem. They must be connected to ICs, packaged with optical interfaces, aligned to fiber or waveguides, stabilized against temperature and mechanical stress, tested at the package level, and qualified for product deployment.

This is why CPO is not only a photonics problem; it’s a packaging, thermal, mechanical, electrical, optical, manufacturing, and reliability problem. A photonics fab can create the optical device. But AI infrastructure requires the optical path to become a stable product-scale system.

6. Mature-node fabs: The infrastructure control layer

Mature-node fabs are often underestimated in AI discussions. But AI infrastructure depends heavily on mature-node silicon for control, sensing, power management, monitoring, security, timing, industrial interfaces, and system management. Many of these functions do not require leading-edge process nodes. On the contrary, they may benefit from mature, robust, and well-characterized process manufacturing technologies.

The AI system may be marketed around the accelerator, but it operates through a large population of supporting devices. Controllers, power management ICs, sensors, retimers, interface chips, baseboard management devices, and other infrastructure ICs help keep the system functional, observable, and controllable.

Without this layer, the accelerator is only a powerful device without a complete operating environment. This is another reason the AI era should not be understood only through leading-edge logic capacity.

Advanced packaging as the convergence platform

If many fab ecosystems create the pieces, advanced packaging becomes one of the main places where those pieces converge. This is why CoWoS, CoWoP, chiplets, CPO, interposers, bridges, substrates, wafer-scale integration, and advanced package-to-board transitions are so important.

They are not just packaging formats; they are also physical convergence platforms. They bring together logic, memory, photonics, power delivery, substrates, interconnect, thermal paths, and mechanical constraints into one manufacturable system.

But that convergence is difficult because each technology arrives with different physical requirements:

• Logic needs dense routing and power delivery
• HBM needs high-bandwidth proximity and thermal control
• Photonics needs optical alignment and temperature stability
• Power devices need current handling and efficiency
• Analog interfaces need noise control and signal integrity
• Substrates need dimensional stability, low loss, and manufacturability
• Cooling systems need physical access to heat sources
• Test flows need visibility into the assembled system
• Reliability flows need confidence across materials and interfaces

This is why advanced packaging is not only “putting chips together.” It’s the physical realization layer of AI infrastructure.

Why “one fab” thinking is no longer enough

Traditional semiconductor conversations often separate the world into categories: logic, memory, analog, power, photonics, packaging, board, system. That separation is useful for organization. But it can hide the real scaling challenge: how AI infrastructure forces these domains to interact.

The logic die affects memory placement. Memory placement affects package size and thermal behavior. Thermal behavior affects power delivery. Power delivery affects substrate design. Substrate design affects signal integrity and manufacturability. Optical I/O affects package architecture. Package architecture affects test access, reliability, and yield.

The outcome is a coupled physical system. A limitation in one layer can become a bottleneck for the entire infrastructure platform. This is why the industry needs to think beyond individual fab outputs and toward a connected realization stack.

From device performance to physical realization

Device performance is still important. Material properties are still important. Transistor density is still important. But they are not sufficient by themselves. A material with excellent properties must still be processed, patterned, bonded, inspected, assembled, tested, and qualified.

A photonic device with strong lab performance must still survive package stress, temperature drift, fiber attach, calibration, and product reliability. A power device with high efficiency must still fit into a board, rack, or package-level power architecture. A high-density substrate must still meet warpage, routing, via, reliability, yield, and cost targets.

An AI accelerator with impressive compute density must still receive data, power, cooling, and system-level integration. This is the central shift: The next era of AI hardware will not be defined only by the best device. It will be defined by the best realized system.

The multi-fab physical realization stack

A more complete way to view AI infrastructure is as a multi-fab stack:

• Logic fabs create the compute engines
• Memory fabs create the bandwidth and capacity layer
• Analog and mixed-signal fabs create interfaces, control, and conversion
• Power semiconductor fabs support efficient energy delivery
• Compound semiconductor fabs enable high-efficiency power and high-frequency functions
• Photonics fabs enable optical data movement
• Mature-node fabs provide control, monitoring, and infrastructure silicon
• Packaging and OSAT flows bring heterogeneous devices into one manufacturable platform
• Substrate and materials ecosystems provide the physical foundation
• Thermal and cooling systems keep the infrastructure operational
• Test, reliability, and yield flows determine whether the system can scale

This is the AI physical realization stack. It’s broader than the accelerator, it’s broader than the package, and it’s broader than the fab.

AI infrastructure is a convergence problem

AI infrastructure is often described through the language of compute performance. But the real system is much larger. It’s a convergence problem across fabs, materials, packages, substrates, optics, power, cooling, manufacturing, test, reliability, and yield.

Leading-edge logic remains essential, but it’s only one layer. The AI accelerator becomes valuable when it’s connected to memory, powered efficiently, cooled effectively, packaged reliably, linked optically or electrically, controlled by supporting silicon, and manufactured at scale.

That’s why the next phase of AI hardware should be understood as a multi-fab physical realization stack.

• Different fabs
• Different materials
• Different devices
• Different process technologies
• One AI infrastructure system

The companies and ecosystems that win will not be those that optimize one layer in isolation. They will be those that connect many semiconductor technologies into reliable, manufacturable, and scalable infrastructure.

And for that, material properties are important, device performance is important, and packaging density is important. But physical realization is what makes them valuable.

Dr. Moh Kolbehdari is senior director of IC/packaging at Socionext US.

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• Intel flash move could put wafer-level packages on the map

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Понад 20 тисяч заяв до КПІ! kpi вт, 07/28/2026 - 18:05

For fiscal fourth-quarter 2026 (ended 29 May), Aehr Test Systems of Fremont, CA, USA — which provides solutions for testing, burning-in and stabilizing semiconductor devices in wafer-level, singulated die, and packaged-part form — has reported greater-than-expected revenue of $18.8m, up 83% on $10.3m last quarter and 33% on $14.1m a year ago. Despite this, fiscal full year revenue of $50m for 2026 is still down on $59m for 2025...

Семінар "Якість без кордонів: інтернаціоналізація та транскордонне забезпечення якості у вищій освіті" KPI4U-2 вт, 07/28/2026 - 17:50

The global semiconductor industry is transitioning to the post-quantum cryptography (PQC) era. PQC is changing how digital systems defend against potential mathematical attacks. PQC algorithms are designed to protect against hackers who try to recover secret keys by breaking the underlying mathematics. However, physical hardware attacks can bypass mathematically secure algorithms, even if a PQC algorithm is perfectly implemented.

As organizations migrate to PQC, replacing the cryptographic assets being protected—PQC private keys, root keys, firmware signing keys—becomes costly and complex in deployed devices like automotive electronic control units (ECUs) and industrial or defense systems. When a chip processes post-quantum algorithms, it handles significantly larger key sizes and more complex mathematical operations than legacy cryptography.

This extended processing time and high computational intensity widen the vulnerability window, leaving the silicon exposed to physical tampering such as side-channel attacks (SCAs) and fault injection attacks (FIAs).

Mathematically upgrading to PQC only stops a hacker sitting at a quantum computer miles away. It does not stop a hacker from attempting physical attacks. This is where analog anti-tamper security IP comes into play. Analog sensors provide the first layer of defense to secure the silicon itself by detecting tampering techniques used in physical attacks, such as clock, voltage and temperature attacks, as well as electromagnetic and laser fault injection attacks.

Clock, voltage, and temperature attacks

A clock attack occurs when a hacker alters the incoming clock’s frequency or timing on a chip to cause glitches in an effort to interrupt normal operations and extract sensitive information. A clock attack monitor can be implemented to track the frequency and timing of the clock signal. If there is any unusual activity, an alert would be raised and preventive action taken.

A voltage glitch attack takes place when a hacker tries to tamper with the incoming power supply. Generating voltage drops or spikes can cause errors that impact encryption algorithms and bypass security procedures. A voltage glitch detector identifies when there is an unexpected change in voltage and sets off an alarm to reset or shutdown the system to protect against data loss.

A temperature or thermal attack involves a hacker quickly heating or cooling a device to generate timing or supply errors without having access to the clock signal or power supply. A temperature sensor can check for sudden temperature variations and then apply countermeasures if required.

Electromagnetic and laser fault injection attacks

An electromagnetic fault injection (EMFI) attack is when the hacker tampers with a device using an electromagnetic pulse, so no electrical contact or physical connection to the chip’s pins is required. An EMFI sensor can be integrated into the silicon to detect even small changes in the internal magnetic field on the device and respond swiftly to stop an attack from causing damage.

A laser fault injection (LFI) attack occurs when a laser beam is used by a hacker to induce errors to breach security and corrupt data. An LFI sensor is placed on a chip to monitor specific transient characteristics of a malicious laser pulse. If there are any indications of an attack, then the sensor can ensure that secret keys are erased or the device may be forced into lockdown mode.

PQC’s physical side

As PQC becomes more widely adopted, the frequency and complexity of physical hardware attacks are expected to rise. Whilst the latest cryptographic algorithms may resist quantum computers, hackers will continue to exploit physical vulnerabilities because without robust protection these are often easier than breaking the underlying mathematics.

This looks set to drive demand for analog anti-tamper IP that can detect clock, voltage, temperature, EMFI and LFI attacks, trigger responses such as key zeroization or secure reset if required, complement digital root of trust (RoT) solutions, and strengthen compliance with hardware security requirements in sectors such as automotive, industrial, financial and government.

Analog IP solutions offer a continuous line of defense, including clock, voltage, temperature and EMFI sensors, which complement digital RoT systems. As physical attack routes evolve, adding optical and LFI detection to the physical security envelope will become the benchmark for securing next-generation system-on-chips (SoCs).

While PQC addresses the security of cryptographic algorithms, analog anti-tamper IP protects the physical implementation of those algorithms. As organizations invest in PQC, safeguarding the hardware root of trust and stopping physical attacks becomes an even more critical part of a comprehensive security strategy.

Chris Morrison is VP of product marketing at Agile Analog.

Related Content

• Looming Quantum Threat as PQC Market Expands
• Post-quantum cryptography (PQC) knocks on MCU doors
• Post-Quantum Cryptography Incorporated into SoCs via eFPGA
• The need for post-quantum cryptography in the quantum decade
• Test and Measurement Strategies for QKD, PQC and Hybrid Systems

The post Why analog anti-tamper security IP is crucial in the PQC era appeared first on EDN.