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КПІ ім. Ігоря Сікорського презентував міжнародним партнерам нові ініціативи з гуманітарного розмінування KPI4U-2 вт, 07/07/2026 - 14:02

Міжнародна конференція від Посольства Мальтійського Ордену KPI4U-2 вт, 07/07/2026 - 13:43

Infineon Technologies AG of Munich, Germany says that the Final Determination issued by the Full Commission of the US International Trade Commission (US ITC) on 7 May has been upheld after the conclusion of the 60-day Presidential Review Period. This confirms that China-based Innoscience (Suzhou) Technology Holding Co Ltd (which manufactures GaN-on-silicon power chips on 8” silicon wafers) infringes an Infineon patent concerning GaN technology, resulting in import and sales bans against Innoscience...

It seems as if every technical advance these days is either directly related to AI software and data centers, or at least tries to establish such a connection, even if that connection is somewhat of a tenuous “stretch.” Despite this, there are a lot of innovative and interesting projects underway that are very analog-centric, with little or no AI association. These advances show what “small” analog can do, where small refers to both physical size and focused functionality.

Consider a neural implant dubbed the Microscale Optoelectronic Tetherless Electrode, or MOTE, developed at Cornell University (Figure 1). Measuring about 300 microns long and 70 microns wide (yes, that’s microns), researchers maintain it’s the smallest neural implant capable of wirelessly transmitting brain activity data.

Figure 1 This brain-implantable MOTE measures just 300 microns long and 70 microns wide and requires no tether or wireless RF link for power or data. Source: Cornell University

It’s connected via red and infrared laser beams that pass harmlessly through brain tissue. The MOTE transmits data back using tiny pulses of infrared light, which encode the brain’s electrical signals. An aluminum gallium arsenide (AlGaAs) semiconductor diode both captures light energy to power the circuit and emits light to communicate the data.

The device also includes a low-noise amplifier and optical encoder, all built using the standard CMOS process technology. The optical link uses pulse position modulation (PPM) for its data encoding as that format is very power efficient, especially in this situation (Figure 2).

Figure 2 System overview shows a MOTE implanted in an awake mouse brain to chronically record neural activity in vivo—incoming light powers the MOTE, and the MOTE, in turn, emits the PPM pulses communicating the recorded data (a). Optical microscopy image compares a MOTE with a strand of human hair (b). MOTE is powered and is communicating optically; it’s continuously powered at a shorter wavelength and communicates at a longer wavelength, making the powering system easier to implement and avoiding power–communication crosstalk (c). Source: Cornell University

The dual-use diode, dubbed a photovoltaic light-emitting diode (PVLED), provides space-saving benefits, functioning as both an LED and a data-link transmitter. An external 623-nm LED source provides power to the PVLED, while MOTE emits 825-nm PPM pulses that encode electrophysiological signals.

The diode is used as a photovoltaic for 93.4% of the time and as an LED for 0.06% of the time, with the remainder of the time spent on transitions. By concentrating the transmitted power into short, bright pulses and encoding information in the timing of those pulses, PPM is much more resistant to noise than amplitude modulation and is very power efficient.

Atomic layer deposition (ALD) of SiO2, Si3N4 and Al2O3 encapsulates MOTE against corrosive biological media without substantially increasing its volume (total encapsulation thickness is under 1.5 µm). High-pressure platinum (Pt) sputtering then provides not only favorable electrode impedance but also an effective and conformal light shield to prevent incident light from generating unwanted photocurrents in the electronics. Critically, each fabrication step is done in parallel, simultaneously fabricating close to 100 MOTEs per chip—and scalable to thousands of MOTEs per square centimeter of silicon (Figure 3).

Figure 3 Bulk fabrication of MOTEs (left) integrating two disparate technologies—CMOS (silicon based) and PVLED (AlGaAs based)—and a cross-sectional view (right) of a fully fabricated MOTE illustrating how the ALD dielectrics and sputter Pt together constitute a shield against biological media and unwanted photocurrents. Source: Cornell University

The underlying CMOS circuits provide low-noise amplification, stable biasing and PPM encoding, and drive the PVLED as an LED (Figure 4). Overall power budget is miserly: nominal power consumption is just one microwatt, divided among the amplifier (50.0%), encoder (10.5%), LED driver (26.2%), and support circuits (13.3%).

Figure 4 Systemic description of a MOTE and its external counterpart for communication—MOTE’s output PPM pulses are detected by an external photodiode before being passed through a decoder (a). Schematics of the front-end amplifier based on pseudo-resistors (left) and the charge pump for optical pulse generation shown on the right (b). Power and area distributions of a MOTE in which the amplifier and filter take most of the power for low-noise amplification (left), and the frame and integration overhead for protection against unwanted light and photocarriers take most of the area, as shown on right (c). Source: Cornell University

How well did they do?

By design, incident LED irradiance is limited to less than 70 mW/mm2, well below the allowed threshold of 250 mW/ mm2, which may inflict heat damage in the brain. The team first performed Petri-dish “static” tests before moving on to live rats. The heads of the implanted live mice were “restrained” while computer-controlled motor moved a rod to stimulate a whisker of an awake, head-fixed mouse.

The implant successfully recorded spikes of electrical activity from neurons as well as broader patterns of synaptic activity—all while the mice remained healthy and active. In two of the six implanted mice, they placed MOTEs on the brain surface, from which they were able to measure the electrocorticographic (ECoG) signals; in the other four mice, they inserted MOTEs into the barrel cortex.

As expected, MOTEs captured the neural responses to whisker stimulations and transmitted the neural signal spike. MOTES were left in the test “subjects” for up to 300 days and continued to function, although there was some degradation in performance, which the Cornell researchers attribute to deterioration of the platinum electrodes.

Why even bother with such a project, rather than using conventional “stick-in” electrodes? In addition to the obvious limitation imposed by the associated wired tether or even a wireless interface attached to the rat, one of the motivations is that traditional electrodes can irritate the brain as the tissue moves around the implant and thus can trigger an immune response. Their goal was to make the device small enough to minimize that disruption while still capturing brain activity faster than imaging systems, and without the need to genetically modify the neurons for imaging.

In you want to know more about the project, its circuitry, and the test results on the rats (I didn’t feel the need to go into detail on that!), check out their detailed and highly readable paper “A subnanolitre tetherless optoelectronic microsystem for chronic neural recording in awake mice” published in Nature Electronics.

Whether it’s rat implants or something non-biologic, these projects—with their tight focus, custom die, minimized number of functional blocks, and no frills or features beyond what is absolutely needed—show what analog designs can do in micropower and microsize designs, and that innovative analog design has not reached a terminal point. As the late, great analog designer Bob Pease liked to remind us, “one good op amp can do more than a thousand logic gates.”

Bill Schweber is a degreed senior EE who has written three textbooks, hundreds of technical articles, opinion columns, and product features. Prior to becoming an author and editor, he spent his entire hands-on career on the analog side by working on power supplies, sensors, signal conditioning, and wired and wireless communication links. His work experience includes many years at Analog Devices in applications and marketing.

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The post Neural implant merges photovoltaics with custom analog, PPM encoding appeared first on EDN.

The memory wall is no longer a theoretical concern. It’s the defining bottleneck in today’s AI, automotive, and data center system-on-chips (SoCs). CPUs operate at GHz frequencies with single-digit nanosecond cycle times, yet DRAM latency remains stubbornly at 60─100 ns, and memory-mapped I/O (MMIO) accesses to on-chip accelerators across complex networks-on-chip (NoC) can take even longer.

As SoC designs scale up with more accelerators, larger memory subsystems, and deeper interconnect fabrics, the cost of every cache miss and every device register access grow. No single architectural feature can solve this. It demands a multi-dimensional approach.

This article shares our experience using Google’s FlatBuffers library as a memory subsystem stress test on the Andes AX46MPV RISC-V core. Our evaluation confirmed that outstanding transaction capability delivers significant benefit, up to 39%, when memory accesses are independent, but only 6% under pointer-chasing patterns where hard data dependencies prevent parallelism.

This demonstrates exactly why a single-dimensional solution is insufficient. The Andes AX46MPV addresses memory latency from multiple angles: outstanding transactions to exploit memory-level parallelism when access patterns allow, hardware prefetching to predict and fetch data before the core needs it, and software prefetch support to give programmers direct control over latency hiding.

Together, these capabilities form a comprehensive latency tolerance strategy—ensuring robust CPU performance whether the bottleneck is cacheable DRAM access or uncacheable MMIO traffic across the SoC.

Below are the six key premises that can help design engineers formulate a latency tolerance strategy to ensure robust CPU performance amid memory bottlenecks.

1. The memory wall problem

Modern workloads, such as AI inference, databases, and graph analytics, are memory bound. As mentioned above, CPUs now operate at GHz frequencies with single-digit nanosecond cycle times, while DRAM latency remains stubbornly at 60─100 ns. This gap, commonly known as the memory wall, means a single cache miss can stall the processor for hundreds of cycles, leaving expensive compute resources idle.

The bandwidth–latency paradox

Technologies like high-bandwidth memory (HBM) and DDR5 are engineered for high bandwidth but realizing that bandwidth requires the CPU or GPU to sustain hundreds of outstanding memory requests simultaneously. Without a deep request pipeline, the memory bus sits idle between transactions, wasting the very bandwidth these technologies were designed to deliver. In other words, bandwidth is only as useful as the processor’s ability to keep the memory channel busy.

Beyond AI: The automotive case

The memory wall is not confined to data center workloads. In automotive SoCs, DRAMs are often soldered directly onto the PCB to withstand vehicle vibration. This soldering, combined with PCB routing constraints, can result in longer signal paths and increased DRAM access latency. Therefore, the CPU’s ability to sustain multiple cacheable in-flight requests is also critical in automotive systems.

2. The MMIO dimension: Long latency beyond DRAM

The memory wall problem extends beyond cacheable DRAM to uncacheable MMIO as well. Modern SoCs integrate many peripherals and accelerators, such as AI engines, NPUs, and DMA controllers. The CPU configures and communicates with these devices through MMIO register accesses.

Each MMIO access is uncacheable and must travel on the on-chip bus. If the CPU can only issue one MMIO transaction at a time, programming a sequence of accelerator registers becomes painfully slow. This is a real bottleneck in systems where the CPU orchestrates multiple accelerators and needs to rapidly set up DMA transfers, kick off inference jobs, or poll status registers.

Real-world example: Meta’s MTIA accelerator

A concrete illustration is Meta’s MTIA—Meta Training and Inference Accelerator—which uses Andes RISC-V cores inside each processing element (PE). Within the chip, these cores access system registers and remote PE resources through an on-chip AXI interconnect, using uncached MMIO accesses whose latency varies depending on the physical distance across the grid.

Figure 1 Here is a look at the MTIA platform, the first-generation silicon targeting Meta’s recommendation systems. Source: Meta

The growing NoC latency challenge

As AI chips grow larger and more complex, accelerator blocks are spread further across the die, connected by NoC. An MMIO access to a block on the far side of the NoC can take 50─200+ cycles just for routing, and even longer under congestion. This makes the CPU’s outstanding MMIO transaction capability a meaningful factor in overall system throughput.

3. FlatBuffers: A memory subsystem stress test

We chose Google’s FlatBuffers library not as a representative AI workload, but as a stress test for the CPU memory subsystem. FlatBuffers is an open-source, cross-platform serialization library designed for zero-copy data access, meaning it reads serialized data in place without a separate deserialization step. While this library design is efficient in many respects, it creates memory access patterns that are particularly challenging for CPU caches and memory subsystems.

What makes FlatBuffers demanding

FlatBuffers uses indirect, offset-based data navigation: accessing any field requires reading an offset, computing a field address, and then following that address to the actual data. This results in multiple dependent memory accesses per field lookup.

The read path, in particular, involves classic pointer chasing, which means each access depends on the result of the previous one. The chasing depth is configurable and can be set to a high value (for example, 2,000), meaning the traversal spans far more data than a single cache line can hold.

As a result, cache misses are frequent and unpredictable. Accesses tend to be small and scattered, touching a few bytes at one location before jumping to an entirely different cache line. Combined with extensive small function calls for field accessors, FlatBuffers stresses the instruction cache, branch predictor, and memory subsystem simultaneously.

Figure 2 Read pointers involve chasing in FlatBuffers. Source: Andes Technology

Establishing a performance floor

By evaluating under these deliberately demanding conditions, we establish a performance floor for the CPU. Real-world workloads, which typically exhibit more regularity and spatial locality, can be expected to benefit even more from the core’s architectural features for latency tolerance.

4. What we learned: Outstanding transactions under two access patterns

Our evaluation on the Andes AX46MPV RISC-V core revealed that the architectural benefit of outstanding transactions varies dramatically depending on the memory access pattern, not just the cache miss rate.

FlatBuffer Create: Independent accesses, high benefit

In the FlatBuffer Create kernel, the CPU allocates buffers, writes fields, and builds the serialized data structure. These memory accesses are largely independent of each other; that is, the address of one write does not depend on the result of a previous read. Despite a low DRAM access frequency of just 0.23%—shared cache misses as a proportion of total instructions—the core achieved a 20% to 39% performance benefit from its outstanding transaction capability.

The range depends on how we model the worst case without outstanding transactions. The upper bound of 39% assumes every DRAM access fully stalls the pipeline for the entire memory latency with no instruction overlap whatsoever, which is a deliberately pessimistic assumption. The lower bound of 20% assumes that some instructions can still be executed during a DRAM stall, effectively halving the DRAM access cycles.

The actual benefit likely falls somewhere within this range, but even at the conservative end, a 20% gain from just a 0.23% miss rate demonstrates that when cache misses are independent, the hardware can issue multiple requests simultaneously and continue useful work while waiting. This is the ideal scenario for memory-level parallelism: rare but independent misses that can be fully overlapped.

FlatBuffer Read: Pointer chasing, limited benefit

The FlatBuffer Read kernel tells a very different story. This workload is dominated by pointer chasing. The CPU reads an offset, dereferences it to compute the next address, reads that location, follows the next offset, and so on. Each memory access depends on the result of the previous one, creating a strict chain of data dependencies.

Despite a much higher DRAM access frequency of 1.99%, the core achieved only a 6% performance benefit from outstanding transactions. The small gain likely comes from brief windows where the access pattern allows limited parallelism. Perhaps when reading multiple independent fields within a single FlatBuffer object after resolving its base pointer. But the dominant pointer-chasing pattern fundamentally limits how much latency the hardware is able to hide.

The key insight: Not all cache misses are equal

This contrast carries an important implication for system architects and workload designers. The value of outstanding transaction capability depends not on how many cache misses occur, but on whether those misses are sufficiently independent to be overlapped. Workloads with parallel, unrelated memory accesses can see dramatic benefits; workloads with serialized, data-dependent accesses will see far less improvement, regardless of how many outstanding transactions the hardware supports.

5. Beyond outstanding transactions: Prefetching as a complementary strategy

Outstanding transactions are most effective when cache misses are independent and can be issued in parallel. However, not all workloads exhibit this pattern. When the access pattern has some regularity but not enough parallelism to exploit, outstanding transactions alone are insufficient. This is where prefetching can provide partial relief.

The Andes AX46MPV includes both hardware prefetch and software prefetch capabilities. Hardware prefetching detects regular access patterns, such as sequential or strided accesses, and speculatively fetches data into the cache before the core requests it. Software prefetch instructions give programmers explicit control, allowing them to insert prefetch hints at strategic points in the code where the hardware prefetcher cannot anticipate the access pattern on its own.

Together with outstanding transactions, these prefetch mechanisms form a multi-layered defense against memory latency, each addressing a different dimension of the problem.

6. A multi-dimensional approach to the memory wall

When cache misses occur in a modern SoC, whether to cacheable DRAM or to uncacheable MMIO device registers across a complex interconnect, the resulting latency is a multi-dimensional problem. No single feature eliminates it. The Andes AX46MPV architecture addresses this challenge from multiple angles: outstanding transactions exploit memory-level parallelism when access patterns allow it, hardware prefetching predicts and fetches data before the core needs it, and software prefetch gives developers an additional tool to partially overlap latency.

Our FlatBuffers evaluation makes this concrete: outstanding transactions deliver a 20─39% gain when cache misses are independent, but under pointer-chasing patterns, the benefit drops to 6%. For SoC designers, this underscores a practical truth: understanding your workload’s access patterns is just as important as the hardware features themselves.

For those building the next generation of AI, automotive, and data center platforms, this kind of comprehensive, multi-dimensional latency tolerance is not a luxury. It’s a necessity.

Mia Chang is a solution architect at Andes Technology with more than 10 years of experience spanning semiconductor circuit modeling and CPU synthesis. She works directly with AI compute and automotive customers, performing in-depth kernel-level analysis to uncover performance bottlenecks in real-world system designs.

Author Acknowledgement

This article would not have been possible without the support of several colleagues. The CCBU team carried out the FPGA measurements that underpin our evaluation. Our NA team provided thoughtful reviews and suggestions that helped sharpen this article. Our knowledgeable architect and R&D team behind the AX46MPV were always willing to discuss the questions and challenges we encountered during benchmark analysis with us. Thank you all.

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The post Memory wall: Why cache miss tolerance defines CPU performance now appeared first on EDN.

Українські школярі — на Міжнародній олімпіаді з кібербезпеки та ШІ в Сіднеї kpi пн, 07/06/2026 - 23:53

It is on irfz44n but I will probably change it to irf3205 to reduce heat. submitted by /u/Hlep420 [link] [comments]

Unintended fluids dripping from above? Accumulating from below? The T300 alerts you to them all. And mysteriously threaded contacts suggest other uses, too.

Back in March, I covered the activation and ongoing usage impressions of three interrelated TP-Link smart home devices: the Tapo H100 smart hub:

display-inclusive Tapo T315 hygrometer:

and Tapo T300 smart water leak sensor:

Toward the end of that March piece, and reiterating a quote I’d initially included in a mid-May follow-up post, I wrote:

I’ve also got a redundant Tapo H100 smart hub and T300 smart water leak sensor, both sitting on the shelf, queued up for teardown, along with a display-less sibling of the T315 hygrometer, the Tapo T310 Smart Temperature and Humidity Sensor:

The Tapo T310 was tore down and analyzed within that same mid-May writeup, with the teardown of the Tapo H100 predating it in late April. And now, in early July, we’re completing the dissection triumvirate with the spare Tapo T300, which I as-always aspire to return to fully functional form post-disassembly for ongoing leak-monitoring use somewhere in the residence.

Revisiting past history

You already saw a set of box and other real-life shots for the sibling Tapo T300 in the initial mid-March entry in this series (assuming you read it, that is); that particular unit now resides at the base of my downstairs water heater. The “dumb” leak sensor previously at that location now sits below the also-downstairs whole-home water filter; another is at the back of my icemaker-augmented combo refrigerator/freezer in the kitchen.

As usual, I’ll start out with some outer box shots, also as usual accompanied by a 0.75″/19.1 mm diameter U.S. penny for size comparison purposes.

This last image of the bottom of the package reveals (among other things) the hardware version (v1.6, succeeding the original v1, as well as with its own v1.8 successor) and serial number:

The hardware version matches that of the Tapo T300 currently in use, although serial numbers differ (of course). Here’s a revisit of the associated box-bottom shot you saw in March:

Open sesame

Let’s see what’s inside:

starting with a sliver of quick-start literature (PDF…here are the accompanying full user guide and datasheet) and some protective foam:

Here’s our patient, still swathed in a translucent protective sleeve:

And now unclothed, once again echoing sibling-device images you saw back in March:

As before (referencing the packaging photos), with the exception of this bottom shot:

versus this differing-serial-number vantage point of the in-use sibling device:

in both cases (and in contrast to the bottom-perspective packaging precursors) now including the always-informative common FCC ID (2AXJ4T300).

The Tapo T300 comes already battery-equipped, as you’ve probably already ascertained from the translucent strip of plastic that begs for removal prior to first-time use, but a power-source swap will sooner-or-later be necessary (“up to three years” before replacement is the claim). The removal of two screws should gain us access to the battery compartment:

Toldja so (there’s two AAAs/LR03s inside):

Next up, four screws, one in each corner, this time with hex heads:

We have liftoff

And with them removed, the two sections of the case separate straightaway, with no further implements of destruction or elbow grease required:

The inside of the bottom portion is largely unmemorable. Nice gasket, though, for likely-already-obvious liquid-intrusion-prevention purposes (IP67). Speaking of liquids, note the four metal pass-throughs, one on each corner, originating with the bottom-side contacts you saw earlier:

The other, larger portion is much more interesting (IMHO, at least):

Leak warning-sound transducer aka “buzzer” (claimed 90 dB!) on the side:

Let’s get that PCB outta there. Removing two more screws should do the trick:

That’s what I’m talkin’ about:

Toward the right are a pair of additional feed-through contacts from the top, intended to catch drips coming from above (vs. already-pooled fluids from below in the prior four-contact case). In the middle is a visible-light pass-through originating at the multi-color multi-function status LED, which I’m betting we’ll see shortly. And at left is the mechanical button portion of the topside control switch. The buzzer on the side, fed by the red-and-black two-color wiring harness, you’ve already met, right?

Simply simple

Now for the PCB itself, beginning with the bottom side, you’ve already glimpsed in past shots.

The proximity contacts for the previously pointed out bottom-side contacts are in the corners, labeled P11-P14. Two of the four battery terminals are here; you might have already noticed that the other two are attached to the case itself. And although at first glance, I’d thought the sizeable cylinder on the left edge was an electrolytic capacitor, the “L323” PCB marking next to it suggests otherwise (analog experts: is this what’s known as a “radial inductor”?). Note, too, that the D6 diode site below and to its right is unpopulated, seemingly, unless my eyes are playing tricks on me.

Now for the more interesting (IMHO) topside (which, bafflingly, is screenprinted “BOTTOM”):

Dominating the landscape at left is the PCB mounted portion of the aforementioned control switch. Below and to its right is a sixteen-lead square IC labeled as follows (I “think”…the “S” and “5” symbols aren’t distinctly different):

300A
S906
S15

Readers’ suggestions as to its identity and function(s) are welcomed. My bet is that, as with the Tapo T310 Smart Temperature and Humidity Sensor, it’s another obscured-marking CC1 series-variant of Texas Instruments’ MSP430 embedded controller family, for (among other things) “Sub-1 GHz dual-band” wireless connectivity. More on that connectivity bit in a moment.

Above and to its right, and at the PCB center, is the status LED. To its right is another, larger IC, this one more easily identifiable; it’s the same Cmsemicon BAT32G135GE application processor that I’d found in the earlier Tapo T310 Smart Temperature and Humidity Sensor teardown. To its right are two more landing pads, labeled T9 and T10 and this time corresponding to the earlier noted topside-located drip-sensing contacts.

And above the entire circuitry assemblage is ANT5, the embedded antenna for the company’s proprietary ultra-low power wireless protocol. Since this application’s data rate (as with hygrometry) is low, unlike with a smart camera (for example), additional Wi-Fi connectivity isn’t necessary in this case.

Speaking of sides, I’ll wrap up for today with four more PCB perspectives related to its backside, since that’s where the bulk of the “vertical” parts are located.

Along with one other tidbit that I came across during my research. You might have already noticed that two of the four contacts on the bottom of the device aren’t solid; instead, they seemed to have unfilled (not to mention M2 screw-threaded) centers. You’d be spot-on with that observation, although nothing I’ve found in the product documentation explains why.

Well, this guy (or gal; dunno) used them to transform the Tapo T300 into a door open/close sensor. If it wasn’t already obvious, the Tapo T300 doesn’t directly leverage a moisture sensor, as a hygrometer does (for example). Instead, it detects normally absent current flow between any of the three paired sets of two contacts, interpreting that conductivity as evidence of fluid presence. The switch used in this creative design derivation, in its “closed” position, generates the same current flow. And this same concept can also be employed for other purposes. Nifty!

Over to you for your thoughts in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

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• Smart hygrometers: Still largely useful even without integrated visual monitors
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• Tapo or Kasa: Which TP-Link ecosystem best suits ya?

The post TP-Link’s Tapo T300 sensor detects water and other liquid-leak dangers appeared first on EDN.

Artificial intelligence (AI) may dominate today’s conversations about smart cities and autonomous mobility, but beneath the pavement lies a technology that has quietly kept traffic flowing for decades. Inductive loop detectors (ILDs)—simple wire coils paired with reliable electronics—continue to deliver dependable vehicle detection, enabling adaptive traffic lights, toll systems, and roadway monitoring.

In a landscape buzzing with AI-driven vision and radar, ILDs stand out as the proven, resilient infrastructure that provides clarity and consistency, reminding us that not all progress depends on novelty—sometimes it rests on steady signal amid the noise.

Applications of inductive loops

In principle, an inductive loop (or induction loop) is an electromagnetic detection system that uses a moving magnet or an alternating current to induce an electric signal in a nearby wire. They are widely applied in transmitting and receiving communication signals and are also integral to hearing-assist devices, where audio signals are magnetically transmitted directly to compatible hearing aids, improving clarity in public venues such as theaters, lecture halls, and places of worship.

Inductive loops also play a crucial role in vehicle detection—embedded beneath road surfaces, they sense the presence of cars and trigger traffic lights or vehicle presence indicators. In addition, they serve in metal detectors and other object-sensing applications, but their impact on accessibility and traffic management makes them especially vital.

The rest of this post deals with inductive loop vehicle detectors.

Inductive loop vehicle detectors

Among current vehicle detection technologies, the inductive loop system remains the industry standard due to its optimal balance of performance, reliability, and cost-effectiveness.

At their core, inductive loop detectors operate by sensing changes in inductance when a metallic object disturbs an electromagnetic field.

This field is generated by a cable loop embedded directly into the roadway; as a vehicle passes over, it alters the coil’s inductance, triggering a detection signal. These systems provide the essential control logic for automating infrastructure, such as operating gates and traffic barriers, managing signal timing at intersections, or dispensing tickets in parking facilities.

Figure 1 A vehicle induction loop presence detector triggers gate mechanisms and logs traffic data for access management. Source: Roger Trade Centre

The system comprises two primary components: the sensing element and the electronic module. The sensing element consists of a wire coil buried within the pavement and a lead-in cable with the loop’s specific geometry defining the boundaries of the detection zone. The electronic module connects to this loop to monitor electromagnetic changes that indicate a vehicle’s presence.

Once a vehicle is detected, the module processes the resulting data according to its specific programming. This information can be acted upon immediately to trigger traffic signals or automated gates, stored locally for subsequent traffic pattern analysis, or integrated as a critical data point into a larger, networked management system.

Furthermore, the physical installation of the sensing element requires a saw cut, which involves milling a narrow groove—typically 1 to 2 inches deep—directly into the asphalt or concrete. Once the wire coil is laid within this channel, the slot is filled with a specialized loop sealant to protect the hardware from moisture and traffic-induced stress.

While this method enables precise placement and easy retrofitting on existing roads, the integrity of the saw cut is vital. Any degradation in the sealant or shifting in the pavement can lead to wire breakage, resulting in system failure or “ghost” detections.

Figure 2 A basic sketch illustrates an inductive loop vehicle detector system. Source: Author

More inductive loop vehicle detector essentials

Over the years, engineers have experimented with various inductive loop geometry configurations to optimize vehicle detection. While early designs were constrained by the limitations of rudimentary electronics, modern technological advancements have rendered many of those barriers obsolete.

This evolution necessitates a reevaluation of traditional standards to accommodate the sophisticated configurations now in widespread use. Today, selecting the ideal geometry requires a comprehensive analysis of site-specific parameters, including adjacent lane interference, the required detection zone area, the specific vehicle types being monitored, and the physical distance between the loop and the electronics module.

In practice, these loops are deployed to capture two primary types of data: presence and passage. Presence detection—monitoring a vehicle within a specific zone or lane—typically requires loops with larger surface areas. Conversely, detecting the passage of a vehicle over a specific point is best achieved using a single, smaller loop.

Once geometry is established, the next critical factor is the number of turns. While the geometry defines the physical detection zone, the number of turns dictates the loop’s inductance value. It is essential to account for the lead-in cable’s inductance, as it contributes to the total input inductance of the system. Engineers must balance these values carefully, as decreasing the loop inductance below recommended thresholds can significantly compromise system stability.

Furthermore, it’s important to note that a vehicle passing over a small portion of a large loop generates a significantly smaller change in inductance than it would when passing over a smaller loop. For maximum system reliability, the detector must be able to register the greatest possible change in inductance when a vehicle enters the detection zone.

Since the detector monitors an inductance shift that is directly proportional to the percentage of the loop area displaced by a vehicle, smaller loop areas inherently provide higher sensitivity. Consequently, when wide-area coverage is required—such as along large gates—multiple smaller loops are often connected to a single detector channel rather than using one oversized loop.

When connecting multiple loops to a single channel, it is standard practice to use identical loops. These loops should share the same dimensions, shape, and number of turns. Maintaining uniform inductance across all connected loops ensures a consistent level of detection sensitivity across the entire monitored area, preventing “dead zones” where a vehicle might go undetected.

For the sake of brevity, this discussion omits foundational concepts such as fundamental inductive theory, loop phasing, and detection height considerations. Furthermore, specialized topics—including the cancellation of undesired magnetic fields through twisted-pair wiring—are left as a subject for further study for those voracious readers seeking a more exhaustive understanding of the underlying physics.

Now, let’s look at some practical pointers for the circuit design notebook.

Practical design pointers

You can build an inductive loop vehicle detector prototype by embedding a wire coil in the roadway and monitoring its inductance. The coil functions as part of a high-frequency oscillator; when a metallic vehicle passes over the loop, it induces eddy currents that decrease the loop’s inductance. This causes a measurable shift in the oscillator’s frequency, which a microcontroller can then process to reliably detect the vehicle.

Success in loop design hinges on balancing sensitivity with environmental stability. Start by documenting the specific loop geometry and the gauge of the wire used, as these factors directly dictate the magnetic field’s reach.

It’s also essential to log the chosen operating frequency; ensuring your system stays within the recommended frequency range for your specific hardware helps avoid interference from nearby power lines or electronic equipment. Finally, always record the layout of the lead-in cables, ensuring they are tightly twisted to minimize noise, and note the pavement conditions to account for any metal reinforcement that might dampen the detector’s response.

As a quick design starting point, you can utilize a Colpitts oscillator built from standard components. The oscillation frequency—typically ranging from 30 kHz to 150 kHz—is determined by the capacitor values and the inductance of the coil windings. The oscillator output is then fed to a microcontroller, which measures the frequency to determine whether a vehicle has been detected.

For better stability, it is recommended to isolate the wire loop from the sensor electronics using a 1:1 ratio isolation transformer, though this is not strictly mandatory. It’s easy to find inspiring design ideas similar to this all over the web.

It’s worth trying a directional loop setup to track traffic flow more accurately. By tracking the activation sequence of two independent sensors, a directional logic loop detector identifies which way a vehicle is headed. The system registers movement based on which loop is tripped first, allowing it to differentiate between opposing flows of traffic.

This capability is particularly useful for shared entrance/exit points in parking facilities and alerting systems to wrong-way drivers on highway ramps. Moreover, these detectors often automate barrier gates, initiating an “open” command for traffic arriving from one side and a “close” command for those departing from the other side.

Figure 3 A directional logic loop detector tracks vehicle direction by monitoring two separate loops. Source: Author

Closing the loop

Inductive loop vehicle detectors prove that even in a world obsessed with complex sensors, the fundamental laws of electromagnetism remain the gold standard for reliability. While computer vision and LIDAR grab the headlines, these buried wire loops continue to quietly power our infrastructure with unmatched precision and weather resistance.

For engineers and makers out there, this technology is a playground of untapped potential—whether you’re optimizing urban traffic flow or building an automated entry system for your own workshop. Don’t just settle for off-the-shelf solutions; grab a spool of wire, dive into the physics, and start prototyping your own detection systems today.

Let’s see what kind of smarter, more responsive world you can build from the pavement up.

T. K. Hareendran is a self-taught electronics enthusiast with a strong passion for innovative circuit design and hands-on technology. He develops both experimental and practical electronic projects, documenting and sharing his work to support fellow tinkerers and learners. Beyond the workbench, he dedicates time to technical writing and hardware evaluations to contribute meaningfully to the maker community.

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Had to add the entire power circuit components as my original Mac (2TB) didn't have any on the other side. Took a lot of research and time (~12hrs), won't go into too much detail. submitted by /u/arduinoRPi4 [link] [comments]

Now I can check small devices such as LEDs, relays and something! I'm so proud of myself because it is works and nothing exploded! Features: variable output voltage(0 to 15V) with graphical display. Used old laptop power supply(19V 2.3A). P.S. schematic on the last photo submitted by /u/IvanIsak [link] [comments]

submitted by /u/OkParsley6142 [link] [comments]

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⚙️ Engineering Project Sprint 2026 (EPS): відкрито реєстрацію KPI4U-2 сб, 07/04/2026 - 10:14

Infineon Technologies AG of Munich, Germany says that the District Court Munich (Landgericht München I) has ruled in favor of it in another patent infringement case concerning gallium nitride (GaN) technology between it and China-based Innoscience (Suzhou) Technology Holding Co Ltd (which manufactures GaN-on-silicon power chips on 8” silicon wafers)...

China-based Innoscience (Suzhou) Technology Holding Co Ltd (which manufactures GaN-on-silicon power chips on 8” silicon wafers) says that Infineon Technologies AG of Munich, Germany was forced to remove certain gallium nitride (GaN) products from its exhibition booth at electronica China 2026 in Shanghai after the products were identified by Innoscience as being subject to a Chinese court injunction prohibiting their sale, offer for sale, and importation into mainland China. The removal took place during the exhibition following intervention by the on-site intellectual property dispute mediation authorities...

Stress exceeding the levels prescribed in absolute maximum ratings specifications may lead to chip malfunctions. Key word: may.

Within the last decade, I was the head of a captive tier 1 automotive embedded electronics department for a global vehicle supplier. Our job was two-fold: on the one hand to build electronic units for our own vehicles whenever an external tier 1 could not meet our price and time-lines, and on the other hand to support external tier 1 companies as well as our own vehicle engineers to deliver robust and first-time right solutions.

Do you have a memorable experience solving an engineering problem at work or in your spare time? Tell us your Tale

Our vehicle engineering team was in the process of doing final testing of a prestigious export consignment of buses destined for a UN peace-keeping mission. A initial batch of two hundred buses were undergoing on-road tests when we discovered that around twenty of them were exhibiting electronic cabin climate control subsystem malfunctions.

This particular subsystem had been developed by a globally reputed tier 1 supplier. Their engineering team was promptly summoned to troubleshoot and fix the problem. Unfortunately, the initial troubleshooting progressed for two weeks without any desired outcome. Finally, we as in-house electronics experts were asked to intervene and rescue the seemingly intractable situation.

Their team leader described the associated circuit block that was a suspected culprit as follows:

A three terminal low-dropout regulator (LDO) with a fourth enable pin is used to power the climate control logic. Whenever we wish to reduce drain on the battery by turning off the climate control system, the LDO is disabled by deactivating the fourth enable pin. Unfortunately, this LDO is misbehaving in all the twenty malfunctioning buses. Their “enable pin” always remains disabled internally, shutting off the output!

“What is your diagnosis?,” we asked. “Your vehicle environment is full of transient spikes reaching up to 70 volts,” he countered. “We have tied the enable pin through a resistor to the 24 V battery bus. No wonder the LDO is refusing to work, since its rating is exceeded.”

“You need to clean-up your vehicle transients to ensure the health of our system,” he advised, showing us a report issued by a certified laboratory. “Our control unit has passed the automotive transient burst tests as per international automotive transient norms. If our design was erroneous, our unit should have failed during the transient test.”

In summary, according to him, our vehicle was inflicting worst transients than those prescribed in automotive test transient specifications. I went through the supplier’s schematic, along with the LDO datasheet. The latter document clearly indicated that the absolute maximum rating for the enable pin was 45V DC. Like all datasheets, however, it also cautioned engineers that any stress exceeding the levels prescribed in the absolute maximum rating may lead to chip malfunction.

I pointed out the datasheet note, explaining to him that a transient suppressor in his circuit was needed to limit external transients to below 45V. My team immediately set to work, installing external transient suppressor units in each bus so that the consignment could be released overnight. But the supplier engineers were not convinced, repeatedly pointing out the claimed “passed” conclusion from the test laboratory.

Automotive global transient test norms specify an acceptance criterion as follows:

• The unit should first pass an in-advance functional test
• The unit can now undergo a “transient burst” test that bombards the power bus with spikes as high as 150V
• The unit should then again pass the same functional test as prior

Note, however, that an absolute maximum rating of 45V is applicable to the worst-case rated LDOs in the field. In contrast, the majority of the chips withstand much higher voltages during operation. This explained why a majority of the buses did not suffer from the malfunction. When a supplier submits samples to the laboratory, test agencies do not test “violation of absolute maximum rating”. They only apply the acceptance criterion in terms of successful functional tests both pre- and post-transient test.

But the supplier engineering team was not prepared to accept above argument. “If you don’t agree with us, let’s meet again tomorrow. This time, please also bring with you the LDO supplier’s application engineer. Both of you should declare in one voice that your circuit does not violate absolute maximum ratings. We have no time to argue now; we need to expedite corrective measures overnight.”

The next morning, we met again with the the climate control supplier engineer, this time also including the semiconductor application engineer in the discussion. The semiconductor engineer confirmed our understanding, much to the dismay of the supplier engineer. Our buses were happily dispatched to their destination after adding necessary protection units and are running without problem to this very day.

Let me summarize the lessons and insights from this case study, which I also frequently share with my automotive clients and trainees:

• An absolute maximum rating of, say, 45 volts does not mean that all chips would get destroyed at 46 volts and beyond. That said, other chips’ operating life may, however, still be reduced.
• Understand the limitations of engineering tests based on visual observations of correct functionality for electronic units. The unit may be violating datasheet limits, ratings, operating conditions etc., but may still seem to be working flawlessly.
• An accurate way to ensure robust and flawless behavior across a mass-produced population of units is to record voltage and other electrical signatures in a laboratory for key circuit points. Doubly ensure that the same is not violating any data sheet limits.
• It is good engineering practice to jointly audit key circuit blocks with the assistance of authorized chip application engineers. Most semiconductor companies are happy to do so, since it preserves their field reputations. They will also gladly prescribe proactive measures to strengthen circuit designs in order to avoid subsequently facing “field surprises” such as this incident.

Vishwas Vaidya is a graduate of the Indian Institute of Technology in Delhi, India. Currently, he is self-employed as an engineering consultant and industry faculty member in the field of embedded systems for global automotive clients and high-repute academic institutions. Vishwas’ articles and research reports have appeared in many worldwide engineering publications.

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Applications in the AI era are memory starved. They need more capacity and, in many cases, more effective memory bandwidth than traditional server designs. Generative AI and large language models (LLMs) store trillions of parameters that must be accessed frequently. And real-time inference for translation, chatbots, and similar services demands low-latency memory paths.

Larger memory footprints enable bigger batch sizes, improving training and inference efficiency. However, while the fastest memory sits on die—in CPU caches—capacity there is inherently limited. For decades, systems have relied on double data rate (DDR) interfaces for high-capacity, relatively low-latency off-chip memory.

Adding more DDR to a CPU, however, runs into hard limits: each interface consumes scarce I/O pins (288 pins on modern DDR4/DDR5 modules), demands strict signal integrity at ever-higher data rates, and carries significant cost. An alternative that has gained real traction is Compute Express Link (CXL) Type 3 memory expanders—devices that attach over a CXL link and present additional system memory to the host.

CXL is a cache-coherent interconnect that lets a CPU access device-resident resources with semantics closer to memory than traditional PCI Express (PCIe) peripherals. A Type 3 memory expander exposes DRAM (and, in some designs, other media) as byte-addressable memory that firmware and the operating system can map and allocate like conventional RAM—after discovery, decode programming, and policy setup.

The critical implication for bring-up and validation is that this memory is logically host-visible yet physically and administratively distinct from local dual inline memory modules (DIMMs). That distinction affects discovery, non-uniform memory access (NUMA) topology, performance, and error-handling paths through firmware and the OS.

Figure 1 The memory-latency pyramid describes relative ordering and validation implications. Source: arXiv

The memory latency–capacity pyramid

System memory is best understood as a latency–capacity pyramid. Small, fast, most expensive structures—CPU caches—sit at the top. Larger, slower, progressively cheaper tiers sit below; local DRAM, then expansion memory, and then I/O-backed storage. Absolute nanoseconds vary by CPU generation, CXL version, link width, topology (direct attach versus retimer or switch), firmware tuning, and contention; the pyramid describes relative ordering and validation implications, not a single fixed latency table.

Local DDR, typically attached near the CPU socket, offers the lowest DRAM access times the OS sees for general-purpose allocation. CXL Type 3 expander memory is DRAM-class and byte-addressable from software’s perspective, but it’s reached across a CXL fabric hop (often with additional buffering and coherency handling).

It therefore sits below local DDR—higher average and tail latency, sometimes behaving like “far memory” in NUMA terms. In other words, imaging CPU 0 accessing DDR memory is attached to CPU 1 in the system, as shown in Figure 2.

Figure 2 Here is a typical two-socket system with a CXL memory expander device attached to CPU 0 via a Gen5, x16 CXL bus. Source: Author

For bring-up, that placement matters as correctness tests may pass while performance and quality-of-service (QoS) tests fail. Workloads with pointer chasing, fine-grained random access, or strict tail-latency budgets are the first to expose suboptimal placement, interleaving, or contention.

Storage and networked memory (NVMe, RDMA, and similar) form the broad base of the pyramid with much higher latency and usually block or page semantics. CXL memory is not in the same tier as SSDs, but it’s meaningfully different from local DIMMs for latency-sensitive software. On a typical two-socket system, the access latency of DDR behind a CXL device can be comparable to accessing DDR attached to the adjacent CPU—a useful mental model when setting performance expectations.

Platform prerequisites: A cross-layer contract

Whether CXL Type 3 memory becomes reliably visible, addressable, and serviceable depends on aligned support across the stack: CPU CXL capability and enablement; system BIOS/firmware support for discovery, decode, and ACPI tables; kernel CXL enumeration and memory management; and expander device firmware for DRAM training, HDM reporting, and mailbox/DOE services. All layers must agree.

Consider CXL Integrity and Data Encryption (IDE); it requires CPU support, BIOS enablement, and device firmware support to be usable end to end. Similarly, the kernel needs a CXL-aware path to recognize the device class, bind memory resources, and transition capacity to an online state the allocator can use.

Reliability, availability, and serviceability (RAS) matter equally. Corrected and uncorrected error notifications must propagate from hardware through firmware to OS subsystems that can log, isolate, or offline affected regions. Because behaviors evolve quickly across kernel releases, validation plans should treat OS version, configuration (huge pages, numactl policies, memory mode), and boot/firmware settings as explicit test variables. Failures are often misattributed to the expander when the root cause is a policy or enablement gap.

Host-managed expander memory generally relies on the in-kernel CXL/memory management stack rather than a monolithic device-specific driver, though platform integrations may include monitoring agents, telemetry exporters, or hardware management interfaces that affect how engineers observe link state, temperature, power, and error counters during bring-up.

Linux and the NUMA story

On Linux, a Type 3 memory expander normally appears as a PCI/CXL function. In upstream kernels with CXL support enabled, the in-tree cxl_pci module is the default bind target. A stock Type 3 host-managed device (HDM) endpoint typically comes up under cxl_pci rather than a vendor-specific host driver for basic enumeration.

The cxl_pci module is PCI-facing glue: it attaches to the device, brings up CXL.io access (including the configuration mailbox), and registers the endpoint with the CXL core so the rest of the stack can expose memory devices to the OS.

In a NUMA machine, the operating system groups CPUs and memory into nodes and treats local memory as cheaper than remote memory. DRAM next to a socket is usually the lowest-latency memory for CPUs in that socket, so the scheduler and allocator try to keep threads and pages on nearby nodes (subject to policy).

CXL Type 3 expander memory is still host-coherent and byte-addressable, but it’s physically and topologically distinct from local DIMMs. Platforms and operating systems therefore commonly expose expander memory ranges as a distinct NUMA node, or as memory with different affinity and distance metadata in ACPI proximity hints. The same application binary can run correctly while performance changes sharply depending on where pages are allocated and whether threads migrate across sockets.

For CXL bring-up and validation, the NUMA story is central. Issues often appear as unexpected remote access or imbalanced bandwidth rather than hard functional failures. Engineers must verify not only that memory is online, but that placement and distance metadata match the intended system topology.

What comes next

Part 2 of this series introduces the user-space tooling ecosystem—cxl/libcxl, ndctl, daxctl, numactl, and topology helpers—and traces the full boot sequence from slot power and DRAM training through DVSEC discovery, decode programming, CDAT delivery, ACPI table handoff, and OS driver binding. Part 3 turns to practical test and debug: interpreting lspci output, validating HDM ranges, exercising CXL-attached memory with numactl, and selecting bandwidth and stress tools for validation gates.

Together, these three parts provide a vendor-neutral, OS-focused playbook for engineers, bringing CXL Type 3 memory expanders from first power-on to production-ready validation.

Ameet Sanghavi works in post-silicon validation for PCIe and CXL at Nvidia with a focus on interface bring-up and validation on shipping products. He has worked on PCIe since 2005 (from PCIe 1.1 onward) and on CXL since 2020 (from CXL 1.1 onward).

Editor’s Note

This is Part 1 of the mini-series on CXL Type 3 memory technology. Part 2 of this series introduces the user-space tooling ecosystem. And Part 3 turns to practical test and debug work.

The views and content of the article are the author’s own and not affiliated to any of his current or previous employers.

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The post Why CXL Type 3 memory matters, what your platform must provide appeared first on EDN.

Converting frequency signals to loop current signals creates an economical result for process industry applications.

Process industry applications commonly employ multiple motors. Their speeds are monitored by tachometers using magnetic pickups from gear wheels mounted on the motors’ shafts. The tachometers produce pulses whose frequencies are proportional to their speeds. Local displays of speeds is generally done by counter/timer-based LEDs or LCDs.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Special modules incorporating expensive counter/timers find use for recording these speeds in control room-based programmable logic controllers (PLCs) and more complex distributed control systems (DCSs). Shielded cables are necessary to carry these pulse signals to the control room, as the signals may induce noise in adjoining cables carrying conventional analog signals. Such an approach is expensive. A more economical alternative solution would be to convert each frequency signal to a 4-20 mA  loop current signal and then transport it to the control room using less expensive cables like those carrying analog signals. Figure 1’s circuit does exactly this.

Figure 1 In one switch SW1 position, this circuit converts 0-50 kHz frequency signals to 4-20 mA loop current alternatives. In the other switch position, the circuit converts 0-5V into 4-20 mA loop current.

The frequency to voltage conversion circuit discussed here is based on an industry-standard LM2907 IC. This chip is extensively used in automotive applications and hence is easily available and inexpensive. It needs only three components to set the basic relationship between frequency and voltage. It uses a charge pump circuit to convert frequency to voltage.

• V output = Vcc*F*R*C (In Figure 1’s circuit, R=R5, C=C4)
• U2 is wired to give a 12 V output, which is fed to the circuit. F is pulse frequency.
• With Vcc as 12V and substituting the component values shown in the circuit, the voltage output works out to 0.264V/KHz.

Exact values for R5 and C4 are not necessary; approximate values are sufficient. The signal is amplified by U1B so that a voltage relationship of 1V/KHz is obtained by tuning potentiometer RV1. C5 filters ripples; increasing its value filters ripples more effectively but also increases the response time. The portion of the circuit surrounding U3 converts 0 to 5KHz into 0 to 5 volts.

The remaining portion of the circuit converts 0/5V into 4/20 mA loop current. R2 determines the “zero” current of 4 mA. If an exact-value resistor is not available, R2 may be replaced with a potentiometer. R13 determines the current span value. Again, if an exact-value resistor is not available, it can be replaced with a potentiometer.

The current going through R2 plus the current going through R13 must be equal to current through R4, as these currents are at the + input of operational amplifier U1A, whose -ve input is grounded. A detailed description of a loop current converter with governing equations can be found in my earlier Design Idea “A 0-20 mA source current to 4-20 mA loop current converter”.

As a bonus, this circuit converts 0-5V into 4-20mA loop current by flipping switch SW1 to the alternative 0-5V input position. Multiple industrial sensors and transmitters generate 0-5V outputs for the parameters they monitor. This circuit may be used to comfortably connect such sensors and transmitters to PLCs and DCSs. Linearity and accuracy are primarily dictated by the LM2907 IC. A simulation study of this circuit indicates accuracy of better than +/- 5%.

Jayapal Ramalingam has over three decades of experience in designing electronics systems for power & process industries and is presently a freelance automation consultant.

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Solid-state drives (SSDs) are among the evolutionary success stories of modern computing. They replaced spinning disks, eliminated mechanical bottlenecks, and enabled the high-speed data access that today’s applications depend on. Plus, they fit into ever-smaller form factors, which we all love.

But as workloads evolve—especially with the rise of edge AI—SSDs are bumping against a critical limitation: heat.

What was once a distant consideration has become a frontline performance constraint. Today’s SSDs are faster, denser, and more heavily utilized than before. And the devices they live in—ultrabooks, tablets, gaming handhelds, and emerging AI-enabled wearables—are thinner, more compact, and often fanless. This clash of trends is creating a perfect thermal storm.

The forecast is ominous—both for consumers and system designers. SSDs will continue buckling under real-world workloads; they’ll throttle data speeds when things get hot; and users will pay the price in diminished performance.

But there must be a cooler way out.

The new reality of sustained workloads

Historically, many storage workloads—the read/write patterns of moving data—were burst-oriented. Opening files, launching applications, and saving documents created short spikes in activity, followed by idle periods that allowed components to cool. Under these conditions, passive thermal solutions such as heat spreaders, vapor chambers, and thermal pads were sufficient.

That’s no longer the case.

Modern workloads, particularly those driven by AI, are sustained and data intensive. Running local LLMs requires loading gigabytes of parameters from storage into memory. AI-powered photo and video editing tools generate continuous read/write cycles during rendering and export. Even gaming has evolved, with real-time asset streaming and procedural generation placing constant demands on storage subsystems.

They are prolonged, high-throughput operations that keep SSD controllers and NAND flash memory active for extended periods. And that changes everything.

Thermal throttling: Hidden performance killer

SSDs are designed with thermal safeguards to prevent damage. Most standard, high-speed controllers begin to throttle performance when temperatures reach approximately 70°C to 80°C. Once that threshold is crossed, the drive reduces its speed to lower heat output.

From a reliability standpoint, this is essential. From a performance standpoint, it’s detrimental. In practical terms, thermal throttling of SSDs can reduce throughput by 20% to 30% or more. A drive capable of delivering 2.0 GB/s may drop to 1.5 GB/s under sustained load. For users, this translates into longer file transfers, slower application performance, and increased latency in AI-driven tasks.

Usually, such performance degradation is unpredictable. And in edge AI applications, where consistent performance is critical, this variability can be unacceptable.

Why passive cooling is no longer enough

The root of the problem lies in the limitations of passive cooling. Passive thermal solutions are designed to spread heat away from hotspots, redistributing it across a larger surface area. This can delay temperature spikes and improve short-term performance, but it doesn’t actually remove heat from the device.

In compact, sealed systems where SSDs operate, heat accumulates over time. Without airflow to carry that heat away, temperatures inevitably rise until throttling occurs.

This challenge is exacerbated by modern device design. In many ultrathin laptops and handheld systems, SSDs are positioned near CPUs, GPUs, and other heat-generating components. The thermal environment is already saturated, leaving little headroom for additional heat dissipation.

The industry has pushed passive cooling to its limits with advanced materials and clever mechanical designs. But physics imposes a hard boundary. Without active airflow, sustained high-performance operation is not achievable.

Micro-cooling: A new approach to active thermal management

How to achieve that airflow? Traditional active cooling relies on fans. Fans move air, enabling heat transfer that effectively removes thermal energy from a system. In desktops and larger laptops, this approach works well.

But fans are not a universal solution. They take up space, generate noise, consume power, and introduce mechanical complexity. In ultra-thin devices, wearables, and sealed systems, integrating a fan is often impractical or undesirable. As a result, many edge devices are designed without active cooling, despite the increasing thermal demands placed on their components. Still, there’s a need for active cooling that fits within the constraints of modern device design.

Micro-cooling (µCooling) technology offers a new approach. Instead of miniaturizing traditional fans, µCooling uses piezoMEMS technology to generate airflow through microscopic motion inside a silicon chip. Often referred to as a “fan on a chip,” µCooling devices are fabricated using semiconductor processes, making them extremely compact, thin, and reliable.

Because they have no moving mechanical parts, µCooling devices avoid many of the drawbacks associated with conventional fans. They operate silently, consume minimal power, and can be integrated into tight spaces where traditional cooling solutions cannot fit. But most importantly, µCooling “fans” move heat out of a system and away from SSDs, something no passive cooling solution can accomplish.

What µCooling means for SSD performance

For SSDs, the introduction of µCooling is transformative. By generating localized airflow around the SSD controller and NAND components, µCooling systems can actively remove heat before it accumulates to critical levels. This helps maintain operating temperatures below throttling thresholds, even during sustained workloads.

Instead of experiencing performance degradation over time, SSDs can sustain higher throughput for longer durations. This is particularly valuable for AI workloads, where consistent data access speeds are essential. In practical terms, this means faster model loading, smoother real-time processing, and more reliable performance during extended tasks such as video rendering or large-scale data transfers.

µCooling also enables system designers to rethink thermal constraints. With active cooling available at the micro level, they can push performance boundaries without being limited by the thermal management challenges.

Enabling the future of edge AI devices

The evolution of SSDs has always been about addressing bottlenecks—first mechanical, then architectural. The next bottleneck is clearly thermal. Without addressing heat, we can’t realize the full potential of modern storage systems in edge devices. Throttling will undermine performance gains, and the user experience will suffer.

µCooling provides a path forward. By bridging the gap between passive and traditional active cooling, it enables a new class of thermal solutions tailored to the needs of modern electronics. It ensures that SSDs, a critical component of the data pipeline, don’t become a bottleneck. And that’s crucial.

As edge AI continues to proliferate, the importance of efficient thermal management will only increase. Devices are expected to do more—process more data, run more complex models, and deliver richer experiences—within smaller and more constrained form factors. Storage systems must keep pace with the demands for sustained, not just peak, performance.

Mike Housholder is VP and GM of thermal management at xMEMS.

 

 

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