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Gallium nitride (GaN) power IC and silicon carbide (SiC) technology firm Navitas Semiconductor Corp of Torrance, CA, USA has appointed semiconductor veteran Gregory M. Fischer to its board, serving on the Compensation and Executive Steering committees. He will stand for reelection in 2027 as a Class III director...

Громнадська Марина. Біотехнологи КПІ задля реалізації цілей сталого розвитку Інформація КП вт, 04/14/2026 - 11:30

Володимиру Володимировичу Пілінському – 85! Інформація КП вт, 04/14/2026 - 11:20

Flagship consumer electronic device launches are among the most operationally complex events in modern engineering. They require years of coordination across hardware, silicon, RF, software, operations, supply chain, and manufacturing. Yet, despite mature processes and experienced teams, flagship programs remain vulnerable to schedule volatility.

The root cause is rarely inadequate engineering talent. More often, it’s structural. Manufacturing realities are integrated too late into architectural decision-making. System-level validation, when deployed early and continuously, functions not as a downstream quality checkpoint, but as an organizational mechanism for compressing schedule risk before capital and timeline commitments are locked.

Financial exposure at flagship scale

At flagship scale, schedule slip is not simply an engineering inconvenience. It’s a material financial event.

Apple’s fiscal year 2025 results reported approximately $416 billion in annual revenue, with iPhone revenue representing roughly half of total sales. Samsung’s Mobile Experience division reported approximately $26 billion in quarterly revenue during. For programs operating at this scale, a one-month delay during a peak launch cycle can defer revenue comparable to the annual revenue of many mid-sized technology firms.

Even outside tier-one OEMs, launch timing directly impacts channel readiness, carrier alignment, ecosystem momentum, and competitive positioning. In high-volume hardware, schedule is strategy.

The challenge is that many launch delays are not caused by unforeseen global disruptions, but by late-stage design changes triggered during production ramp. Industry analyses consistently show that a significant portion of late engineering change orders originate from integration and manufacturability issues that were technically detectable earlier in the development cycle.

When these issues surface during ramp, optionality has already collapsed. Tooling is frozen, suppliers are capacity-allocated, and marketing calendars are committed. At that stage, validation confirms risk rather than preventing it.

Why component-level validation fails at scale

Traditional validation strategies are optimized for component correctness. Subsystems are tested against modular specifications, and readiness decisions are based on aggregated subsystem pass rates. This approach ensures that parts function independently; however, it does not guarantee that the system functions reliably under real-world, high-volume conditions.

Many failure modes emerge only during full-system interaction. Digital signal interference, RF coexistence conflicts, thermal coupling between tightly integrated subsystems, and parasitic effects often cannot be fully replicated in isolated bench testing.

For example, a high-speed display flex cable may pass standalone signal integrity validation. During system-level engineering verification testing (EVT) under real RF load, that same cable can radiate broadband noise that desensitizes the primary cellular receiver. The result is a coexistence failure that frequently forces late-stage shielding changes or mechanical redesign.

Similarly, assembly processes introduce stress, tolerance stack-up, and handling variability that are absent in early prototypes. Component-level validation ensures parts are defect-free. It does not predict how those parts behave when integrated and manufactured at scale. The consequence is predictable: issues emerge when yield sensitivity tightens during ramp.

A defect observed in 1 out of 100 early validation units translates into 10,000 defective devices at a one-million-unit scale. At millions of units, small deltas compound rapidly.

The design–manufacturing impedance mismatch

A recurring root cause of late-stage validation failures is misalignment between design optimization and manufacturing constraints. Design teams optimize for performance, power efficiency, compact form factor, and cost targets. Manufacturing teams optimize for yield stability, throughput, repeatability, and process capability. Both are correct within their domains.

Failure occurs when manufacturing sensitivity is not structurally integrated into architectural trade-off decisions. In cross-functional reviews, performance metrics are often presented without quantified yield sensitivity analysis. Design freeze decisions may proceed based on functional validation, while manufacturing risk remains probabilistic rather than modeled. Schedule pressure can incentivize accepting integration risk with the assumption that ramp will resolve residual issues.

System-level validation acts as the translation layer between these domains. When embedded early, it exposes divergence between design intent and production feasibility while design changes remain affordable. The cost-of-change curve, widely cited in engineering economics literature, demonstrates that defects discovered during mass production can cost orders of magnitude more to correct than those identified during early design phases. Whether the multiplier is 10x or 100x depends on context, but the direction is consistent: late discovery amplifies cost and schedule exposure.

System-level validation as risk compression

Reframing system-level validation as a schedule-risk compression mechanism changes how engineering organizations deploy it. Risk compression means reducing the variance between projected and actual ramp performance before high-volume commitments are made. It means narrowing the gap between modeled yield and early ramp yield while architectural flexibility still exists.

Consider a ten-million-unit program targeting 97% yield but only achieving 94% during early ramp. A 3% delta produces 300,000 additional defective units. At a $500 bill-of-materials cost, that equates to $150 million in direct exposure: before accounting for logistics, containment actions, rework, warranty impact, and brand degradation.

When system-level validation is embedded earlier in the development cycle, integration uncertainty is resolved before tooling freeze and capacity allocation. Manufacturing sensitivity becomes an architectural input, not a downstream constraint. Validation shifts from reactive confirmation to proactive risk reduction.

Governance implications for senior managers

For senior engineering and manufacturing managers, the implication is structural. System-level validation must be positioned upstream of design freeze, not solely before ramp. In practice, this requires:

• Upstream integration: Embedding manufacturing engineering into early architecture discussions.
• Quantified sensitivity: Requiring quantified yield sensitivity data before design freeze.
• Strategic alignment: Aligning validation milestones with major financial commitments.
• Holistic ownership: Elevating system-level risk ownership to program leadership rather than distributing it across siloed subsystem teams.

Organizations that treat system-level validation as a downstream quality function implicitly accept schedule volatility as a cost of doing business. Organizations that embed it as a bridge between design architecture and manufacturing execution create structural advantage. They stabilize flagship launch timelines, reduce ramp inefficiency, and preserve optionality when trade-offs are still affordable.

Ayokunle Oni is a system engineering program manager at Apple, where he helps coordinate the iPhone hardware design and engineering process across cross-functional teams. He specializes in system integration and validation and has led complex engineering programs from concept through production, working closely with global manufacturing and vendor partners.

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The post How system-level validation compresses schedule risk in device design appeared first on EDN.

To deliver solutions for next-generation artificial intelligence (AI) systems, a strategic collaboration has been announced that will leverage the RISC-V design expertise of smart digital system specialist CEA-List and the silicon photonics expertise of micro/nanotechnology R&D center CEA-Leti of Grenoble, France to introduce high-bandwidth communication and high-efficiency computing technologies into the established 3D stacking and interposer platforms of Taiwanese foundry Powerchip Semiconductor Manufacturing Corp (PSMC)...

About Chua's citcut: https://www2.eecs.berkeley.edu/Pubs/TechRpts/2009/EECS-2009-20.pdf My implementation: CHUA custom PCB board (thank you, JLCPCB!), TL082 op amps signal conditioner board (from +/-6V to 0 - 2V, from +/-1V to 0-2V) X/Y simple scope - Teensy4.0+ ILI9341 SPI display. Video: https://imgur.com/a/R0H5TSl submitted by /u/AdWest6565 [link] [comments]

Photonic simulation CAD software developer Photon Design Ltd of Oxford, UK has partnered with Cardiff University to deliver a two-day laser design course as part of its physics curriculum...

Specialty semiconductor and performance materials producer 5N Plus Inc (5N+) of Montréal, Québec, Canada has appointed Alban Fournier as chief financial officer (CFO), effective 27 April...

BluGlass Ltd of Silverwater, Australia — which develops and manufactures gallium nitride (GaN) visible laser diodes based on its proprietary low-temperature, low-hydrogen remote-plasma chemical vapor deposition (RPCVD) technology — has received commitments from investors to raise about AUS$8m (before costs) at an issue price of AUS$0.24 per share. The upsized placement includes one free attaching option for every share subscribed for under the placement, exercisable at AUS$0.38 and expiring on 31 May 2028...

Just some quick soldering in my free time. Wanted to see if its possible to bodge a 50 Ohms dummy load. Its not perfect since it picks up a lot of noise without any EMF shield and the impedance is not exactly 50 Ohms with these resistors. submitted by /u/arjobmukherjee [link] [comments]

So the design is ready and working in LTSpice. The red graph shows the voltage of the L3L4 transformer, that can be seen in the middle of the circuit. The voltage oscillates roughly between +10 and -10 kV. The blue graph shows the voltage difference between the upper and lower CW circuits output. submitted by /u/CountCrapula88 [link] [comments]

Was tinkering this rainy weekend, initially just playing around with assessing noise performance of a couple of amps, which quickly reminded me about input offset at higher gain. Using a pack of 8x fresh AA cells for most of these measurements, in an inverting amp with gain of 101 (5% error possible). The low-voltage amps were tested with 3x fresh AA cells, just under 5V. The homebrew op amp is made from non-sorted 2N3904/2N3906, circuit from Figure 2 of https://sound-au.com/project07.htm The vintage part numbers were generally vintage mid-1970s to late-1980s. Only a single amplifier was measured in every case. Nothing too rigorous but amusing to see how well they general conformed to datasheet typical. Pleasantly surprised how good the modern ST variant of the LM324A is. Just sharing in case anyone else finds it interesting. Part Vio (mV) Typ, Max (+/- mV) LM308 2.23 2, 7.5 CA3160A 3.35 2, 5 TL081C 7.09 NA, 15 LM741C -2.11 2, 6 XR-084 2.58 3,6 LM324A (ST) -0.85 2, 3 MCP6004 1.54 NA, 4.5 4.5v TLV2464 -0.35 0.5, 2 4.5v LM4562 -0.12 0.1, 0.7 homebrew 5.47 NA submitted by /u/DiscountDog [link] [comments]

I found it cheaper to buy lower amperage power supplies and having them in parallel instead of one with the same specs. I have made a passive balancer using 0.05 ohm resistors and one fuse so that one power supply doesn't works more than the rest. I am going to add ideal diodes to make it diode OR'ing to even further make the balancing better. Using this to drive a flyback transformer. The power supplies are 24V 6A so all four gives me 24V 24A. submitted by /u/Whyjustwhydothat [link] [comments]

Electric motors are everywhere—from the cars we drive to the appliances in our homes—but most rely on rare earth magnets that come with high costs and environmental challenges. A new wave of innovation is changing that story. Magnet-free electric motors are proving that smart engineering can deliver powerful performance without depending on scarce materials.

By removing rare earths from the equation, these designs promise cleaner supply chains, more sustainable production, and fresh opportunities for industries ranging from electric vehicles to renewable energy. It’s a shift that could redefine how we think about powering the future.

Why rare earths matter

Rare earth magnets, especially neodymium and dysprosium, have been the secret ingredient behind the compact, high-torque motors that power everything from electric vehicles to wind turbines. Their ability to deliver strong magnetic fields in small packages has made them indispensable in modern motor design.

But there is a catch: mining and processing rare earths is energy-intensive, environmentally challenging, and geographically concentrated in just a few regions of the world. This creates supply chain risks, price volatility, and sustainability concerns that ripple across industries.

By understanding why rare earths became so central to electric motors, we can better appreciate the significance of moving beyond them—and why magnet-free designs are more than just an engineering curiosity. They represent a strategic shift toward resilience, affordability, and cleaner technology.

How do you pull without a magnet

So how do you build a motor without magnets? The answer lies in clever engineering that takes advantage of the natural properties of materials and the geometry of the motor itself. Instead of relying on powerful magnets to create motion, magnet-free designs use principles like reluctance torque—where the rotor naturally aligns with the path of least magnetic resistance—or induction, where currents in the rotor generate the force needed to spin.

These approaches may sound technical, but the idea is simple: by rethinking the fundamentals, engineers can coax motors into delivering the same performance we expect, without the rare earth magnets. The result is a motor that can be lighter, more affordable, and easier to manufacture at scale. And because these designs lean on widely available materials, they sidestep the supply chain bottlenecks that have long plagued magnet-based motors.

Why it matters

Magnet-free motors are not just an engineering breakthrough; they are a practical step toward cleaner, more resilient technology. By removing rare earths, manufacturers can cut costs, ease supply chain pressures, and reduce environmental impact.

The benefits ripple across industries: in electric vehicles, they promise more affordable and sustainable mobility; in renewable energy, they support wind turbines and other systems without relying on scarce materials; and in industrial machinery, they offer reliable performance with simpler, more scalable production.

In short, magnet-free motors matter because they combine innovation with real-world impact, helping power a future that is smarter, greener, and less dependent on limited resources.

Figure 1 Today’s magnet-free electric motors deliver high efficiencies for heavy-duty and commercial vehicle applications. Source: Advanced Electric Machines

Working principles of magnet-free motors

For learners, makers, and anyone with a curious engineering mind, the real excitement lies in how magnet-free motors actually work. Instead of relying on rare earth magnets to generate motion, these designs tap into fundamental physics—using reluctance torque, induction, or clever rotor geometry to produce rotation.

Think of it as guiding the motor to “want” to align itself with paths of least resistance, or harnessing currents induced in the rotor to drive movement. The beauty is that these principles are elegant, scalable, and rooted in concepts every engineer encounters early in their studies. By revisiting the basics with fresh eyes, magnet-free motors show how fundamental science can be reimagined to solve modern challenges.

At their core, magnet-free motors rely on clever ways to generate motion without permanent magnets, using principles that every curious engineer can appreciate.

That is, reluctance motors exploit the tendency of a rotor to align with the path of least magnetic resistance, producing torque through geometry rather than magnets. Induction motors create rotation by inducing currents in the rotor with alternating fields, a design that is simple yet powerful. Synchronous reluctance motors combine aspects of both, offering efficiency and control that rival traditional designs.

Each approach shows how fundamental physics—magnetic fields, current flow, and mechanical alignment—can be harnessed in different ways to achieve the same goal: reliable rotation. For learners, makers, and innovators, these principles are a reminder that rethinking the basics can unlock new possibilities for sustainable engineering.

Figure 2 A synchronous reluctance motor demonstrates magnet‑free operation with smooth torque characteristics. Source: ABB

It’s important to note that not all reluctance motors are the same. A synchronous reluctance motor (SynRM) runs in step with the supply frequency, using flux barriers in the rotor to align with the path of least magnetic resistance, delivering smooth torque and efficiency. A switched reluctance motor (SRM), by contrast, relies on sequentially energizing stator phases to pull a simple steel rotor around; it’s rugged and powerful but tends to be noisier with more torque ripple.

Sitting between these designs is the permanent magnet assisted SynRM (PMA‑SynRM), which adds small magnets to stabilize the field and boost efficiency while still using far fewer rare earths than traditional permanent magnet motors. Together, these variations show the spectrum of approaches engineers use to balance performance, simplicity, and sustainability.

Unlocking SynRM performance with VFDs

While SynRMs deliver smooth torque and efficiency, they typically need a variable frequency drive (VFD) to start and stay synchronized with the stator’s rotating field. The VFD supplies control frequency and voltage, making these motors flexible but dependent on modern power electronics.

By contrast, older induction motors could start “across the line”—plugged directly into the grid—though at the cost of high inrush currents and less precise control. This reliance on VFDs underscores how magnet-free motor innovation is inseparable from advances in drive technology, reminding designers that motor and electronics progress go hand in hand.

As a worthy side note, VFD is the electronic brain that makes modern motors flexible. By adjusting the frequency and voltage, it lets a motor start gently, avoid the punishing inrush currents of direct grid connection, and run at variable speeds with precision. For SynRMs, the VFD is essential—it keeps the rotor locked in sync with the stator’s rotating field. Older induction motors could start “across the line” without such electronics, but that simplicity came at the cost of efficiency and control.

Figure 3 A compact VFD module suitable for driving 3-phase SynRM motors supports efficient control in both industrial and household applications. Source: Mean Well

From a design standpoint, the dependence on VFDs is both enabling and constraining. On the enabling side, drives unlock efficiency gains, smoother torque, and precise speed control that make SynRMs competitive with permanent-magnet machines.

On the constraining side, they add cost, require integration expertise, and shift part of the reliability burden from the motor to the electronics. For engineers, it means evaluating magnet-free motors is not just about rotor geometry; it’s about the total system, where sustainability benefits must be balanced against drive complexity and lifecycle economics.

Note that modern control strategies such as field-oriented control (FOC) and sensorless vector control extend the capabilities of these VFDs. FOC regulates stator currents to deliver precise torque and flux, while sensorless vector methods estimate rotor position without mechanical sensors, reducing cost and improving reliability. Together, they allow SynRMs—and other magnet-free designs—to match the responsiveness and efficiency of permanent-magnet machines.

Quick FOC take: Field‑oriented control does not have to be daunting. For makers eager to experiment, compact FOC shields/modules provide a straightforward, low‑power entry point. The Arduino SimpleFOC Shield is a practical example, lowering barriers and making hand-on exploration accessible.

Figure 4 SimpleFOC Shield empowers accessible FOC experimentation for Arduino users. Source: Author

Next, getting into design significance, the combination of magnet-free motor design, advanced VFDs, and intelligent control strategies has broad implications. Engineers gain access to motors that are lighter, more affordable, and easier to manufacture at scale, while sidestepping rare-earth supply chain constraints.

In the long run, magnet-free motors not only reduce dependence on scarce materials but also align with global sustainability goals, positioning them as a cornerstone of next-generation electrification across industries spanning from manufacturing to consumer appliances.

Closing thoughts

Magnet-free motors are steadily moving from concept to reality, driven by both maker ingenuity and industry ambition. With BMW and Mahle advancing externally excited synchronous motors to reduce rare-earth dependence, and Tesla having already demonstrated the scalability of induction motors, the message is clear: sustainable propulsion can deliver performance without compromise.

For makers and engineers alike, this is an invitation to experiment boldly and rethink motor design fundamentals, because the next leap in innovation may emerge as much from a personal workbench as from an automotive R&D lab.

T. K. Hareendran is a self-taught electronics enthusiast with a strong passion for innovative circuit design and hands-on technology. He develops both experimental and practical electronic projects, documenting and sharing his work to support fellow tinkerers and learners. Beyond the workbench, he dedicates time to technical writing and hardware evaluations to contribute meaningfully to the maker community.

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• Motor control design: an introduction to motors and controllers
• Designer’s Guide to High-Performance Motor Control for Robotics

The post Magnet-free electric motors: Driving innovation beyond rare earths appeared first on EDN.

Following the introduction of Industry 4.0, power electronics are becoming more significant in both digital and industrial infrastructures. Factories, energy systems, and data centers are getting smarter and more connected. This requires efficient power solutions that offer high power density and can scale with them.

Semiconductors are expected to deliver performance beyond the limits of conventional silicon-based power devices. Wide-bandgap (WBG) materials such as silicon carbide (SiC) and gallium nitride (GaN), as well as novel approaches to designing, packaging, and controlling power devices, are helping achieve the main goals of Industry 4.0: efficiency, flexibility, scalability, and intelligence.

800-VDC power architecture

One of the most significant changes introduced in the power system is the move of data centers to 800-VDC distribution, as detailed in an Nvidia white paper. Traditional systems that use AC and low-voltage DC can’t keep up with the speed and growth needs of AI-based workloads. High-performance computing clusters, especially those that support generative AI and machine learning, demand more power and should use it as efficiently as possible.

By raising the distribution voltage to 800 VDC, operators can reduce the current for a given power level. This approach offers the benefits of reduced I2R losses and the ability to use thinner wires. Overall, efficiency can thus be increased, and more power can be integrated in the same area or volume. The design also becomes less complicated because there are fewer steps in the conversion process.

This new architecture directly affects semiconductor requirements. Power devices need to perform well at higher voltages with minimum loss and support fast switching. Chipmakers and manufacturers are developing power solutions to support Nvidia’s 800-VDC power architecture reference design for next-generation AI factories to improve efficiency and reduce power losses.

To support gigawatt-scale AI factories based on an 800-VDC power architecture, Flex, for example, introduced a new reference design (Figure 1) that integrates power, liquid cooling, and compute capabilities into a modular assembly. This prefabricated solution streamlines the implementation of 800-VDC architectures and, according to the company, enables 30% faster deployment than conventional systems.

Figure 1: Flex’s reference design accelerates giga-scale AI factory deployment through a modular and preassembled structure. (Source: Flex) SiC semiconductor advances

Due to its physical properties, such as high breakdown voltage, low switching losses, and high thermal conductivity, SiC can operate efficiently and provide high reliability in high-voltage and high-power environments.

At the high-voltage end, SiC devices are going into the multi-kilovolt range. More devices are gaining ratings above 1,200 V, making SiC more common in places where silicon-based power devices used to be the norm.

Navitas Semiconductor recently announced the availability of samples for its 2,300-V and 3,300-V high-voltage SiC products, specifically designed to increase efficiency in AI data centers, power grids, and renewable energy infrastructure. The devices, available in discrete, module, and known-good-die formats, are based on the company’s Trench-Assisted Planar architecture.

This semiconductor structure optimizes electric-field management, significantly reducing voltage stress and improving avalanche robustness compared with traditional trench- or planar-MOSFET designs. It also achieves lower RDS(on) at high temperatures and better current spreading.

As power devices improve, their packaging becomes increasingly crucial to the overall performance of the system. Newer packages are designed to reduce parasitic inductance, improve thermal management, and handle larger current densities.

These advancements in packaging technology enable higher performance and efficiency gains. Texas Instruments (TI), for example, recently unveiled two isolated power modules for applications from data centers to electric vehicles that require improvements in power density, efficiency, and safety. The UCC34141-Q1 and UCC33420 isolated power modules leverage TI’s IsoShield technology, which copackages a high-performance planar transformer and an isolated power stage, providing functional, basic, and reinforced isolation capabilities.

TI’s proprietary multichip packaging solution claims up to 3× higher power density than discrete solutions in isolated power designs and shrinks the solution size by as much as 70% by packing more power into smaller spaces. Applications range from factory automation PLC modules and EV and powertrain systems to grid infrastructure and rack and server power.

Wolfspeed Inc. has revealed that its 300-mm SiC platform, leveraging patent-pending innovations, is set to become a key material component for AI and high-performance computing (HPC) packaging by the late 2020s. Figure 2 shows a conceptual demonstration of an interposer substrate built on the company’s 300-mm SiC wafer. According to Wolfspeed, the SiC substrate helps to improve the thermal, mechanical, and electrical performance of next-generation packaging structures required by AI and HPC systems.

Figure 2: Conceptual demonstration of a 100 × 100-mm interposer substrate enabled by Wolfspeed’s 300-mm SiC wafer (Source: Wolfspeed Inc.) GaN advances

While SiC excels at high voltages, GaN is suited for low- and medium-voltage applications, especially below 650 V. This semiconductor can switch at high frequencies, up to the megahertz range, with very low power loss, making power converters more efficient and smaller and requiring less cooling.

One important trend in GaN’s growth is integration. For example, Schottky diodes could be incorporated into GaN transistors to reduce losses from reverse conduction and make it easier to build power stages. Following this concept, Infineon Technologies AG has introduced the industry’s first industrial-grade GaN power transistors featuring an integrated Schottky diode.

Traditionally, GaN devices in hard-switching applications suffer from higher power losses due to their large body-diode voltage drop. This issue gets worse during the “deadtime” of a power controller. Engineers previously solved this by adding an external Schottky diode or complex controller tuning, both of which increase design time and costs. The new CoolGaN transistor G5 family solves this by integrating the diode directly into the transistor, reducing deadtime losses and boosting overall system efficiency.

Another important trend is bidirectional switching, where new GaN devices can block current and voltage in both directions. This simplifies converter topologies and requires fewer components. This capability is especially crucial for applications such as energy storage systems, EV chargers, and power-factor-correction circuits.

Renesas Electronics Corp. has introduced the industry’s first bidirectional switch (TP65B110HRU) based on depletion-mode (d-mode) GaN technology (Figure 3). Most current high-power conversion systems rely on unidirectional silicon or SiC switches that block current in only one direction. This limitation forces engineers to design multi-stage circuits or use “back-to-back” switch configurations, which significantly increases component count and reduces overall efficiency.

By integrating bidirectional blocking into one GaN product, this technology enables “single-stage” power conversion. The high switching speed and low stored charge of GaN also enable higher power density and switching frequencies. According to the company, this architecture has demonstrated over 97.5% power efficiency, providing a solution well-suited for AI data centers, on-board EV chargers, and renewable energy applications.

Figure 3: Renesas’s TP65B110HRU high-voltage d-mode bidirectional GaN switches (Source: Renesas Electronics Corp.) Solid-state transformers

Solid-state transformers (SSTs) are a huge change in how power is transferred and controlled. SSTs are not like ordinary transformers, as they use power electronic converters to modify, split, and control the voltage.

Using this technology, more advanced features become available. These include two-way power flow, real-time voltage management, and the capacity to operate with renewable energy sources. Smart grids, microgrids, and Industry 4.0 all need SSTs that can change rapidly and easily. For SSTs to grow, WBG semiconductors are particularly significant.

For example, Infineon and DG Matrix, a company specializing in SSTs, have partnered to integrate SiC semiconductors into the Interport multiport SST platform. This collaboration aims to modernize the connection between the public grid and energy-intensive applications such as AI data centers, EV charging, and industrial microgrids.

Unlike traditional copper- and iron-based transformers, SSTs are semiconductor-based devices. They are smaller and lighter, accelerating deployment and providing higher power density. Adopting Infineon’s SiC technology, these SST systems achieve improved efficiency and reliability.

The technology enables direct power conversion from medium-voltage grid levels to the low-voltage requirements of modern digital infrastructure. DG Matrix plans to scale toward higher-voltage platforms to support the global rollout of high-performance power infrastructure.

The post Power electronics evolve to maximize efficiency appeared first on EDN.

У КПІ фахівці провідних енергокомпаній провели цикл занять для студентів-енергетиків kpi пн, 04/13/2026 - 15:49

На війні загинув студент нашого університету Роман Андрійчук kpi пн, 04/13/2026 - 15:43

The technology treadmill never stops, and so it goes with Blink’s second-generation hub device versus its predecessor.

Last month, I compared the conceptually similar (and thankfully, concurrent-use RF-compatible) hub-and-spokes approaches used by Blink and TP-Link for their respective battery-operated device ecosystems. Blink’s particular hub implementation, the first-generation Sync Module still in active use at my residence to this very day, doesn’t support local recording storage, only to the cloud, a service which fortunately is free for me (albeit in a somewhat limited-duration fashion) as a legacy customer.

(it’s more recently been moved from my office to the laundry room, and as regular readers know from other recent writeups, that Belkin Wemo smart switch above it is also now DOA)

Gratis capacity for non-geriatrics

But when I saw an inexpensive “for parts only” second-generation Sync Module available for sale on eBay, I still jumped on the opportunity, driven by curiosity. Primary differences between the two generations include, for the more recent model:

• A functionally active embedded USB-A connector, for mating with a flash stick or other mass storage device for local recording storage
• More robust, therefore more responsive, integrated processing, and
• Claimed wider-range Wi-Fi coverage

Turns out the device itself works fine, at least to the degree I’ve tested it so far; I was able to factory-reset it, and the Blink app can now “see” it (although I haven’t yet set it up). The only thing missing was the originally included AC/DC adapter with a micro-USB output, but I’ve got plenty of spares of those already, along with the one currently fueling its same-dimensions precursor in case I ever decide to upgrade in situ. So, let’s dive inside and see what we can learn, both in an absolute sense and relative to the first-gen Sync Module that I took apart…yikes….nearly seven years ago. Shall we?

Here’s today’s patient, as usual accompanied by a 0.75″ (19.1 mm) diameter U.S. penny for size comparison purposes:

All-important FCC ID (2AF77-H2121520):

Micro-USB power input:

and now-functional USB-A data port:

Open sesame

I wish everything I tore down was this easy to open up:

At this point…

Let’s pause a moment for some interesting (at least to me) background info. In re-reading my archaic first-gen teardown verbiage, I noted that I’d written (among other things) the following:

Today’s teardown candidate is that very same Sync Module. The one currently in use with my Blink XT cameras matches their black color; this particular one was purchased standalone off Ebay specifically for teardown purposes and is white (and previously used). Color scheme deviations aside, the two models are functionally identical.

I was right with my “identical” claim, at least with respect to the functional angle. And I’d already noted the color deviation. But further (and more recent) research has enlightened me that there were other (non-functional) hardware differences between my in-use device and the one I took apart, too. Blink actually brought to production multiple main variations of the first-generation Blink Sync Module (including a low-volume initial “launch” iteration), along with region-specific tweaks of each variant reflective of differing RF spectrum regulations:

There have been 5 main revisions of sync modules:

Version 0 which was white and has a (non-functional) ethernet port and (non-functional) USB and BLE (non-functional) available. This was the ‘launch’ era.

 Version 1a which is white and has a (non-functional) ethernet port and (non-functional) USB.

Version 1b which is white or black and has a (non-functional) USB.

Version 1c which can be white or black and has no ports.

These were all the general ‘XT’ era modules.

Version 2 (the current one) which has a functional USB port.

All the modules are currently compatible with each other, but Modules 0, 1a,b,c have support ‘no longer guaranteed’.

However, this isn’t the end of the story, as the boards inside all come in combinations of EU and US and Intl flavors (due to regulatory / radio differences) too!

I’m guessing that the version I tore down back in mid-2019 was a “Version 1a”. I suppose it also could have been a “Version 0”, although I didn’t come across any Bluetooth Low Energy circuitry inside it. The one still in use here is a “Version 1b”.

Intra-generational variation

When the Redditor who wrote the above shared his thoughts four years ago, there may have been only one (initial) version of the Sync Module 2 we’re looking at today. Fast forward to the present, however, there now have been (at least) two. The initial hardware was based on Atheros silicon for both the processor and Wi-Fi module; Blink subsequently switched to NXP-sourced ICs for both the processor and wireless subsystems, the latter this time supporting not only Wi-Fi but also both Bluetooth and BLE.

Onward. Remove two screws:

And the PCB pops right out:

You’ve already gotten a glimpse of the PCB frontside, so in fairness to its backside counterpart, let’s start there with the detailed analysis:

Admittedly, there’s not much of note, unless you’re into passives and embedded traces, that is. At lower left is the reset-and-pairing switch. And to its right is a Winbond W25Q256JV 256 Mbit serial NOR flash memory, presumably for system code storage. For comparisons sake, here’s the comparatively sparse backside of the first-gen Sync Module PCB:

Now flipping the PCB back over…

I didn’t bother expending much effort at peeling the initially stubborn sticker off the processor; I already know from the NXP logo visibly atop the chip in its upper right corner in conjunction with the helpful Wiki reference page I’d found that it’s the second iteration of the second-gen design, employing NXP’s MCIMX6Z0DVM09AB application processor with the following specs:

• ARM Cortex-A7 running Linux
• 900MHz
• SRAM: 128kB
• SPI/UART/I2C
• 96KB bootrom, 128KB internal RAM
• Has Arm TrustZone

That other NXP chip I previously noted is the 88W8987-NYE2 wireless “solution”. Below the processor is an ISSI IS43TR16640BL 1 Gbit DDR2 SDRAM. And at the top center of the PCB is one more notable (albeit tiny) IC. Labeled as follows:

455A
CQRX
220

It’s Silicon Labs’ Si4455 sub-GHz wireless transceiver, which (as the name) implies implements the proprietary long-range 900 MHz channel that Blink refers to as the LFR (low-frequency radio) beacon.

In closing, here’s the first-generation Sync Module PCB topside for comparisons sake:

And with that, I’ll turn it over to you for your thoughts in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN Magazine.

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The post The Blink Sync Module 2: Faster response and local storage, too appeared first on EDN.

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