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Закріплення освітніх програм за структурними підрозділами університету kpi чт, 07/09/2026 - 17:20

📰 Газета "Київський політехнік" № 25-26 за 2026 (.pdf) Інформація КП чт, 07/09/2026 - 16:45

Нове життя лабораторного обладнання: міжнародна підтримка електрохімічної освіти в КПІ kpi чт, 07/09/2026 - 15:58

Revisiting the past can leave the reader with a range of reactions, including both bemusement at then-embryonic developments and amazement at the accuracy of forecast extrapolations.

After reading the sentence that follows this one, pause for a moment and guess when it was first written, prior to plunging forward in my own prose:

The amount of effort and money put into artificial intelligence has been quite limited, and there are only about a half-dozen major centers of such activity in the world.

Clearly, this quote is a “few” years old! Consider, for example, that last September Gartner forecasted that worldwide spending on AI would hit $1.5 trillion for that (last) year. The above quote is from renowned astrophysicist Carl Sagan’s treatise, “Broca’s Brain: Reflections on the Romance of Science”, first published in 1979, with which I recently reconnected over a long weekend read.

Most people overestimate what they can achieve in one year and underestimate what they can achieve in ten years. (Bill Gates)

Specifically, it came from chapter 20, “In Defense of Robots”, which in its original form was titled “In Praise of Robots” and appeared in the January 1975 edition of Natural History magazine. Unsurprisingly, given that the source material is more than a half-century old at this point, some of it is charmingly dated. Consider, for example, this chapter excerpt:

There will be strong pressures for continued miniaturization of intelligent machines. It is clear that remarkable miniaturization has already occurred. Vacuum tubes have been replaced by transistors, wired circuits by printed circuit boards, and entire computer systems by silicon chip microcircuitry. Today, a circuit that used to occupy much of a 1930 radio set can be printed on the tip of a pin.

Or, speaking of the current state of intelligent machines, this passage:

The ten best chess players in the world still have nothing to fear from any present computer, but the situation is changing. Recently, a computer for the first time did well enough to enter the Minnesota State Chess Open. This may be the first time that a non-human has entered a major sporting event on the planet Earth…The computer did not win the chess open, but this is the first time one has done well enough to enter such a competition. Chess playing computers are improving extremely rapidly.

And then there’s this, focusing on Sagan’s primary area of expertise, space:

In the exploration of Mars, unmanned vehicles have already soft-landed, and only a little further in the future they will roam about the surface of the Red Planet as some now do on the Moon.

What would Sagan have thought about the fact that, as I’m writing these words, NASA just announced that its Perseverance rover has traveled the distance of a marathon on Mars, notably much of it autonomously? He wouldn’t, I’d argue, be at all surprised. And that, dear readers, is at the core of why I’m focusing on his book, and this chapter in particular, today. To wit, immediately after the prior quote, he elaborated on his prognostication “tease”, writing:

The Viking landers deposited on Mars in summer of 1976 have a very interesting array of sensors and scientific instruments, which are the extension of human senses to an alien environment. The obvious post-Viking device for Martian exploration, one which takes advantage of the Viking technology, is a Viking rover in which the equivalent of an entire Viking spacecraft, but with considerably improved science, is put on wheels or tractor treads and permitted to rove slowly over the Martian landscape.

But now we have a new problem, one that is never encountered in machine operation on the Earth’s surface.  Although Mars is the second closest planet, it is so far from the Earth that light travel becomes significant. At a typical relative position of Mars and the Earth, the planet is 20 light minutes away. Thus, if the spacecraft were confronted with a steep incline, it might send a message of inquiry back to Earth. Forty minutes later, the response would arrive saying something like, “For heaven’s sake, stand dead still!” But by then, of course, an unsophisticated machine would have tumbled into a gully.

Consequently, any Martian rover requires slope and roughness sensors. Fortunately, these are readily available and are even seen in some children’s toys. When confronted with a precipitous slope or large boulder, the spacecraft would either stop until receiving instructions from the Earth in response to its query and televised picture of the terrain, or back off and start in another and safer direction. Much more elaborate contingency decision networks can be built into the onboard computers of spacecraft of the 1980s.

Any sufficiently advanced technology no longer distinguishes itself from pure magic. (Arthur C. Clarke)

The fundamental point of In Defense of Robots, at least per my interpretation of it, is to provide Sagan with a platform to answer a question he posited at the beginning:

The powerful abilities of computing machines to do arithmetic hundreds of millions of times faster than unaided human beings are legendary. But what about really difficult matters? Can machines in any sense think through a new problem? Can they make discussions of the branch-contingency-tree variety with which we think of as characteristically human?

Sagan’s answer to that question was an unqualified “yes”, and here’s what he thought it would look like, again specific to astrophysics and related topics:

In the development of such machines we find a kind of convergent evolution. Viking is, in a curious sense, like some great outsized clumsily constructed insect. It is not yet ambulatory and is certainly incapable of self-reproduction, but it has an exoskeleton, it has a wide range of insect-like sensory organs, and it is about as intelligent as a dragonfly.

But Viking has some advantages that insects do not. It can, on occasion, by inquiring of its controllers on Earth, assume the intelligence of a human being. The controllers are able to reprogram the Viking computer on the basis of the decisions they make.

As the field of machine intelligence advances, and as increasingly distant objects in the solar system become accessible to exploration, we will see the development of increasingly sophisticated onboard computers, slowly climbing the phylogenetic tree from insect intelligence to crocodile intelligence to squirrel intelligence and, in the not very remote future, I think, to dog intelligence.

That said, Sagan was also keen to expand far beyond astrophysics with his forecasts, even to the realm of psychoanalysis. Consider chatbots’ increasingly common use as virtual therapists, albeit with diverse user experiences and outcomes, as you read the following excerpt:

In a time when more and more people in our society seem to be in need of psychiatric counseling, and when timesharing of computers is widespread, I can even imagine the development of a network of computer psychotherapeutic terminals something like arrays of large telephone booths in which for a few dollars a session we are able to talk to an attentive tested and largely non-directive psychotherapist. Ensuring the confidentiality of the psychiatric dialogue is one of the several important steps still to be worked out.

Or consider something a bit “closer to home” for the broad engineering community, that of humanoid and other robotic systems for industrial and other related applications:

If intelligent machines for terrestrial mining and space exploratory applications are pursued, the time cannot be far off when household and other domestic robots will become commercially feasible…There are many common tasks, ranging from bartending to floor washing, that involve a very limited array of intellectual capabilities, albeit substantial stamina and patience.

All-purpose ambulatory household robots, which perform domestic functions as well as a proper 19th century butler, are probably many decades off, but more specialized machines, each adapted to specific household functions, are probably already on the horizon. It is possible to imagine many other civic tasks and essential functions of everyday life carried out by intelligent machines.

Much in life is simply a matter of perspective. It’s not inherently good or bad, a success or failure; it’s how we choose to look at things that makes the difference. (David Niven)

But I can’t help but wonder: was Sagan too sanguine about the societal upheaval caused by AI-powered robotic (and broader AI) supplant?

For the development of domestic and civic robots to be a general civic good, the effect of re-employment of those human beings displaced by the robots must be of course arranged. But over a human generation, that should not be too difficult, particularly if there are enlightened educational reforms. Human beings enjoy learning.

If anything, he seemed more concerned that human beings’ overreaction (at least in his eyes) to such displacement might unnecessarily delay or even preclude this transition and broader transformation, to the broader detriment of our species (thereby at least in part explaining, I suspect, the shift from robot “praise” to “defense” from the 1975 article to 1979 book chapter):

We appear to be on the verge of developing a wide variety of intelligent machines capable of performing tasks too dangerous, too expensive, too onerous, or too boring for human beings. The development of such machines is, in my mind, one of the few legitimate spin-offs of the space program. The efficient exploitation of energy and agriculture, upon which our survival as a species depends, may even be contingent on the development of such machines.

The main obstacle seems to be a very human problem, the quiet feeling that comes stealthily and unbidden, and argues that there is something threatening or inhuman about machines performing tasks as well or better than human beings, or a sense of loathing for creatures made of silicon and germanium rather than proteins and nucleic acids. But in many respects, our survival as a species depends on our transcending such primitive chauvinisms.

In part, our adjustment to intelligent machines is a matter of acclimatization. There are already cardiac pacemakers that can sense the beat of a human heart. Only when there is the slightest hint of fibrillation does the pacemaker stimulate the heart. This is a mild but very useful sort of machine intelligence. I cannot imagine the wearer of this device resenting its intelligence [EDITOR NOTE: as regular readers will likely already understand, I particularly resonated with this point].

I think in a relatively short period of time there will be a very similar sort of acceptance for much more intelligent and sophisticated machines. There is nothing inhuman about an intelligent machine. It is indeed an expression of those superb intellectual qualities that only human beings, of all creatures on this planet, now possess.

Whether or not you resonate with Sagan’s perspectives in the excerpts I’ve shared, I suspect you’ll (near-)universally agree with my admiration for the accuracy of his prophecies, along with the rare combination of intelligence and open-mindedness (with at least one notable exception) that were at their foundation. Regardless, I encourage you to pick up a copy of Broca’s Brain: Reflections on the Romance of Science and give it a read for yourself.

It’s only $6.99 on Kindle as I write this (and as I read it), and I also commonly come across both hardcover and paperback copies of it at used bookstores. There’s always also your public library, of course. And worst case, I stumbled across a YouTube video of someone reading the (bulk of the) text of the In Praise of Robots chapter:

Fair warning: there’s at least one several-paragraph section missing (I suspect due to a multi-“take” merging edit error, not intentionally), ironically the one from which the quote that opened this writeup came. And the regularly changing “psychedelic” special effects (which I suspect were an attempt, apparently successfully, to circumvent copyright infringement algorithms) compel me to encourage you to focus solely on the audio. But, hey…free!

Regardless of how you end up consuming Broca’s Brain, I hope you find it a fruitful experience, versus a waste of time. Be sure to come back here afterward and share your thoughts in the comments, ok? Thanks!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

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The post Carl Sagan’s prescient thoughts on AI and robots appeared first on EDN.

🏆 7 PhD-дослідницьких проєктів КПІ ім. Ігоря Сікорського стали переможцями конкурсного добору МОН України! KPI4U-2 чт, 07/09/2026 - 12:40

Optical in-situ metrology system maker LayTec AG of Berlin, Germany says that Sandia National Laboratories has purchased a customized manual-loading version of its EpiX mapping station, combining white light reflectance (WLR) and photoluminescence (PL) metrology for non-contact optical wafer mapping...

Regarding the patent infringement complaint filed against it by Wolfspeed Inc of Durham, NC, USA — which makes silicon carbide (SiC) materials and power semiconductor devices — in the United States District Court for the District of Delaware, gallium nitride (GaN) power IC and silicon carbide (SiC) technology firm Navitas Semiconductor Corp of Torrance, CA, USA says that it disputes the allegations, will “vigorously defend itself and its products against baseless accusations of infringement”, and expects to prevail in the litigation. In the meantime, Navitas remains “fully committed to executing its growth strategy and delivering innovative products that address the rapidly expanding demand for next-generation power semiconductors”...

Samsung’s PM1763 PCIe 6.0-based enterprise SSD features 9th-generation V-NAND flash memory and a new 4-nm controller. Optimized for AI and HPC servers, the drive is available in 4-TB, 8-TB, and 16-TB capacities. The 16-TB model delivers sequential read and write speeds of up to 28,400 MB/s and 21,900 MB/s, respectively—up to twice the performance of its predecessor, the PM1753.

According to the company, the PM1763 can transfer a 40-GB LLM in approximately 1.4 seconds, helping minimize data latency between processors and accelerators while improving overall AI processing efficiency. The SSD is optimized for liquid-cooled server environments through direct-to-chip cooling. This design enables sustained peak performance while improving power efficiency by up to 1.8 times compared to the previous generation.

To address security requirements for AI and virtualized infrastructure, the PM1763 supports post-quantum cryptography (PQC), the Security Protocol and Data Model (SPDM) 1.4, and Commercial National Security Algorithm (CNSA) 2.0. It also provides link encryption based on the TEE Device Interface Security Protocol (TDISP) to reinforce data protection across storage interfaces.

Samsung has now begun mass production of the PM1763 SSD.

PM1763 product page 

Samsung Electronics  

The post Enterprise SSD accelerates AI server data transfer appeared first on EDN.

Using a vertically stacked-die design, AOS’s DFN6×5 AmpStack package integrates two MOSFETs configured as a high-side/low-side half-bridge. It increases power density and maximizes available PCB space compared to a solution using two discrete DFN5×6 MOSFETs. The package enables high-density power conversion applications ranging from megawatt AI factories to power tools.

The AOPL66801 80-V MOSFET showcases the new half-bridge package with an optimized switch-node clip connecting the high-side and low-side MOSFETs. This architecture minimizes parasitic inductance within the package. Compared to a standard discrete solution, it also reduces PCB parasitic inductance, minimizing phase-node voltage ringing and decreasing stress on the MOSFETs. Key specifications for the AOPL66801 include:

An integrated Kelvin sense pin maintains gate-voltage stability during high di/dt switching. The dedicated connection provides a more effective high-side gate-drive path, helping reduce switching losses. The device also supports a maximum junction temperature of 175 °C for increased thermal capability.

The AOPL66801 is available now in production quantities with a 16-week lead time. Pricing is $6.16 per unit in 1000-piece quantities.

AOPL66801 product page 

Alpha & Omega Semiconductor 

The post Stacked-die half-bridge boosts MOSFET power density appeared first on EDN.

The Vishay 34 PHE absolute position sensor provides 10-turn linear or rotary displacement sensing with a 3600° range. Using non-contact Hall-effect technology, it delivers up to ±1% linearity (full stroke), 1° resolution, and a service life of more than 10 million cycles.

According to Vishay, the 34 PHE is priced 40% lower than previous-generation devices. It is designed for servo loop motion control systems requiring high accuracy and long-term stability in harsh environments. Typical applications include industrial motor and actuator displacement tracking, solar panel alignment systems, and flow control valve positioning.

The sensor features IP65 sealing and withstands vibration up to 20 g and shock up to 50 g. Integrated reverse-voltage and overvoltage protection (−14 VDC and +28 VDC) reduces the need for external protection circuitry. It supports single or dual analog ratiometric outputs or a digital PWM output. In dual-output mode, the two channels track position in opposite directions to enable basic fault detection. The 34 PHE reports its position immediately after power-up, even following a power loss, without requiring recalibration, homing, or initialization.

Samples and production quantities of the sensor are available now, with lead times of 14 weeks.

34 PHE product page 

Vishay Intertechnology 

The post Hall-effect sensor measures 10-turn position appeared first on EDN.

VeriSilicon’s CPP2000 Camera Post-Processing IP improves image quality for reliable vision performance in robotics, drones, and other mobile vision applications. It is designed for straightforward SoC integration and processes YUV images from image signal processors using a range of image enhancement techniques.

The IP supports image and video processing at up to 8K resolution, applying motion-compensated temporal filtering, advanced spatial noise reduction, chroma adjustment, dynamic contrast enhancement, and edge enhancement to improve noise suppression, sharpness, contrast, and overall detail fidelity.

The CPP2000 is implemented as a modular, streaming hardware pipeline in which each stage operates as a dedicated accelerator, enabling continuous real-time processing from input to output. Multiple hardware configuration options are available to address varying requirements for power, performance, area, and latency across applications.

CPP2000 product page  

VeriSilicon

The post IP enables 8K image and video post-processing appeared first on EDN.

Taiyo Yuden has introduced the HVX(-K) and HTX(-K) series of AEC-Q200-qualified conductive polymer hybrid aluminum electrolytic capacitors. The 46-device lineup is intended for noise suppression and power smoothing in power supply circuits for automotive control and safety functions such as power steering and ADAS.

The hybrid capacitors provide improved capacitance characteristics over the earlier HVX and HTX series. For instance, the 80-V RAHTX181M1RGP5005K offers a capacitance of 180 µF and a rated ripple current of 3900 mA RMS at 135°C. The devices are available in seven case sizes, with diameters of 6.3 mm to 12.5 mm and heights of 7.7 mm to 16.5 mm.

By combining a conductive polymer with an electrolyte solution, the hybrid capacitors achieve the low ESR of conductive polymers while retaining the self-healing properties of aluminum electrolytic capacitors, enhancing both performance and reliability.

The HVX (-K) and HTX (-K) series are now in production. Detailed information can be found here.

Taiyo Yuden

The post Hybrid capacitors target automotive power appeared first on EDN.

Vancouver-based Teck Resources Ltd, Canada Growth Fund Inc (CGF) and Natural Resources Canada (NRCan)’s $2bn Canada Critical Minerals Accelerator (formerly the Critical Minerals Sovereign Fund) have signed a strategic investment agreement to support expanding production capacity for germanium, gallium and antimony at Teck’s Trail Operations smelting and refining complex in British Columbia...

Erlangen-based Fraunhofer IISB (Institute for Integrated Systems and Device Technology) and Wettenberg-based microwave & radio frequency plasma system maker PVA TePla AG are pooling their expertise in a Joint Lab for the production of aluminium nitride (AlN) crystals...

A self-heated Darlington transistor pair makes a simple, sensitive, and sturdy airflow sensor. But first an annoying non-linearity needs unbending.

If you take a self-heated transistor in a TO-92 package and force it to hold a constant temperature differential above ambient, the power input required to keep it stuck to setpoint will be determined by its thermal impedance ZT relative to the air, as given by:

ZT = ZJ + 1/(SC + KT √AF )

where:

ZJ = junction-to-case thermal impedance = 44°C/W
SC = still-air case-to-ambient conductivity = 6.4 mW/°C
KT = “King’s Law” thermal diffusion constant = 0.75 mW/°C√fpm
AF = air flow in ft/min

Wow the engineering world with your unique design: Design Ideas Submission Guide

The AF term suggests the arrangement might be handy for air flow measurement, because of the way it makes ZT, and therefore power input for a given differential, a function of air speed.  Figure 1 shows the resulting power vs AF relation a differential (Dt) = 31oC. Do note, however, the annoying non-linearity.

Figure 1 This graph shows the power dissipated vs air speed of a TO-92 held at a constant 31oC above ambient Pw = 31/ZT.

Figure 2 shows a practical thermostat circuit to achieve and maintain this delta-T while outputting a signal predictably related to Pw.  It utilizes a Darlington sensor transistor pair (Q1 and Q2) to compensate for ambient temperature and convert the resulting nonlinear Pw curve into a linearized airflow readout.  Its current mode output is compatible with the long cable runs often seen in airflow measurement applications.

Figure 2 This linearized Darlington anemometer circuit supports a 4-20mA current mode output.  Adjust R10 to calibrate 4mA (zero fpm), R11 to calibrate 20mA (250fpm).

Here’s how it works.

Q1 serves as the self-heated sensor modeled in the Figure 1 math, with Q2 providing ambient temperature compensation.  Opamp A2 runs a feedback loop that forces the Vbe differential between Q1 and Q2 (and thus the temperature differential between Q1 and ambient) to hold a constant 31oC.  It does this (with the help of Darlington current gain) by forcing Q1’s current draw (I) through R3 to drive Q1’s power dissipation (Pw) to follow the fig.1 curve of heat-vs-air flow.  The resulting voltage developed (IR3) is the basis of the air speed measurement.

Okay so far.  But how does compensation for Figure 1’s nonlinearity happen?   Well, happily the function of Q1’s Pw vs collector current I isn’t linear either.  In fact Pw = 5vI – I2R3.  That quadratic I2 term is the key.  It creates the lovely linearizing curve shown in Figure 3.

Figure 3 This graph details Q1 power dissipation vs  collector current.  Pw = 5vI – I2R3.

The 2nd-order curvature of Figure 3 compensates for the bend in Figure 1. Although the match isn’t perfect, when converted to the 4-20mA by opamp A1, the realized output is a calibrated readout of air speed that differs from ideal by less than +/- 5% from 0 to 250fpm, as shown in Figure 4.

Figure 4 This graph’s data relates anemometer output vs airspeed: FPM = 15.6(Iout – 4mA) +/-10FPM.

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

Related Content

• Self-heated Darlington transistor pair comprises new air flow sensor
• Linearized portable anemometer with thermostated Darlington pair
• Nonlinearities of Darlington airflow sensor and VFC compensate each other
• Improve thermal airflow sensor PSRR with just two resistors
• A groovy apparatus for calibrating miniature high sensitivity anemometers

The post Solid state airflow sensor with linear 4-20mA output appeared first on EDN.

I reused the housing of an old timing light and built a new LED timing light from scratch. It works for checking ignition timing and adjusting ignition advance on many motorcycles and even carbureted cars with a distributor. The circuit, build process, and testing are covered in the full video. If anyone is interested, the link is in the comments. submitted by /u/mrwolfdiy [link] [comments]

Infineon Technologies AG of Munich, Germany is to supply CoolSiC MOSFETs 1200V and matching dual-channel EiceDRIVER 2EDB9259Y gate drivers to silicon carbide (SiC) power electronics and advanced control systems provider ADVANTICS of Saint-Genis-Pouilly, France for its new line of liquid-cooled power converters. The solutions are said to enhance efficiency, power density and reliability in applications such as megawatt charging systems (MCS) for heavy-duty vehicles and vessels, as well as energy storage systems and DC microgrids for data centers. The collaboration helps to address the need for faster charging, robust grid infrastructure and more efficient power conversion...

The costs of designing and producing an analog ASIC chip can be grouped into three main parts: human capital, software tools, and prototype fabrication. While all three are equally critical to success, it’s important to note that design tools and wafer foundries are ubiquitous. All semiconductor companies have equal access to them, and it’s rare that a problem with the performance of an analog ASIC comes from the tools used or the wafer foundry that produced it.

Human capital: The ultimate differentiator

If you’re considering an analog ASIC, specification development, circuit design, and physical layout are the most critical steps. These are the true differentiators between the “doers” and “pretenders” (for more on this, read my article “For a Successful Analog ASIC, First Weed Out the Pretenders”).

They require the highest level of analog design skills. I’m referring to teams of craftsmen that have done hundreds of complex precision analog chips that meet requirements others said were impossible. These individuals typically have 30 to 40+ years of experience and can command salaries exceeding $350K per year. They are scarce, they are expensive, and they are worth every penny.

If you remember one thing from the paper mentioned above, let it be this: human capital is the ultimate differentiator.

The feasibility study: De-risking the design

It all starts with a feasibility study conducted by the engineers who will be designing the chip. Figure 1 below shows the steps involved.

Figure 1 The feasibility study must be conducted by the engineers designing the chip. Source: Javelin ASIC Devices

The feasibility study is a risk aversion step intended to identify and quantify risks and establish a plan to mitigate them for a successful result. Additionally, it allows the design team to quantify the time required to do the design and assess a fixed cost to complete it.

Done properly, it can take up to two months to complete the study; more if significant invention is involved, less if the chip is an amalgamation of off-the-shelf existing silicon. These costs range from $20K to $70K and are always credited to the full development if a contract is executed. Since some simulation is required, costly software tools are involved early on.

Figure 2 Human capital and software tools unite in the design phase. Source: Javelin ASIC Devices

Design phase: From specification to architecture

Several things occur during the design phase. The preliminary specification becomes a working document and grows from a 4–6-page product definition paper to an in-depth datasheet that may well exceed 50 pages, becoming more detailed with minimum and maximum limits, definitions of registers, power requirements, and more.

The thoroughness of the datasheet is a measure of the craftmanship of the design team. The datasheet drives the wafer fabrication process selection that matches the requirements for voltage, current, noise, precision, cost, and more to the most optimal foundry and a specific process.

The architecture of the ASIC is defined in functional blocks and teams with decades of experience with those blocks (charge pumps, 24-bit and higher A/D converters, precision low-drift Vrefs, and chopper-stabilized amplifiers) are created and assigned. Whenever possible, programmability using registers is added to tighten Gaussian distributions and maximize yields.

Collaboration, reviews, and designer governance

Weekly calls with the customer’s engineers are scheduled to report on status progress and offer design alternatives that may improve performance, reduce chip size (cost), avoid environmental impacts (electrical noise and temperature variations), add functionality, and more. At the completion of each major block, a design review should be scheduled with the customer’s engineering team that dives deep into a transistor-level explanation of how each aspect of the block works. It includes schematics, simulation result targets compared against specification requirements, and an overview of any external components required.

Software design tools are acquired for the duration of the project. Quarterly calls with customer corporate management are established to review schedules and cash flows. Digital teams are assembled to manage logic, memory, and register requirements.

Test strategy: Third-party vs. custom systems

In parallel with the design of the ASIC itself is the design of the test system. Sometimes evaluating a precision analog ASIC can be as challenging as the chip itself. There are two schools of thought. One is to generate a test specification to be supplied to a third-party test house that fits the capabilities of their array of commercially available test systems.

These companies will review the specifications and recommend which brand of tester is best suited. They will charge a one-time fee for the development of any unique hardware and software program needed to interface your ASIC to their tester. Getting everything up and running can easily cost between $100K and $200K.

An alternative that Javelin uses is to develop a custom test system, specifically tailored for the ASIC. We build two identical systems—one for the wafer probe and one for the final test of the packaged chip. They can be collocated in any test house and interface with the required handlers, or they can be stand-alone.

We prefer this approach because it assures perfect correlation between the wafer probe and final testing. And surprisingly, it’s less expensive. This approach offers complete flexibility in moving testing from one location to another without incurring duplicated tooling costs.

Custom ASIC economics vs. commodity products

When a commodity analog semiconductor company develops a standard product intended to be sold to thousands of disparate customers, they absorb all development costs and amortize it into their unit pricing, hoping their marketing department has identified sufficient sales potential to recover the costs and still show a profit in the long term.

However, when a custom ASIC is involved, the story changes slightly. There is only one customer, and it’s responsible for paying for the complete development. In exchange, it gets exclusivity to the chip.

Exclusivity is important because the justification for paying development costs often includes integrating proprietary IP or creating new inventions to achieve performance advantages over competitors using off-the-shelf components. Other advantages include a significantly smaller size, lower power consumption, protection from product obsolescence, and much more.

Software tools: Powerful but expensive

Although the development costs associated with creating the new IC also include wafer fabrication and package assembly, I want to stay focused on human capital and software tools for a moment. There’s more to it than meets the eye. For those not familiar with chip development costs, the numbers can be intimidating.

While the semiconductor industry often focuses on the multi-billion-dollar capital expenditures of leading-edge digital nodes, the economics of analog IC development follow a distinctly different trajectory. Development does not involve huge capital equipment investments. The investment comes in the form of human capital and tool rental.

Over the past few decades, the tools for supporting analog chip design have improved dramatically, driven in part by the growth in analog applications in automobiles, consumer products, and sensor calibration and signal conditioning, in which precision and accuracy, along with quality and reliability, are of paramount importance. A few of the most popular tools used by analog designers include Cadence Virtuoso and Spectre, Synopsys Primetime, and Mentor Graphics Calibre.

Regardless of whom you select to do your analog ASIC, they will likely use these same tools, as they are available to everyone. However, they are expensive and these costs need to be accounted for. Prices aren’t published and NDAs prevent users from disclosing them, but estimates for a single, fully featured seat for analog/mixed-signal design (layout and simulation) range from $150k-$300k per year. A seat is typically one “open window” for one user, so you can see how the dollars add up quickly.

Prototype fabrication and mask costs

Most silicon fabricators offer multi-product wafers (MPW) for some or all of their processes. These are highly valuable tools for seeing silicon samples at a low cost. They afford the ability to locate and remove any errors prior to production.

On popular processes, they are run monthly, but on others they are run less so, maybe two, three, or six times a year. If you miss the window with an available tape-out, it could be a long wait. MPWs are not required, but when available, they are an important step in evaluating early silicon and debugging test systems well ahead of production.

Whether engaging an MPW or not, the final significant tooling expense is the production mask set. Prices vary from wafer fab to wafer fab and are dependent on the number of masks required to make the ASIC. Figure on spending $75K to $150K.

Figure 3 Test and assembly operations are a critical part of ASIC fabrication costs. Source: Javelin ASIC Devices

Experience matters: Mitigating risk in ASIC development

If an off-the-shelf new chip design runs into a problem, the semiconductor company has the option to simply delay introduction while their engineers sort things out. That is not an option for your ASIC. You are counting on it to be available on a specific date to support the launch of your new or next-generation product.

Don’t be fooled by companies claiming they have been in business for 20 or 30 years. That means very little. What’s important is the experience of the folks doing the work. How long has each engineer been designing analog ASICs?

Everyone makes mistakes, but mistakes are part of learning. You need teams that have made the mistakes decades ago and learned from them. Don’t let your project become a learning experience for novices. You deserve to see the resumes of the people responsible for your ASIC. Ask to see them and insist on speaking with the engineers themselves.

Which brings up another point: you deserve to have direct access to any engineer working on your ASIC. Don’t accept some project manager or marketing manager acting as a gate keeper to be the focal point for all communications between you and your supplier. They add no technical value and insert delays in communications, which more often than not are time critical.

Bob Frostholm is co-founder and CMO of Javelin ASIC Devices.

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• 7 Steps to a Successful Analog ASIC
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• 7 myths of analog and mixed-signal ASIC design
• A 12-point overview of the advantages of custom analog ASICs

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