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Built around Arduino and a special breakout board, it drives a relay when it detects and recognises a previously paired RFID tag; it is also suitable for reading contactless NFC cards.

RFID and NFC: a technology that is now widespread

Recognition and access control performed by turnstiles, gates and motorised doors driven by RFID electronic systems is now an established reality in many fields, involving both companies and apartment buildings; by now many of us carry in our pocket a passive wireless tag (transponder) that lets us enter the workplace, buy a drink from a food vending machine, get into the gym, but also open the front door of the house and clock in at work. The same technology, known as RFID, is the basis of the most recent and now widespread contactless electronic identification and payment systems, also known as NFC, built into debit cards or into mobile devices such as smartphones and tablets.

We devote the project you find in these pages to RFID/NFC technology; it is both a complete application for access control and a development and prototyping platform for very short range identification systems based on passive or active transponders (tags).

How a passive RFID tag works

Before getting into the heart of the project, let us make a preamble that helps in understanding how RFID works: systems of this kind behave as true transponders and are typically passive, meaning that the portable identification device (called a tag) only acts when it is excited by the fixed exciter system and has no autonomous power source of its own. Here is how it works: the detection system has an exciter circuit that generates an electromagnetic field, typically at low frequency (normally around 125 kHz, but systems operating at higher frequencies exist) and radiates it through a coil over a short distance; this ranges from a few cm for contactless payment systems and NFC (where transmission must be kept as narrow as possible to avoid fraudulent interception by hackers and malicious people) to a few tens of cm for pedestrian and vehicle access points.

Induction and identification of the tag

When a tag enters the electromagnetic field, an alternating voltage is induced in the coil inside it; this is rectified by a diode and charges a capacitor, between whose plates enough energy remains to run the tag’s logic. That logic is based on an encoder which, once powered, generates an identification code (usually unique) that drives the base of a transistor; at every logic high level the transistor conducts and electrically “loads” the coil, causing an induced reaction in the coil of the exciter circuit, as a result of which each conduction increases the current draw.

Through a sense resistor the exciter circuit detects the pulses and reconstructs the code produced by the encoder, thus managing to identify the tag. During the periods when the transistor loads the coil, the diode prevents the capacitor from discharging, so that the energy stored in it keeps the encoder running for the time needed to complete identification.

The project

That said, let us look at what the RFID identification system consists of; essentially it is a programmable transponder electronic lock with a user interface for easy use.

The project is based on an Arduino Uno fitted with an LCD Shield, a 5 volt relay module and a module specifically for reading RFID tags and NFC in general. The module in question ( Fig. 1 ) is the PN532, a NFC/RFID tag reader/writer (writing applies to active tags) with a coil integrated in the PCB, I²C, SPI and HSU (High Speed UART) communication interfaces, plus an indicator LED. The board, measuring 43x41x4 mm, can work as an RFID card reader/writer, as an NFC reader for Android smartphones (it only works with some types) and in wireless peer-to-peer mode between two similar devices.

The PN532 module: interfaces and supported tags

The circuit works with a voltage from 3.3 to 5 V and the communication interface, available on a row of pads on one side of the board, is selected via dip-switches as shown in Table 1 . In reality the board, as you can see in Fig.1 , carries two rows of contacts: one with four pads and one with 8; together they form both the data interfaces and the service connections, that is, power supply and control signals.

The row of four pads carries the I²C bus, namely SCL, SDA, common ground and power supply; the 8-pad row carries the complete SPI bus, so SCK, MISO, MOSI and SS, plus Vcc, GND, reset (RST0) and IRQ, which are pins to be used for direct control from a microcontroller: in particular IRQ provides a signal every time a tag detection is made, to request the microcontroller’s attention.

Supported tags and reading distance

Among the tags supported by the module are Mifare 1k, 4k (Mifare is a standard created by NXP Semiconductors and widely used in RFID and NFC cards), Ultralight and DesFire cards, as well as ISO/IEC 14443-4 cards such as CD97BX, CD light, Desfire, P5CN072 (SMX), Innovision Jewel cards such as IRT5001 and also FeliCa cards such as RCS_860 and RCS_854. The ISO/IEC 14443 standard provides for operation with an excitation electromagnetic field at a frequency of 13.56 MHz.

The maximum tag capture and communication distance for our PN532 module is typically between 30 and 70 mm. The module can be used with Arduino to build access control devices, etc., thanks to the library provided for managing it.

The library for managing it is supplied by Adafruit and can be downloaded both from the manufacturer’s site and from the page www.futurashop.it/NFC-RFID?search=RFiD (the library is called adafruit pn532).

Practical build

Good, let us now move on to assembling the system components; to sum up, the hardware as a whole consists of:

• Arduino UNO;
• LCD Keypad Shield (1686-SHIELD-LCD);
• RFID module (2846-PN532);
• 5V-10A relay module (2846-RELAY1CH).

The whole set is available from Futura Elettronica (online shop www.futurashop.it) and the product codes are those shown in brackets. Once the hardware has been obtained, it must be connected with Arduino jumpers following the connections given in the wiring diagram you find in these pages.

As for the RFID module, the connections to Arduino, or rather to the LCD Shield, are:

• the SCK contact goes to pin 13 of the shield;
• the MISO contact goes to pin 12 of the shield;
• the MOSI contact goes to pin 3 of the shield;
• the SS contact goes to pin 2 of the shield;
• the VCC contact goes to the 5V pin of the shield;
• ground (GND) goes to the GND pin of the shield.

Relay connections and user interface

The relay module, on the other hand, connects with its 5V to the 5V of the Arduino (together with the power supply of the RFID module) and GND to a free GND pin of the Arduino (or of the LCD Shield); the relay’s control input must be connected to pin D5 of the Arduino (of the Shield).

To manage the LCD shield, which forms the user interface of the system, the sketch includes the appropriate library (also downloadable from www.futurashop.it), which allows the alphanumeric display to be controlled and the buttons to be read.

Speaking of buttons, in the project they have the following functions:

• UP and DOWN let you move between menu items;
• SELECT is used to choose a menu item;
• DOWN starts interrogation of the transponder;
• LEFT, from the display’s initial screen, lets you test the output relay;
• RST; returns you to the initial screen.

To use the system we recommend enclosing all the electronics in a plastic case machined so that the buttons protrude and the LCD display remains visible; the RFID board can be glued with silicone sealant just below the front panel of the case, which, being plastic, does not interfere in any way with the electromagnetic field generated by the coil or with detection of the induced reaction.

That said, we can look at the system’s features.

Start-up and main menu

So let us take a look at how the whole thing works, starting by saying that it must be powered through the DC jack of the Arduino Uno with a mains power supply able to deliver at least 500 milliamperes and a voltage of 9 to 10 volts.

As soon as the device is powered up, the LCD display shows the words “Access Card Reader” ( Fig. 2 ).

The message “Lettura: Lettura in corso” (Reading: reading in progress) is then shown. The system will then read any tag present within range (the electromagnetic field) of the module, replying with a message granting or denying authorisation. Of course, all this only makes sense if the system has previously stored one or more tags, otherwise authorisation will always be denied; when authorisation is granted, the relay is activated.

From the main screen, pressing the “DOWN” button takes you to the menu, which offers the following options:

• Read Mode (Fig. 3), corresponding to the initial tag reading procedure;
• Edit Mode (Fig. 4), corresponding to the procedure for learning a tag and writing it to the Arduino memory;
• Delete Mode (Fig. 5), which lets you delete all the tags already learned whose code is in the Arduino memory.

Use the “UP” and “DOWN” buttons to scroll through the options, and press “SELECT” to select one. Press “RST” to return to the initial procedure at any time. While the “Main menu” screen is displayed you can press the “LEFT” button to test that the relay works correctly.

Edit mode: registering a new tag

Let’s briefly look at the modes, starting with Edit Mode: once selected, it lets the user register a new tag.

The procedure, which starts when the display shows the screen in Fig. 4, requires you to pass the tag to be learned over the module at a maximum distance of 7 cm, at which point the system automatically acquires its code and saves it among the authorised ones. If the tag is not detected (you will notice because the display content does not change), try passing it at a shorter distance until it is detected.

Bear in mind that the module can recognise certain types of tag, which are also the most common ones, so the tags you want it to learn must be among those summarised a few paragraphs back.

In any case, if the storage operation succeeds, the display will show the message “TESSERA SALVATA” (Fig. 6).

At this point, if you stay in Edit Mode and pass the same tag you have just learned again, its code is removed from memory; this deletion state is confirmed by the message “TESSERA RIMOSSA” (Fig. 7).

Delete mode and read mode

Let’s move on to Delete Mode, which starts when the display shows the screen already seen in Fig. 5; from there, to remove all the previously learned tags from memory you have to press the SELECT button; once you do, the display shows the screen visible in Fig. 8.

When the operation is complete you have to press the “RST” button to return to the main menu. Once the memory has been cleared, the display shows the screen visible in Fig. 9.

We finish with Read Mode: when you enter it from the main menu (with the screen of Fig. 3 on the display) and pass a tag in front of the module, what is shown in Fig. 8 appears.

In practice, when the module detects a tag within its field of action it interrogates it, and during this phase the display shows the message of the aforementioned figure. When the read is complete, two conditions shown in Fig. 9 can occur: if the tag is one of those already learned in Edit Mode, it is recognised and the display shows the message Acc. Consentito, together with the relay switching on. If instead the tag is not recognised as one of those already learned, Acc. Negato is shown and nothing happens to the relay.

Customising the firmware

These are all the functions provided, but of course by “tinkering” with the firmware you can implement others; for example, you can add various kinds of local signalling to the relay output, such as a buzzer that sounds when a tag is recognised or an LED that lights up when the aforementioned condition occurs.

If you want, without “tampering” with the Arduino sketch you can add an LED or a buzzer by connecting them in parallel (the LED requires a limiting resistor, typically 270 ohm…) to the relay coil, that is in series with the collector of an NPN transistor connected in common emitter with its base driven by the Arduino Uno output that controls the relay board.

The firmware

Having looked at the hardware and described how it works, let’s spend a few lines on the firmware that manages the electronic lock.

The sketch to load into the Arduino Uno board is quite bulky, so in Listing 1 we only reproduce the most significant portion, the one dealing with normal operation. You can download the whole sketch (.ino file) together with the files for this issue of the magazine.

Listing 1

if (success) { // Display some basic information about the card if(debug) { Serial.println(“Found an ISO14443A card”); Serial.print(“ UID Length: “);Serial.print(uidLength, DEC);Serial.println(“ bytes”); Serial.print(“ UID Value: “);nfc.PrintHex(uid, uidLength); } cardid = getCardIdAsInt(uid,uidLength); //is MASTER if (cardid == uid_master) { master_mode = 1; master_mode_counter = 0; if(debug) Serial.println(“MASTER detected, going into MASTER MODE “); } // is not MASTER else { int32_t findUid = findRfidInEeprom( uidLength, uid); // is MASTER MODE, include or exclude RFID from storage if(master_mode == 1) { // card rfid already exists so exlude it from storage if( findUid != -1) { if(debug) { Serial.println(“removing card from eeprom”); Serial.println(“ “); lcd.setCursor(0,1); lcd.print(“Tessera Rimossa “); delay(2000); lcd.setCursor(0,1); lcd.print(“Modifica… “); } deleteRfidfromEeprom(findUid, uidLength); } // card rfid not found in storage so include it else if (findUid == -1) { // check if space to store rfid available int32_t storageAddress = getEepromStorageAddress(uidLength); // storage available if(storageAddress >= 0) { if(debug) { Serial.print(“storing card in position = “);Serial.print(storageAddress);Serial.println(“ “); } // storing card writeRfidToEeprom( storageAddress, uidLength, uid); lcd.setCursor(0,1); lcd.print(“Tessera Salvata “); delay(2000); lcd.setCursor(0,1); lcd.print(“Modifica… “); } else { // no storage space available or error if(debug) Serial.println(“memory full or error”); } } master_mode = 0; } // no MASTER MODE, authorise or deny door access else { // card authorised if( findUid != -1) { // open door // write routine for door access, example set an output to high if(debug) Serial.println(“Card authorised”); lcd.clear(); lcd.setCursor(0,0); lcd.print(“Lettura:”); lcd.setCursor(0,1); lcd.print(“Acc. Consentito”); digitalWrite(11,HIGH); delay(2000); digitalWrite(11, LOW); lcd.setCursor(0,1); lcd.print(“Lettura in corso”); } else { // deny access if(debug) Serial.println(“Card not authorised”); lcd.clear(); lcd.setCursor(0,0); lcd.print(“Lettura:”); lcd.setCursor(0,1); lcd.print(“Acc. Negato”); delay(2000); lcd.setCursor(0,1); lcd.print(“Lettura in corso”); } } } delay(500); }

As usual the firmware starts with the definition of the I/Os and the inclusion of the libraries, of which there are two in this project: the one for the RFID reader and the one for the LCD Shield.

The setup follows and then we come to the portion shown in the aforementioned Listing 1, where, depending on the mode we have set using the shield’s buttons, the card (the RFID tag) will be stored, deleted or, in the case of “normal” operation, simply read to compare its identification code with the data in memory; in this case, if the code read is already present in the Arduino Flash memory, the relay on the board is activated.

The relay is activated in pulse mode, that is monostable, and the time it stays in the “energised” state (and therefore with the relay contact closed) is 2 seconds, as defined by this portion of code:

digitalWrite(11,HIGH); delay(2000); digitalWrite(11, LOW);

where digitalWrite (11, HIGH) is the instruction that activates digital line 11 (which controls the relay board), delay(2000) sets the time it stays at high level through the delay with which output D11 returns to low level and, finally, digitalWrite (11, LOW) brings the aforementioned Arduino line back to logic low.

If you want, you can change the relay activation time by changing, in the sketch, the value in brackets after delay, remembering that it is in milliseconds.

Conclusions

So we have reached the end of the description of this project, which, although it was born as an electronic lock with a transponder key, can be used for a variety of applications and, with a few tweaks to the firmware, can find use in identification via NFC thanks to the full support provided by the sensor board and its pairing with a Personal Computer.

Related products

• RFID NFC 13.56 MHz Read-Write Module
• LCD keypad shield for Arduino
• NFC RFID reader with two transponders

The post NFC/RFID Lock with LCD appeared first on Open Electronics.

Nuvoton Technology introduces the NSP2340BA24E Smart Buzzer, integrating voice capabilities and buzzer driving functions into a single IC. Designed to extend the capabilities of conventional piezo buzzers beyond simple beep sounds, the NSP2340BA24E enables direct playback of voice and sound effects, bringing more intuitive and distinctive audio interaction to home appliances, security systems, healthcare devices, industrial equipment, and other smart applications.

Conventional buzzers have long been widely used in electronic products for audible alerts and operation feedback due to their simple architecture and proven reliability. However, as smart devices become increasingly sophisticated, simple beep patterns alone may not provide the intuitive and informative user experience required by modern applications.

Built around the concept of “Beyond the Beep,” the NSP2340BA24E expands the role of the conventional buzzer by enabling richer and more expressive audio feedback.

From Simple Beeps to Voice & Melody

The NSP2340BA24E Smart Buzzer integrates embedded Flash and a buzzer driver, together with a voltage booster and Class-AB amplifier, enabling direct drive of a piezo buzzer for voice and sound-effect playback. This transforms the buzzer from a simple audible alert component into a more informative audio interface.

With voice and diverse audio content, products can communicate operating status, notifications, and warning messages more clearly. Instead of relying solely on different beep patterns to indicate different conditions, the NSP2340BA24E enables more recognizable voice or sound feedback, helping users understand device status more intuitively. This approach allows developers to build upon familiar piezo buzzer designs while creating greater product differentiation and a more engaging audio experience.

Highly Integrated Design for Easier Implementation

The NSP2340BA24E integrates audio content storage, voltage boosting, and buzzer driving capabilities into a highly integrated solution. The NSP2340BA24E supports booster output of up to 24V, along with UART, I²C, and Two-Wire interfaces for host MCU control. It also supports In-System Programming (ISP), allowing audio content to be updated through the host MCU.

With this integrated architecture, developers can more easily introduce Voice & Melody capabilities into products traditionally designed around buzzers, while maintaining flexibility to customize audio content for different products and application requirements.

Expanding the Value of Buzzers Across Smart Applications

The NSP2340BA24E can be applied across a broad range of products requiring audible feedback and status notification. From operation and completion notifications in home appliances to warning alerts in security systems and status feedback in industrial equipment, the NSP2340BA24E allows sound to do more than simply attract attention—it can help users better understand what a device is communicating.

With the NSP2340BA24E Smart Buzzer , Nuvoton extends the conventional piezo buzzer beyond simple beep sounds to richer Voice & Melody experiences, providing developers with greater flexibility in audio design and enabling more intuitive audio interaction for the next generation of smart devices.

The post Nuvoton Introduces NSP2340BA24E Smart Buzzer, Redefining the Buzzer Sound Experience appeared first on ELE Times.

Polar Semiconductor LLC of Bloomington, MN, USA (the only US-owned foundry specializing in high-voltage, power and sensor semiconductors) and IC-Link by imec (the design and manufacturing division of nanoelectronics research center imec of Leuven, Belgium) are collaborating to provide 8-inch production of enhancement-mode (e-mode) gallium nitride (GaN) devices to serve critical markets such as AI data centers, automotive, aerospace & defense, and the industrial grid...

Infineon Technologies AG introduces the XDP8HD40S-1, a high-voltage hot-swap controller designed for digital power path protection and monitoring in next-generation AI server power architectures operating at ±400 Volt and 800 Volt direct current (VDC). As AI clusters scale from 48 V toward higher rack power levels, reliable hot-swap functionality becomes increasingly important for maintaining uninterrupted system operation. The XDP8HD40S-1 enables power modules, converters, GPUs, and server subsystems to be connected and disconnected safely while preserving system integrity, extending Infineon’s power semiconductor portfolio, spanning silicon, silicon carbide (SiC), and gallium nitride (GaN), further into the protection and monitoring layer required for scalable AI infrastructure.

“Future AI data centres require power delivery systems that combine high efficiency, maximum reliability, and comprehensive protection capabilities,” said Magdalene Boebel, Senior Vice President and Business Line Head of Power System ICs at Infineon. “The XDP8HD40S-1 enables system designers to implement reliable hot-swap solutions for ±400 V and 800 V power architectures while providing the monitoring and protection features needed to maximize server uptime and operational efficiency.”

The XDP8HD40S-1 is designed for a range of high-voltage applications, including two-wire 800 V or ±400 V intermediate bus converters and GPUs, 1.500 V intermediate bus converter systems, high-voltage rack and server power delivery, battery backup systems, peak shaving, and 400 V to 800 V single- or dual-side hot-swap implementations. The device is compatible with Infineon’s power semiconductor portfolio, including OptiMOS MOSFETs and CoolSiC JFETs, allowing designers to build efficient, rugged protection stages using the same underlying technologies Infineon has already applied in its 800 VDC AI data center reference designs.

Operating at higher system voltages increases the complexity of controlling inrush current and protecting infrastructure from transient events. The XDP8HD40S-1 integrates digital Safe Operating Area (SOA) control with programmable and preconfigured active protections. Together with a variable pulse SOA control mode (Boost Mode), the device supports optimized startup behavior while maintaining safe operation of the power switch. An integrated gate driver supports external SiC cascode implementations based on a MOSFET and JFET combination, enabling efficient control of high voltage power stages. To further enhance system robustness, the controller incorporates surge immunity protection and supports fast power-switch shutdown with a configurable 1.5 A pull-down current, helping protect AI compute infrastructure during abnormal operating conditions.

The XDP8HD40S-1 supports a broad operating voltage range, with VDDB from 4.5 V to 24 V and VDDA from 4.5 V to 13.2 V, allowing integration into a variety of server and rack-level power systems. For system management and remote diagnostics, the controller includes a PMBus 1.5 interface with enhanced security features for integration into data centre management infrastructure. A built-in black-box recording feature captures critical event information to help accelerate fault analysis and system debugging. Additional protection features include programmable input and output overvoltage and undervoltage protection, external temperature sensor support, and overtemperature protection.

Modern AI server platforms increasingly require real-time visibility into power consumption and system health. The XDP8HD40S-1 addresses this through 12-bit current and voltage analog-to-digital converters, providing measurement accuracies of approximately 1 percent for voltage, 1 percent for current, and 3 percent for power, with analog power monitoring reporting accuracy of 1.5 percent and integrated energy metering for continuous system monitoring. These capabilities support system optimization, predictive maintenance, and power management strategies in high-density AI computing platforms, complementing the reference designs Infineon has already demonstrated for 800 V-to-48 V and direct-conversion architectures now emerging as AI data center rack power continues to rise.

The post Infineon Introduces XDP8HD40S-1 High-Voltage Hot-Swap Controller, Extending its Power Semiconductor Portfolio From Grid to Core for 800 VDC AI Server Architectures appeared first on ELE Times.

HARTING Technology Group, a leading global provider of industrial connectivity, today announced it has joined the NVIDIA MGX ecosystem as a power system component provider for the NVIDIA Vera Rubin NVL72 platform.

HARTING delivers power whip solutions – cable assemblies that distribute power from the building to each rack – as growing AI compute demands reshape how power is distributed within data centres. The solutions span the transition across two generations of NVIDIA MGX power architecture, from 480 VAC to the NVIDIA 800 VDC architecture, designed to support the rapidly increasing power demands of AI factories.

As AI workloads grow and compute density increases, data centres must manage significantly more power within increasingly dense environments without compromising reliability, efficiency or scalability. That shift is placing new demands on the connectivity systems that deliver power to AI compute infrastructure.

“AI is fundamentally changing data centre infrastructure, and HARTING has the engineering expertise to help enable that transformation,” said Philip Harting, Chairman of the Board and CEO, HARTING Technology Group. “Our inclusion in the NVIDIA MGX ecosystem brings our decades of connectivity experience in high power environments, from rolling stock to automotive, to the infrastructure supporting the next generation of AI.” For the NVIDIA MGX platform, HARTING provides a 100A/480VAC power whip for the 3RU 110kW power shelf for NVIDIA Vera Rubin NVL72, supporting the transition to 800 VDC with a next-generation 157A/800 VDC DC-DC power whip connecting the power infrastructure to the compute rack.

“As AI compute becomes more powerful and rack densities increase, the industry has to rethink power distribution from the ground up,” said Christian Gysin, Chief Technology Officer and Member of the Executive Board, HARTING Technology Group. “The transition from 480VAC toward 800 VDC is a significant step in that evolution. Connectivity must support higher power levels while delivering the reliability, safety and scalability these environments demand. That is precisely where HARTING’s engineering expertise comes into play.”

HARTING solutions transmit power, data and signal across mission-critical systems worldwide. The company is drawing on decades of experience in demanding industrial environments and its global engineering and vertically integrated manufacturing capabilities to address the evolving connectivity requirements of AI infrastructure and data centres.

As part of the NVIDIA MGX ecosystem, HARTING will be featured on the NVIDIA AI Factory MGX Ecosystem wall at the OCP Global Summit 2026. The executives from HARTING will honourably attend the NVIDIA MGX ceremony. Besides, two HARTING power whip solutions supporting the NVIDIA Vera Rubin NVL72 platform will also be on display in the HARTING booth (Booth No. C79) demonstrating the power connectivity behind current and next-generation AI infrastructure.

The post HARTING Joins NVIDIA MGX Ecosystem to Power Next-Generation AI Infrastructure appeared first on ELE Times.

As AI workloads drive demand for more scalable and flexible data centre architectures, organizations are looking for faster, more efficient ways to move, store and protect data. Microchip Technology is helping to address these needs by expanding its portfolio of data centre solutions with new innovations in PCIe connectivity, NVMe storage and acceleration that support high-performance computing infrastructure.

“Customers are looking for technology partners that can address multiple challenges across the infrastructure stack while helping simplify design and accelerate deployment,” said Brian McCarson, Corporate Vice President and GM of Microchip’s data centre solutions business unit. “By continuing to expand our portfolio, we’re providing the building blocks needed to create more efficient, secure and adaptable platforms for today’s increasingly distributed and data intensive computing environments.”

Designed to bring PCIe Gen 6 connectivity to space- and power-constrained platforms, the Switchtec PCIe 6.0 Low Lane-Count (LLC) switch provides up to 64 PCIe Gen 6 lanes, 32 ports and flexible x2, x4, x8 and x16 bifurcation options. Integrated Direct Memory Access (DMA) supports efficient peer-to-peer data movement between connected devices while reducing host CPU involvement. Like Microchip’s larger Switchtec Gen 6 devices, the LLC switch features PCIe Multicast and partitioning capabilities along with robust security through hardware root of trust and secure boot technologies. The new device delivers PCIe Gen 6 capabilities with a smaller, lower power footprint to extend support to a broader range of data centre and intelligent edge applications.

To address the industry’s requirements for secure, scalable and AI-optimized storage infrastructure, Microchip is updating its Flashtec SSD controller portfolio with an enhanced version of the PCIe Gen 5 NVMe 5016 controller. Building on the controller’s high-performance, power-optimized architecture, the updated device adds support for Commercial National Security Algorithm Suite (CNSA) 2.0 to help customers prepare for emerging post-quantum security requirements. Dual-port capability enables highly available storage architectures through redundant data paths and load balancing, while advanced virtualization, Quality of Service (QoS) management and flexible programmability help optimize performance. Together, these enhancements extend the Flashtec platform’s ability to address evolving NAND technologies, high-capacity SSD designs and next-generation enterprise, hyperscale and AI deployments.

Microchip is also expanding the capabilities of its Adaptec SmartRAID 4300 family of NVMe RAID storage accelerators with a series of enhancements designed to address practical operational needs. The updates are focused on strengthening storage security, minimizing downtime, expanding data protection and simplifying deployment across a wider range of environments. Self-encrypting drives (SEDs) with both local and remote key management, and RAID 6 and RAID 60 options have been added for increased resiliency and security. Broader platform compatibility is enabled through support for Linux, Debian, Ubuntu and Microsoft Windows 11 environments. Additional updates such as dynamic NVMe configuration for in-service management, persistent event logging and peer-to-peer rebuild support for greater CPU offload help reduce management overhead while minimizing service disruption. StorageCore API support further expands integration flexibility, enabling customers to incorporate SmartRAID management into third-party tools through in-band host applications as well as customized out-of-band BMC management frameworks.

The latest additions reflect the company’s ongoing commitment to advancing the performance, availability and security of next-generation computing platforms. Visit the website to learn more about Microchip’s full portfolio of data centre solutions.

Development Tools

Microchip’s data centre portfolio is supported by a suite of development and management tools, including ChipLink software for configuration, diagnostics, telemetry and debug of PCIe switches. Additional support includes software for device monitoring, configuration and firmware management, Flashtec NVMe controller development resources and Adaptec storage management software.

The post Microchip Expands Data Centre Portfolio to Meet Evolving AI Infrastructure Demands appeared first on ELE Times.

The JetKVM Mini delivers KVM over IP for 39 dollars. The board captures a computer’s video, encodes it in H.264 and sends it to the host over WebRTC. It also drives keyboard and mouse as if they were physically connected. Compared with the original JetKVM, which relied on Linux running on a Rockchip RV1106G3 SoC, the Mini uses an ESP32-P4X for video capture, H.264 encoding, USB and the rest of its functions. The project therefore moves to RISC-V and to a FreeRTOS firmware based on ESP-IDF.

The Mini variant has a 100 Mbps RJ45 Ethernet port. The Mini W adds dual-band WiFi 6, Bluetooth and 802.15.4 for Zigbee and Thread thanks to an ESP32-C5 module. Pricing is 39 dollars for a single unit and 33 dollars per unit in a three-pack bundle. The Mini W costs 42 dollars, or 36 dollars per unit in the three-pack bundle.

ESP32-P4X: dual-core 400 MHz RISC-V CPU and 32 MB of PSRAM

The heart of the Mini is Espressif Systems’ ESP32-P4X. Inside there is a 32-bit dual-core RISC-V HP CPU running at up to 400 MHz, with an AI instruction extension and single-precision FPU, plus a RISC-V LP MCU core at up to 40 MHz. Memory includes 768 KB of HP L2MEM, 32 KB of LP SRAM, 8 KB of TCM, 32 MB of PSRAM, 128 KB of HP ROM and 16 KB of LP ROM. For storage there is 16 MB of flash and a microSD card slot, used for virtual media.

The VPU supports the H.264 and JPEG codecs, with a Pixel Processing Accelerator and a 2D DMA controller. The GPU is a 2D Pixel Processing Accelerator. The display is a 240 x 240 pixel non-touch IPS panel. The HDMI input goes up to 720p60 or 1080p30, with 4K supported through JetKVM OS Services. The H.264-encoded stream is sent to the host over WebRTC.

USB ports, 5V/500mA power and 42 x 42 x 23 mm dimensions

On the connectivity side, the Mini offers two USB 2.0 Type-C ports. The main one runs at 480 Mbps, the second at 12 Mbps. Power is 5V/500mA through a USB Type-C port. Dimensions are 42 x 42 x 23 mm, so the device fits in a fist. Those who want to rework the firmware development side will find in the catalogue the development board with Wi-Fi, Bluetooth and USB Type-C connector, useful for getting familiar with the ESP32 ecosystem before getting hands-on with the KVM.

• 32-bit dual-core RISC-V HP CPU up to 400 MHz with AI extension and FPU
• RISC-V LP MCU core up to 40 MHz
• 768 KB of HP L2MEM, 32 KB of LP SRAM, 8 KB of TCM
• 32 MB of PSRAM, 128 KB of HP ROM, 16 KB of LP ROM
• 16 MB of flash and microSD slot for virtual media
• 240 x 240 pixel non-touch IPS display
• 100 Mbps Ethernet over RJ45 in the Mini variant
• Dual-band WiFi 6, Bluetooth and 802.15.4 in the Mini W via ESP32-C5

The software runs on FreeRTOS with the ESP-IDF framework. Capture and encoding go through JetKVM OS services, while transport to the browser relies on WebRTC. Those who want to follow development and read the code will find the project’s code repository, where the firmware is published and updated. Open source firmware was planned from the start, so the Mini also suits anyone who wants to modify the capture logic or add features.

What a KVM over IP like the JetKVM Mini is for

A KVM over IP is useful when the computer to be controlled is far away or has no operating system running. The Mini gets into the BIOS, the boot screen or the bootloader, because it works at the level of the video signal and keyboard and mouse emulation. That is why it is used for rack servers, for mini PCs without a monitor and for test machines in the lab. The 100 Mbps Ethernet port is enough for a 1080p30 stream, while the W variant frees you from the network cable.

The 240 x 240 pixel IPS display shows status information directly on the device, without opening the browser. The microSD slot also lets you mount ISO images as virtual media, so an operating system can be installed remotely. Finally, the second USB 2.0 Type-C port at 12 Mbps handles the emulation peripherals. Those who want a starting point for their own IoT experiments will find in the catalogue the development kit for IoT projects with WiFi 6 and integrated peripherals, a way to get practice with the radios in the Espressif family.

Source: https://github.com/jetkvm

Related products

• ESP32 – Development board with Wi-Fi, Bluetooth and USB Type-C connector
• ESP32-C6-Zero Wi-Fi 6 IoT Development Kit

The post JetKVM Mini: $39 KVM over IP Built on ESP32-P4X appeared first on Open Electronics.

At the Open Compute Project (OCP) Global Summit, Texas Instruments (TI) debuted the first analog-to-digital converter (ADC) to enable 24/7, low-power, event-based remote monitoring at nanosecond resolution.

As AI workloads rapidly increase, data centres operators face significant challenges around power instability, inadequate real-time monitoring and signal degradation, all of which can lead to costly downtime. TI is addressing these challenges through its new ADC device and other analog solutions designed to tackle the challenges of scaling artificial intelligence (AI) infrastructures. Demonstrations on display in TI’s booth, No. E45, at OCP include:

• Real-time nanosecond-level telemetry: TI’s ADC34DSO75 is the industry’s highest performance 3 gigasamples per second (GSPS) ADC, enabling 24/7, low-power, event-based remote monitoring at nanosecond resolution – thousands of times faster than what current solutions offer. Existing monitoring solutions often fail to detect the nanosecond-level power-rail glitches that cause costly, unplanned downtime in data centres. By combining ultra-high speed sampling with advanced on-chip digital signal processing in a small form factor, the ADC34DSO75 detects and captures transient fault events in real time.

As the industry’s first solution to offer fully remote, event-based telemetry, the device eliminates the need for on-site debugging and oscilloscopes. By providing continuous, high-resolution monitoring of low-voltage, high-current power rails, the ADC34DSO75 helps data centres minimize downtime – which can cost operators hundreds of thousands of dollars an hour – while optimizing grid power efficiency. This compact, efficient solution offers hyperscalers unmatched remote diagnostic capabilities at a fraction of the size and cost of conventional monitoring methods.

• Reliable high-voltage power delivery: The LMI800PS is the industry’s first 800V isolated hot-swap controller, replacing a complex discrete solution requiring five integrated circuits with a single high-density package that delivers in-rush current and power path protection. The integration of an isolated bias supply and PMBus telemetry reduces board area by more than 60% and simplifies high-voltage designs. The LMI800PS enables safe power insertion and fast fault isolation, meeting safety standards with 5kVrms reinforced isolation and more than 8mm creepage. This prevents a single load failure from disrupting the shared power bus and maximizes data centres stability. Supporting both ±400V and 800V distributions, the device provides a scalable solution for diverse rack architectures, accelerating the deployment of high-efficiency power systems required for next-generation AI infrastructures.
• Ultra-low jitter signal integrity: The LMK6B is a bulk acoustic wave (BAW)-based oscillator that delivers best-in-class jitter performance and power-supply rejection ratio (PSRR). As data center transmission rates approach 3.2Tbps, the margin for timing error shrinks significantly, and even minute jitter can increase bit error rates and cause system instability. The LMK6B provides industry-leading jitter performance of 9.6fs at 625MHz, ensuring reliable performance and preserving signal integrity for next-generation, AI-driven networking infrastructures.

“As AI workloads drive massive scale, the need for real-time visibility and architectural stability has never been greater,” said Karthik Vasanth, Vice President and General Manager for TI’s Data, Converters and Clocks business unit. “By delivering industry-leading solutions for high-speed telemetry, advanced power protection and precision timing, TI is enabling hyperscalers and operators to design the next generation of AI data centres with optimized performance and minimal downtime.”

The post TI Unveils New ADC to Enable Nanosecond-Level Telemetry, Minimise Downtime in AI Data Centres appeared first on ELE Times.

AI-assisted chip engineering is increasingly capable of reaching meaningful design milestones. But reaching GDS does not establish that the resulting engineering outcome is better. If AI agents are going to participate more deeply in semiconductor design, the next question must move beyond capability: Did the AI beat an engineering benchmark that engineers already trust?

And if it appears to have done so, can the engineering data prove the improvement rather than relying on one successful run or thousands of tool logs? That is the natural next step in the trust discussion.

The problem is no longer only whether AI can make engineering decisions. It’s whether those decisions can be evaluated using the same discipline engineers already use to evaluate designs. A useful framework is:

Target workload → Workload/Memory model → Engineering benchmark → DOE → RSM/Regression → Predict → Verify with EDA → Measure error → Compare → Repeat

Two ideas are central. First, the benchmark must represent the workload the silicon is actually intended to serve. Second, the AI-generated design history must be converted into measurable engineering evidence.

Benchmark must start with the workload

For an AI accelerator, frequency, power, area, and timing are not really the beginning of the problem. They are consequences of the workload. Relevant assumptions may include model type, context length, concurrency, compute intensity, memory footprint, HBM capacity, memory bandwidth, interconnect traffic, and communication behavior.

A long-context inference workload may create very different memory requirements from a short-context workload. A compute-bound workload may favor one architecture. A memory-bound workload may favor another.

So, before asking whether AI beat a benchmark, engineers first need to ask: Was the benchmark derived from the workload the chip is actually expected to serve? Because a statistically excellent optimization against the wrong workload is still the wrong design.

The chain therefore begins with:

Workload → Compute and memory behavior → Hardware requirements → Engineering benchmark

Only after that do conventional design metrics become meaningful.

Define a benchmark engineers already trust

The reference implementation could come from an existing production design, a previous tapeout, an experienced engineering team, a conventional EDA flow, or another controlled implementation. The important point is comparability.

The AI-generated design and the reference should be evaluated against equivalent conditions:

• Workload
• Process technology
• PDK and libraries
• Frequency target
• Timing requirements
• Power budget
• Area constraint
• Operating corners
• Physical-design constraints
• Memory requirements
• Sign-off requirements

Against the same workload and engineering problem, what did the AI actually improve? Then the comparison becomes meaningful.

Passing the requirement isn’t enough

A benchmark should include margin, not merely pass/fail. Suppose two implementations both reach 2.2 GHz. One closes timing with +5 ps of margin. The other closes with +45 ps. Both technically pass. But they are not equivalent engineering results.

The same principle applies to power, area, IR drop, EM, thermal behavior, routing, memory bandwidth, and corner margin. The useful question becomes: How far inside the acceptable engineering region did the AI place the design?

That is more informative than simply asking whether it crossed a threshold.

AI creates an engineering dataset

An AI-assisted design process may explore far more alternatives than a human team could practically investigate manually. Those iterations can contain combinations of:

• Frequency
• WNS/TNS
• Power
• Area
• Placement
• Congestion
• Routing
• IR drop
• EM
• Thermal behavior
• Memory behavior
• Physical violations

Those observations should not automatically be treated as disposable logs. They can become an engineering dataset. The question then becomes: Can the data describe the design space well enough to evaluate the AI result quantitatively?

DOE can structure the exploration

Design of experiments (DOE) provides one established way to organize the search space. Possible controllable variables might include floorplan parameters, placement density, clock constraints, cell sizing, buffering, voltage, routing strategy, power-grid parameters, memory configuration, or other design-specific controls. Measured responses could include timing, frequency, power, area, congestion, temperature, IR drop, EM, memory bandwidth, and physical violations.

Conceptually, engineering response = f (design variables)

For AI accelerators, workload parameters can also enter the problem: engineering response = f (design variables, workload variables). That allows the analysis to examine not only how the design responds to physical controls, but how sensitive it is to changing workload assumptions.

Turn data into a predictive model

Response surface methodology, regression, or other surrogate modeling approaches can then be used to describe relationships in the explored design space. The exact mathematical model is less important than the engineering principle: Do not treat thousands of AI-generated engineering states as unrelated observations. Build a quantitative model of the design space.

That model can expose useful relationships. Which variables dominate timing? Where does frequency improvement become expensive in power? When does area reduction create unacceptable congestion? How sensitive is memory demand to workload assumptions? Where does the feasible engineering region begin to disappear?

Now the AI-generated history becomes more than activity. It becomes interpretable engineering evidence.

The model must earn trust too

Regression does not automatically make a model trustworthy. Useful statistical measures may include R², adjusted R², predicted R², RMSE, residual behavior, and lack-of-fit. But for this application, there is an even more important test: How accurately does the model predict the next actual EDA result?

Suppose the model predicts: WNS = +25 ps and the actual EDA result is: WNS = +23 ps. That is useful predictive agreement. If the prediction is +25 ps and the actual result is −40 ps, the model has missed something important. Prediction error can therefore become part of the engineering evidence.

Across repeated runs, engineers can ask:

• Is the error small?
• Is it stable?
• Is it biased?
• Is it improving?
• Does it become worse in a particular design region?

That leads to one of the most important principles in the framework: The AI should not only show that the design improved. It should also show that its prediction of the design agrees with actual engineering results. Trust increases when prediction and engineering reality repeatedly agree.

Compare the distribution, not the best run

One good result is not enough. The AI-assisted process should be repeated under controlled conditions. For important engineering responses, evaluate:

• Mean
• Standard deviation
• Percentiles
• Confidence interval
• Range
• Outliers
• Success rate
• Margin relative to requirements

The question is: What does this method usually produce, and how tightly distributed are the outcomes? One exceptional tapeout is interesting. A repeatable distribution of strong outcomes is much more convincing.

That is especially important when the system contains stochastic optimization, multiple agents, changing starting points, or large search spaces.

Optimization quality lives in the trade-offs

A design can improve one metric while becoming worse elsewhere. Useful relationships may include:

• Frequency vs. power
• Frequency vs. area
• Timing margin vs. power
• Area vs. congestion
• Performance vs. thermal density
• Performance vs. memory bandwidth

The important question is not simply whether one number improved. It is: Did the AI discover a better engineering trade space for the target workload? That is a much stronger benchmark than asking which run produced the highest frequency or smallest area.

The benchmark must be able to move

AI hardware introduces another complication. The workload itself can evolve while the silicon is being designed. Model architecture can change. Context length can increase. Concurrency can grow. Memory behavior can shift. The balance between compute and communication can change.

An accelerator optimized perfectly against one workload assumption may reach tapeout only to discover that the target has moved. So another useful question is: How sensitive is the AI-generated design to plausible changes in workload assumptions?

So, the objective is not to design one chip for every possible future workload. It is to understand whether the useful engineering region is broad or narrow.

A trustworthy method must be able to say “No”

A good evaluation framework should not exist only to prove that AI works. It must also be capable of proving that it did not. Perhaps frequency improves but power and area deteriorate enough that the conventional benchmark remains better.

Perhaps the average result improves but variability becomes unacceptable. Perhaps the model fits historical observations but predicts new EDA results poorly. Perhaps one impressive result hides a low overall success rate. Perhaps the AI optimizes the silicon well against a workload assumption that is no longer representative.

A trustworthy methodology must therefore be capable of concluding that, for this workload and engineering problem, the AI-assisted approach did not beat the benchmark. That is part of engineering trust.

Trusted EDA can remain the arbiter

None of this requires AI to replace established sign-off tools. A practical model is:

AI-assisted exploration and optimization → Trusted conventional analysis and sign-off

AI may perform more of the search, optimization, debug, and closure work. Established EDA can remain the independent engineering reference. The immediate test is therefore not whether AI becomes the sign-off authority. It is: Can AI repeatedly produce designs that survive trusted sign-off?

That makes adoption much more practical.

Manufacturing alignment is the final check

Even after the AI beats the design benchmark, one additional question remains. Before hardware exists, actual manufacturing yield and reliability are still unknown. But the tapeout already contains indicators of how demanding the physical realization may become:

• Routing density
• Local current density
• Thermal concentration
• Physical margin
• Variation sensitivity
• Die area
• I/O requirements
• Package requirements
• Test complexity

So engineers should ask: Did the AI achieve the improvement in a way that remains reasonably aligned with the intended manufacturing target? This does not claim to predict actual manufacturing yield. It asks whether the AI won the design benchmark by creating a much harder downstream physical problem.

From AI capability to engineering evidence

The complete framework is:

Target workload → Workload/Memory model → Engineering benchmark → DOE → RSM/Regression → Predict → Verify with EDA → Measure error → Compare → Repeat

The result is not an AI score. It is engineering evidence. Target workload defines what the silicon must execute. Workload/Memory model translates that workload into compute, bandwidth, capacity, and communication requirements.

Engineering benchmark establishes the trusted reference and required margins. DOE structures the exploration. RSM/Regression models the engineering response space. Predict estimates the outcome of the next move.

Verify with EDA tests that prediction against engineering reality. Measure error quantifies predictive accuracy. Compare evaluates improvement, margins, and trade-offs against the benchmark. Repeat establishes whether the result is reproducible.

The question for the industry

AI-assisted semiconductor engineering is increasingly demonstrating that AI can perform meaningful chip-design work. The next challenge is harder. It must prove that the engineering result is actually better.

That requires the correct workload, a benchmark engineers trust, quantitative modeling, predictions tested against real EDA results, and measured prediction error, repeated experiments, trade-off analysis, and trusted sign-off.

The question therefore becomes: Can AI beat a benchmark engineers already trust for the workload the silicon is intended to serve—and can the engineering data prove that it did? That is a much higher standard than an impressive demonstration.

But semiconductor engineering already knows how to work this way. Perhaps the path to trusting AI is not to abandon established engineering discipline. It is to apply that discipline directly to AI-generated design.

• Define the workload
• Define the benchmark
• Model the response
• Predict
• Verify
• Measure the error
• Compare
• Repeat

Then ask the question that matters: Did the AI actually beat the benchmark—and can the engineering data prove it?

Dr. Moh Kolbehdari is senior director of IC/packaging at Socionext US.

Related Content

• The AI design world in 2026: What you need to know
• Four tie-ups uncover the emerging AI chip design models
• Applied Materials Bets $5B on a New Model for Chip Innovation
• How AI is reshaping IC signoff: Trust, speed, and intelligent workflows
• The Magic of Agentic AI Will Come From a Holistic Approach to Chip Design

The post AI silicon tapeout: Can it beat a benchmark engineers trust? appeared first on EDN.

They look like simple, passive lumps of material molded onto a cable or dropped onto a PCB but looks can be highly deceiving. To the uninitiated, a ferrite bead is just a mysterious black cylinder taking up space on a wire. But underneath that boring exterior lies an engineer’s secret weapon for turning pesky high-frequency noise into harmless heat.

To understand a ferrite bead, you have to look past the standard inductor symbol often used for it on a schematic. At low frequencies, a ferrite bead does behave like a garden-variety inductor, offering low DCR (DC resistance) and letting your desired signals pass right through.

But as the frequency climbs into the megahertz range, the magic happens. The bead’s inductive reactance (XL) takes a backseat to its resistive component (R). Instead of reflecting high-frequency noise back into your circuit like a pure inductor would—which can cause unwanted resonance and ringing—the ferrite bead acts like a frequency-dependent sponge, trapping that electromagnetic interference (EMI) and dissipating it as a tiny amount of thermal energy.

To see why this shift happens, it helps to look at the bead’s equivalent circuit.

The core physics: How they actually work

To understand ferrite beads, it helps to look at how they are modeled in a circuit. A bead isn’t just a simple inductor (L). Instead, it is best modeled as an inductor (L) and a lossy resistor (R) in series, both in parallel with a parasitic capacitor (Cp). This combination explains why their behavior transforms so dramatically as frequency changes.

At low frequencies, the inductive element dominates. The bead behaves like a small coil, storing energy in its magnetic field and reflecting disturbances back toward the source. In this regime, signals pass through almost unaffected, while the bead quietly resists sudden changes.

As the frequency rises, however, the bead’s resistive component takes over. Instead of bouncing noise back into the circuit, the bead begins to absorb it. High‑frequency EMI is converted into tiny amounts of heat inside the ferrite material. This lossy behavior is what makes beads so effective at cleaning up noisy power rails and suppressing RF interference.

The parasitic capacitor adds another wrinkle: at very high frequencies, it can provide a bypass path, limiting the bead’s effectiveness. That’s why datasheets often show impedance curves that peak and then roll off.

Mathematically, the bead’s impedance is expressed as Z = R + jX, where X is the reactance (from inductance or capacitance). At low frequencies, X dominates. At high frequencies, R becomes the star of the show, ensuring that unwanted signals aren’t reflected but instead dissipated.

This dual nature—reactive at low frequencies, resistive at high—makes ferrite beads uniquely suited to tame the invisible chaos of EMI.

Figure 1 A mixed-signal IC filtering scheme attenuates digital supply noise from sensitive analog power domains. Source: Analog Devices Inc.

Note at this point that ferrite beads come in several distinct forms tailored to different circuit needs: multilayer chip beads use internal printed traces for compact surface-mount filtering; wirewound beads coil insulate copper wire around a core to handle higher DC currents with minimal power loss; leaded through-hole beads offer sturdy mounting for traditional power electronics; and snap-on cable cores (chokes) clamp around external cables to stop them from acting as RF antennas. Regardless of their physical design, all these types share the same core function—absorbing high-frequency EMI and dissipating it harmlessly as heat.

Strip away the form factors—whether it’s a tiny chip bead soldered to a modern PCB, a leaded through-hole bead in a power circuit, or a snap-on choke on a laptop cord, all ferrite beads do the same job. They act as “high-frequency sponges” that absorb unwanted EMI and turn it into heat. On circuit boards, chip beads clean up power lines right at the source, while on external cables, ferrite cores keep long wires from becoming broadcast antennas that violate regulatory limits.

Ferrite bead vs. standard inductor

While inductors and ferrite beads may look alike, their roles in a circuit are fundamentally different. A standard inductor is designed to store energy in its magnetic field, with a high Q factor that minimizes losses and allows it to resonate cleanly with capacitors. Its purpose is precision—shaping signals and conserving energy.

A ferrite bead, on the other hand, is intentionally engineered to be lossy. Its resistive element rises sharply at targeted high frequencies, ensuring that instead of ringing with noise, it absorbs and dissipates it as heat. In effect, inductors are tools for energy conservation and resonance, while ferrite beads are noise suppressors, sacrificing efficiency at high frequencies to protect circuits from EMI.

This purposeful lossy behavior is why beads are so common on USB cables, power rails, and RF lines, where stability and quiet operation matter more than resonance.

The trap: Current saturation and DC bias

Here’s where ferrite beads reveal a hidden weakness that many beginners overlook: DC current ruins their effectiveness. The culprit is magnetic saturation. As a steady DC current flows through the bead, the ferrite core material begins to saturate. In this state, the core can no longer respond linearly to changes in magnetic flux, and its effective permeability drops sharply.

The consequence is dramatic. Impedance, which is the bead’s measure of resistance to unwanted high‑frequency signals, collapses. A bead that proudly advertises 600 Ω of impedance at a given frequency might deliver only 50 Ω if you push it near its maximum rated DC current. Instead of choking off noise, it becomes nearly transparent, letting interference slip through unchecked.

Figure 2 Key performance specifications—including impedance, rated current, and operating temperature—are shown from a leaded ferrite bead datasheet. Source: Author

This is why datasheets specify a maximum DC bias current: it’s not just a thermal limit, but a functional one. Exceeding it means the bead stops being a noise filter and starts behaving like a weak wire. For engineers, the lesson is clear—always size ferrite beads with headroom for DC current. Otherwise, your carefully chosen EMI suppression component may silently fail, leaving your design vulnerable to the very noise it was meant to kill.

How to read a ferrite bead datasheet

A ferrite bead’s datasheet is more than a list of part numbers—it’s a roadmap to understanding how the bead will behave in your circuit. The most important plot is the impedance vs. frequency curve. At low frequencies, the curve is dominated by reactance (X), showing the bead’s inductive nature.

As frequency rises, the resistive component (R) overtakes X, and the curve peaks—this crossover frequency marks the point where the bead stops reflecting noise and starts absorbing it. That peak is the sweet spot for EMI suppression.

Figure 3 These impedance-frequency characteristics of a surface-mount ferrite bead are adapted from the manufacturer datasheet. Source: Micros

As you can see the plot displays X (reactance) dominating at lower frequencies (~10–30 MHz) and dropping near 100 MHz, while R (resistance) rises to equal/exceed X and dominates the total impedance Z around 100 MHz.

Another critical parameter is the DC resistance or DCR. While often overlooked, DCR tells you how much voltage drop the bead will introduce on a power rail. A bead with high impedance but excessive DCR can starve sensitive circuits of voltage.

The trick is to balance; choose a bead with a strong impedance peak at your noise frequency, but low enough DCR to keep your power rails stable. Reading datasheets this way ensures you’re not just picking a bead; you’re engineering a reliable noise filter.

Material matters: Curie temperature and resistivity

Ferrite beads are not only defined by their geometry but also by the ferrite material itself, and two parameters—Curie temperature and resistivity—play a decisive role in bead choice. The Curie temperature marks the point at which the ferrite loses its magnetic properties; MnZn ferrites typically sit around 200–300 °C, while NiZn variants can reach 350 °C or higher, meaning that operation near this limit causes permeability to collapse and impedance to vanish.

Resistivity differences further shape performance: MnZn ferrites, with relatively low resistivity in the 10–100 Ω·cm range, are well suited to suppressing lower-frequency noise below about 1 MHz but suffer eddy current losses at higher frequencies. Whereas NiZn ferrites, with resistivity in the 103–106 Ω·cm range, excel in the 10–100 MHz band and beyond, making them the preferred choice for RF and high‑speed digital suppression.

The design lesson is clear—match bead material to the noise spectrum and respect the Curie limit, because thermal stress or the wrong resistivity profile can silently erase EMI suppression.

Practical applications and best practices

Ferrite beads earn their keep in real-world designs by strategically blocking noise where it matters most. They are commonly placed in power supply filtering, forming part of LC rails to keep voltage lines clean. They also shine in decoupling pi-filters, where they help isolate noisy digital blocks from sensitive analog domains—such as keeping a microcontroller’s chatter away from an ADC’s quiet input stage.

But placement requires caution. A classic pitfall is dropping a ferrite bead directly next to a ceramic decoupling capacitor. Together, they can form an unintended LC tank circuit that resonates at certain frequencies. Instead of suppressing noise, this setup can actually amplify it, creating spikes that defeat the bead’s purpose.

The best practice is to space beads thoughtfully, use them in conjunction with resistive damping when necessary; to fix this, engineers often damp the circuit by adding a small series resistor or using a high-ESR electrolytic/tantalum capacitor in parallel with the ceramic capacitor. And always check impedance curves to ensure they’re working in your target frequency band. In short, ferrite beads are powerful tools, but only when applied with care.

Beads of truth: What textbooks miss

Ferrite beads may look like humble black cylinders or chips, but they embody a subtle engineering truth: they’re not inductors, they’re intentional noise killers. What they don’t teach you in school is that their effectiveness hinges on details often buried in datasheets—DC bias limits, impedance crossover points, and placement pitfalls that can turn a filter into a noise amplifier. Mastering ferrite beads means thinking beyond the schematic symbol and into the physics of saturation, loss, and frequency response.

So, the next time you spot that “mystery cylinder” on a USB cable or a bead on a power rail, remember it’s not there to store energy; it’s there to sacrifice it, converting interference into harmless heat. As an engineer, your job is to wield that sacrifice wisely. Read the curves, respect the ratings, and place beads with intent. Do that, and you’ll transform a quiet component into a powerful ally against EMI.

Now take a fresh look at your current designs. Pull up a ferrite bead datasheet, trace your power rails, and ask yourself: are your beads truly suppressing noise, or just sitting there as decoration? The answer could be the difference between a flaky prototype and a rock‑solid product.

T. K. Hareendran is a self-taught electronics enthusiast with a strong passion for innovative circuit design and hands-on technology. He develops both experimental and practical electronic projects, documenting and sharing his work to support fellow tinkerers and learners. Beyond the workbench, he dedicates time to technical writing and hardware evaluations to contribute meaningfully to the maker community.

Related Content

• Box Level EMI Suppression
• All about surface-mount ferrites
• Active noise control: Engineering silence in audio systems
• Power Tip 69: A Simple Oversight Can Ruin EMI Performance
• Key parameters to consider when selecting drum core power inductors

The post The secret life of ferrite bead: More than just a lump on a wire appeared first on EDN.

🏋️‍♂️Спартакіада 2026-2027 навчального року kpi пн, 10/12/2026 - 17:21

VolAnti is an open source acoustic drone detector: it listens to the sound of the propellers instead of the radio signal. That is why it also works against fibre-optic FPV drones, which emit nothing and stay invisible to any receiver. The project is by Agam Rossen and it only detects and alerts, with no jamming, interception or countermeasures.

The heart is an ESP32-S3. Four ICS-43434 MEMS microphones are arranged in a cross, 79 mm from corner to corner, and synchronised from a single source. The four streams are summed: at these frequencies 79 mm is a tenth of a wavelength, so sound from any direction adds up in phase while each capsule’s own noise does not. The gain is about 6 dB of signal-to-noise ratio for free, with a nearly omnidirectional response.

The spectrum is computed with a 2048-point FFT every 512 samples at 16 kHz, that is one window every 32 ms. The detector keeps a running picture of what the site normally sounds like at every frequency and subtracts it. Quiet things are learned in about 6 s, loud broadband bursts in less than a second.

The harmonic comb of the propellers and the six consecutive windows

A propeller with B blades at R revolutions per second generates a harmonic comb with evenly spaced peaks and silent valleys. For every candidate speed from 70 to 2000 Hz the firmware sums the energy on the teeth of the comb, subtracts that in the valleys, normalises and keeps the best score. On top of that the same speed has to win six consecutive windows within 2%: a single high-scoring frame means nothing, noise does not behave like that, a rotor does.

Four independent detectors work on the same spectrum and the alarm is whichever one is sure first. The measured latencies vary a lot from one to another:

• detector 1, fast comb: 0.23 s latency
• detector 2, slow comb: 1.4 to 4 s latency
• detector 3, envelope wash: 1 to 3 s latency
• detector 4, no-floor comb: 5 to 15 s latency

On 6 September 2026 tier 4 triggered the alarm at 104.2 m, 114 yards on the map. On 21 August, on open ground with variable wind, detection was at 14 m with loaded propellers and no false alarm all day. On 28 August, with the first production board, the detector output was identical to the reference on the golden vectors, with a worst frame of 29.4 ms against the 32 ms budget over 1,938 frames and no overrun.

Power, e-paper screen and an 18-byte LoRa packet

Power starts from a 1S 2500 mAh LiPo, charged by the BQ24074 and regulated to 3.3 V by the TPS63020 buck-boost. The claimed runtime is 18-22 h on a single charge. The case measures 91 mm and also houses an e-paper screen. The radio is a Ra-01H module: the LoRa alarm packet is 18 bytes, so a few dozen bytes are enough to let a second VolAnti know there is something in the air.

The frequency has to be set for the country of use: 868 MHz in the UK and the EU, 915 MHz in the United States. In still air and at a quiet site you can expect 100 to 200 m. At a windy or noisy site you can expect 15 to 50 m, and above 8 m/s detection is assumed to be degraded. So far there have been no false alarms in the field sessions.

Rebuilding it takes very little. The breadboard build costs about £35-45 and an evening, while the complete unit costs about £50-80 and a weekend. In Agam Rossen’s repository you will find the firmware, the live simulator, the breadboard guide, the complete unit guide, the flashing instructions, running multiple units, the audio test and the website source.

Assembly needs no exotic tools: soldering, a bit of patience and the willingness to tune the detector to your own site. A school or a farm can build and repair it themselves, without depending on a supplier. For anyone who wants to start from a development board, the ESP32-C6-Zero IoT kit is an option for practising with Wi-Fi 6 and built-in peripherals, while a round ESP32-S3 HMI display with a touch knob and LVGL graphics can serve as the control interface in a more ambitious version.

Source: https://github.com/agamrossen/VolAnti

The post VolAnti: the open source acoustic drone detector that listens to propellers appeared first on Open Electronics.

A seemingly newer device reverts to a legacy processor architecture, in comparison to one certified earlier that same year. Does it matter? And was it due to Matter?

This is the end
Beautiful friend
This is the end
My only friend, the end
The Doors, “The End”

In quoting those epic song lyric opening lines, I’m not referencing an ex-girlfriend, as Jim Morrison had reportedly done, but instead applying them to my long-running TP-Link smart plug teardown series. This entry, for the Tapo P110M, marks the end of the publication line (at least as currently planned) for this specific content cadence.

I hope you enjoyed reading about the various devices as much as I enjoyed taking them apart, photographing them, and writing about them.

The series, up to this point, began in February and encompasses the following analyses:

• TP-Link’s Kasa HS103: A smart plug with solid network connectivity
• TP-Link’s Kasa EP10: If at first it doesn’t connect, buy, buy again
• TP-Link’s Kasa EP25: Energy monitoring for a hoped-for utility bill nose-dive
• TP-Link’s Tapo P105: A Kasa EP10 clone, or evolutionarily derived?
• TP-Link’s Tapo P125: A smart plug with an Apple HomeKit vibe
• TP-Link’s Tapo P115: Smart plug subtracts Apple, adds energy tracking

Reiterating a frequently uttered mission-statement mantra I most recently chanted last month, my basic aspiration with this project was to ascertain to what degree (if any) differences in the company’s various smart plug products’ feature sets, broadly between the Kasa and Tapo product lines as well as between products within a given line, were due to hardware variability versus (or in addition to) software-implemented inconsistency. Last month’s unveil was a particular hardware-evolution doozy, as it involved the processor architecture (and associated codebase) conversion from Arm (Realtek) to RISC-V (Espressif Systems).

So, what will we find inside the Tapo P110M? Usually, but not always, TP-Link’s Matter smart home and IoT protocol-supportive product variants include “M” as a product name suffix. More generally, in addition to Matter cognizance (or lack thereof), we’ve seen over this past year that the manufacturer also differentiates devices based on parameters such as energy monitoring and reporting capabilities and Apple HomeKit protocol support, not to mention cosmetic variances such as size, shape and weight, switch and activity LED locations, and the like.

The P110M, for example, implements all three aforementioned software enhancements, only one of which (energy tracking) last month’s Tapo P115 shares. Let’s see how, if at all, this differentiation is also reflected in hardware.

Feature set confusion

Here’s a stock shot of the Tapo P110M, to start.

 

Looks curiously familiar, albeit not identical, doesn’t it?

My two-pack came from Amazon’s Resale (formerly Warehouse) website area and set me back $13.77 after a 30%-off promotion active at the time, plus tax. While just now revisiting the product page both there and at TP-Link’s website, I was initially confused, since the latter (not to mention TP-Link’s broader product line overview page) explicitly notates support for Apple’s Home protocol, Siri interface and the like, all absent from the former. However, I suspect Matter cognizance is at the nexus of the discrepancy, as noted at Amazon product page verbiage:

Matter-certified devices, regardless of brand, can work together and are compatible with most major smart home platforms like Amazon Alexa, Apple HomeKit, Google Home, and Samsung SmartThings. Enjoy more flexible and unified control.

Translation, I’m guessing: the Tapo P110M doesn’t support Apple services directly, but instead implicitly via their common Matter-support intermediary.

Here’s the usual suite of outer box shots, complete with the also-as-usual 0.75″ (19.1 mm) diameter U.S. penny accompaniment for size comparison purposes. Top.

Front.

Left side.

Back.

Right side.

And bottom.

Peeling away an edge of the information-obscuring Amazon Resale sticker exposes to view the hardware revision number—v1.6—of what’s inside. And in a rarity, at least from my experience, that’s the only hardware version option listed on the product support page (albeit with multiple to-date associated firmware updates). A refreshing change of pace.

Sticker shock

Let’s now see what’s inside.

One of the two Matter stickers was previously removed from its original backing sheet. Wonder where it went? Hold that thought.

I’ve usually found with returned-and-resold stuff like this that only one of the multiple items in the package has been removed prior to re-placement and shipment back to Amazon. I generally select that same one as my teardown “victim”. But which one was it in this case?

Again, it’s usually the one on the left (or upper left corner for a quad-device box). But the prior owner of this set might have been left-handed; the indent for the device on the right is frayed.

Here’s more visual evidence of the prior owner’s out-of-box device selection preference. There’s the missing sticker, now adhering to the top of the smart plug on the right.

Putting the left-side device aside, let’s continue with the usual overview photo set. Top, again.

Front.

Left side.

Back.

Right….what?

Turns out the Matter QR code and info are already stamped on the device’s right side. Turns out, too, the owner stuck the supplemental sticker on the wrong device, because the info sets don’t match. Truthfully, I don’t think the sticker’s intended for the device at all (unnecessary info redundancy, don’cha know) but if so, it instead should have been stuck on top of the other device.

Maybe owner confusion is at the core of why it ended up getting returned? Dunno. Onward.

As usual, the bottom of the device contains useful info, including the FCC ID (2BCGWBP1100).

Quick aside: the FCC ID for last month’s Tapo P115 is quite similar (2BCGWP110). That’s not confusing at all, right? Its listed “final action date” is February 29, 2024 (a leap year, obviously) while this one’s “final action date” is July 24 of that same year. Therefore the “seemingly newer device…in comparison to one certified earlier that same year” prose in the subhead.

A screw loose

One more stock shot to go: the latest in a line of company-supplied interior concept images:

And that’s enough for the setup; let’s get inside. Practice makes perfect, apparently; this time not only was no bloodshed, but no tabs were snapped, either.

Voila.

Here’s the half you’re undoubtedly all most interested in.

Device-to-device design consistency takes the form, among other things, of the relay, yet another Churod A16-V-105DA2F.

The bottom and right-side views are equally reminiscent and unmemorable.

And, last but not least, what of the digital PCB on the left? I’ll start with the boring side (unless you’re into traces, test points, and/or embedded antenna silhouettes, that is).

That’s what’s known as a tease. Here’s the side you care about, especially after last month’s reveal that it had captured and encompassed a processor architecture shift.

No such momentous luck this time, alas. We’re back to Realtek’s RTL8720CM at left, previously found on several previous TP-Link smart plug designs, along with a Shanghai Belling BL0937 single-phase energy monitoring IC and Eon Silicon’s EN25Q32B 32 Mbit serial flash memory on the right (not found with the Tapo P115, since the NVM was single-package integrated alongside the processor in that case).

And of course there’s also yet another mysterious five-lead packaged device in the lower left corner (I’m still sticking with my guess that these are dual transistor devices), this time marked “TACeE1” . Plus, we can’t forget the switch alongside an LED smack dab in the center.

Why the seeming chronological advancement but architectural back-step from RISC-V is back to Arm this time? My guess is that it has everything to do with Matter. The specification is in the rapid-evolution early phase of its technology lifecycle, and with no offense intended to Espressif Systems, Realtek is the more mature of the two suppliers in this particular product category.

Sound off with your theories and/or broader thoughts in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

• Tapo or Kasa: Which TP-Link ecosystem best suits ya?
• TP-Link’s Tapo P115: Smart plug subtracts Apple, adds energy tracking
• TP-Link’s Kasa EP10: If at first it doesn’t connect, buy, buy again
• TP-Link’s Kasa EP25: Energy monitoring for a hoped-for utility bill nose-dive

The post TP-Link’s Tapo P110M smart plug: Matter and energy monitoring matter appeared first on EDN.

​Semiconductor manufacturer onsemi, specialised in silicon carbide (SiC) power solutions, power management, and CMOS image sensors has introduced its Embedded Power Platform—a wafer-level power architecture that integrates multiple dies (silicon, SiC, and GaN) directly into a single system. This new semiconductor packaging architecture enables higher power density, lower electrical losses and easier power-system integration. This platform has the potential to develop traction inverters and power systems that are smaller and more efficient for EVs.

​onsemi announced the Embedded Power Platform on September 16, 2026, at its headquarters in Scottsdale, Arizona, USA. The architecture delivers up to 3-5 times higher power density compared to current traction inverters. It supports the integration of silicon, silicon carbide, and gallium nitride (GaN) technologies, along with field-effect transistors, drivers, and controllers.

Advance Packaging Reduces EV Power Losses

Traction Inverter design developed by onsemi replaces high-in​ductive wire bonds with precision wafer-level redistribution layers (RDLs). This method reduces inductance and performs higher switching frequency operations. It reduces heat loss and increases EV traction inverter efficiency by addressing both thermal and performance challenges simultaneously.

Subaru Corporation, a Japanese multinational automotive manufacturing company has shown interest in implementing this embedded power platform developed by onsemi in its future electrified vehicles. This technology engagements between industries allows them to explore methods that can enhance energy efficiency, reduce development complexity, and facilitate next-generation vehicle architecture.

The post onsemi Unveils Advanced Semiconductor Packaging to Improve EV Inverter Efficiency appeared first on ELE Times.

​Multilayer electrodes combine different electrode layers with varying material compositions. This approach provides multilayer coating, enabling better ion transport and mechanical stability compared to a conventional single coating layer in battery technology. While traditional electric vehicle (EV) batteries rely on single-layer coatings, implementing a multilayer coating architecture could enhance battery performance and extend its service life.

Enhancing EV Battery Performance

Researchers will examine different coating materials, layer thicknesses, and electrode structures for both anodes and cathodes. The team will then investigate coating formulation and drying conditions to understand their impact on electrode quality and manufacturing process consistency.

The project will evaluate two coating techniques, which include two-layer slot-die coating and multilayer curtain coating under Aachen’s Chair of Production Engineering of E-Mobility (PEM) to develop scalable production process. On the basis of outcome results of these two methods, the projects aim to broader the thickness of electrode from 200 micrometres to 800 micrometres. This increase in thickness of electrode coating will allow battery manufacturers to reduce the number of inactive layers (separators and current collectors) within a cell and lower the cost of production while expanding energy density.

The post RWTH Aachen Develops Scalable Manufacturing Technology for Multilayer EV Battery Electrodes appeared first on ELE Times.

​Battery technology plays a central role in describing the performance and driving range of an electric vehicle. The more advanced and efficient the battery technology, the better the overall performance of an electric vehicle will be. With advancements in battery technology over time, ProLogium, a battery developer company has officially announced its Dynamic Coordination Network (DCN) electrolyte architecture for its next-generation GEN4 battery technology.

The purpose of introducing this technology is to showcase advancement in electrolyte design, combining characteristics of liquid and solid electrolytes. The company aims to address key challenges in next-generation batteries such as charging speed, ion transport and battery performance.

DCN Electrolyte Architecture Targets Faster Charging

Electrolyte is a key factor in battery technology, determining how well the battery works, how long it lasts, and how safe it is. It enables lithium ions to move between positive and negative electrodes during charging and discharging. The physical and chemical properties of an electrolyte such ionic conductivity, viscosity, transference number, electrochemical stability window, and solid electrolyte Interphase (SEI) influence charging performance, energy efficiency and battery operation.

The role of ProLogium’s DCN architecture is the coordination of lithium ions within the electrolyte, aiming to improve ion transport and support fast charging in its next-generation battery technology.

As per the company’s report on internal test results, the battery can charge from 5% to 80% in 6.4 minutes. This figure is from the company’s end and should not be considered as independent verification of performance on a production electric vehicle. Charging time in real-life scenarios depends on many factors like battery temperature, charger capacity, cell design, and the battery management system.

The post ProLogium Unveils New Electrolyte Architecture to Advance Ultra-Fast-Charging EV Batteries appeared first on ELE Times.

Keysight Technologies, today announced the Keysight Velocity 4900 Series, a new line of cost-effective Layer 1 automation switches designed to transform and automate physical connectivity in network test labs. Through software controlled testbed configuration and management, the Velocity 4900 Series enables engineering teams to dynamically connect and automate the management of test equipment using an intuitive graphical user interface. Teams can securely access and share valuable lab resources remotely, improve equipment utilization, and create repeatable testing workflows for increasingly complex networks and infrastructure supporting AI, 6G, and next-generation services.

As the speed, scale, and complexity of next-generation network technologies and services increase, test teams face growing pressure to perform accurate, comprehensive validation and keep pace with rising traffic volumes. Yet many test labs still depend on manual cabling and time-consuming physical topology changes, leaving valuable equipment underutilized or inaccessible to remote teams. These limitations slow testing, increase the risk of configuration errors, and prevent physical lab infrastructure from integrating fully with automated development and continuous integration and continuous delivery (CI/CD) workflows. Without greater lab automation, organizations risk delays to product releases and critical network updates, with significant business and operational consequences.

The Velocity 4900 Series addresses this physical-connectivity bottleneck by replacing manual testbed configuration with software-controlled Layer 1 connectivity. Engineering teams can quickly create, save, modify, and reproduce physical test topologies while securely sharing expensive or scarce test resources with authorized users across teams and locations.

The first two models in the series are:

• Keysight Velocity 4902: A high-speed Layer 1 automation switch supporting Ethernet speeds from 100 megabits per second (Mbps) to 100 gigabits per second (Gbps). The platform includes 72 QSFP28 ports, supporting 288 connections with breakouts, providing flexible connectivity for high-speed functional and performance testing.
• Keysight Velocity 4906: A high-density Layer 1 automation switch with 288 SFP28 ports supporting Ethernet speeds from 100 Mbps to 25 Gbps. Its density enables organizations to connect and automate a larger portion of their lab inventory within a compact, fixed-form-factor platform.

Both switches provide true Layer 1 forwarding through an ultra-low-latency, fully transparent switching matrix. They support single-mode fiber, multimode fiber, direct-attach copper, and active optical cables, with port speed and media configuration available on a per-port basis. Additional capabilities include port tapping for diagnostics and monitoring and one-to-many traffic replication for broader test coverage and more efficient reuse of traffic-generation resources.

Key benefits of the Velocity 4900 Series include:

• Faster, repeatable testing: Automates physical testbed setup and teardown, allowing teams to provision complex topologies in seconds or minutes rather than relying on hours or days of manual cabling.
• Secure global resource sharing: Helps authorized engineers remotely access and share test equipment across labs, teams, and geographic locations without requiring physical cable changes or equipment movement.
• Improved equipment utilization: Enables organizations to pool scarce or expensive instruments, make underused assets available to more teams, and reduce unnecessary equipment duplication.
• Greater test coverage: Allows engineers using Velocity software to configure physical test environments, run tests, and automatically tear down and recreate those configurations in seconds, expanding test coverage while reducing manual effort and connection errors.
• Incremental lab modernization: Provides a cost-effective starting point for Layer 1 automation that can expand into resource reservation, lab orchestration, test automation, and CI/CD integration through the broader Keysight Velocity portfolio.

Anil Kollipara, Vice President and General Manager of Automated Testing and Assurance, Keysight, said: “Engineering teams developing services and infrastructure to support AI, 6G, and next-generation systems need test environments that can change as rapidly as the technologies they are creating. The Velocity 4900 Series gives organizations a practical and cost-effective way to begin modernizing the physical lab. By automating Layer 1 connectivity and making test resources easier to share, Keysight is helping customers improve utilization, expand test coverage, and accelerate development without requiring a complete lab transformation.”

The Velocity 4900 Series integrates with the broader Keysight Velocity portfolio, enabling organizations to extend software controlled physical connectivity into resource reservation, lab orchestration, test automation, and CI/CD workflows. The Keysight Velocity 4902 and 4906 are available for order immediately with initial deliveries planned for January 2027.

The post Keysight Introduces Velocity 4900 Series to Accelerate Test Lab Modernization for AI and 6G appeared first on ELE Times.

L&T Technology Services, a global leader in Engineering Intelligence Solutions and ER&D services, today inaugurated its AI-Native EI Lab for Digital Manufacturing in Bengaluru, an experiential environment where customers and partners can see AI-Native Manufacturing, digital twins and autonomous systems working together across the lifecycles.

The EI Lab extends LTTS’ Engineering Intelligence charter to the manufacturing shop floor. Through live and scenario-based demonstrations, customers can move from digital engineering and virtual validation to connected production, intelligent operations and autonomous systems, and see the integration pathways that make each of them scale.

The EI Lab is built around multiple capability pillars:

• Manufacturing Intelligence: An AI-powered Manufacturing Command Center with executive decision-intelligence, manufacturing data fabric with knowledge graph, a supply chain control tower supported by AI-powered production planning and multi-plant benchmarking.
• AI-Native Factory: Here intelligent machines, robots, cobots, drones, autonomous systems and digital twins work together to execute manufacturing tasks with minimal human intervention. This layer has an NVIDIA accelerated environment combining NVIDIA Omniverse, NVIDIA Isaac Sim, NVIDIA PhysX, NVIDIA Cosmos, NVIDIA NeMo, and OpenUSD-based digital twin workflows, accelerated visualization and technologies for Industrial and Physical AI.
• Operations AI & Autonomy: A verification gate that checks actions generated by agent swarms before they reach a machine, enabling verifiable, governed execution and safer autonomous decision-making across connected manufacturing environments. This layer encompasses factory design & simulation, production, process & quality control, maintenance and sustainability.
• LTTS’ Unified Intelligence platform: EIOne, the Engineering Intelligence platform that brings together 100+ EI solutions and agentic AI swarms into a single, governed ecosystem. It empowers enterprises to rapidly build, deploy, orchestrate, and scale AI-driven engineering & manufacturing workflows while ensuring enterprise-grade security, governance, and operational control.

“AI is transforming how manufacturers design, simulate and operate the factories of the future,” said Vishal Dhupar, Managing Director for South Asia at NVIDIA. “The EI Lab, combining NVIDIA technologies spanning hardware, software and world models and LTTS’ deep engineering expertise, gives manufacturers a practical environment to explore and validate AI-driven, simulation-first approaches to industrial transformation.”

“The EI Lab for Manufacturing brings Engineering Intelligence into a tangible manufacturing environment, allowing customers to experience how engineering, AI and physical systems can come together to address real-world challenges. Our collaboration with NVIDIA adds advanced simulation and accelerated computing capabilities to this environment, while our engineering & manufacturing expertise helps translate these technologies into practical manufacturing solutions for our global customers,” said Amit Chadha, CEO & Managing Director, L&T Technology Services and NASSCOM Executive Council Member.

The post L&T Technology Services Launches EI Lab for Manufacturing and Operations, Featuring NVIDIA Accelerated AI-Native Factory appeared first on ELE Times.

The TP4056 module with protection charges single-cell 3.7 V Li-Ion and Li-Po batteries. It also protects them from overcharge, deep discharge and short circuit. Compared with the basic version it adds the DW01A chip. AdriRobot describes its schematic, the charge current and a few practical hookups. We already covered the version without protection in Li-Ion Charger with the TP4056 Module.

The variants of the TP4056 module

Several boards are built around the TP4056. The one without protection only handles charging. The one with protection, the subject of this article, adds the DW01A and a dual MOSFET. That way it shields the battery from overcharge, deep discharge and short circuit.

There are also versions with an MT3608 step-up converter, adjustable from 4 to 28 V. The J5019, also called HW-357, does not protect the battery. The LX-LCBST, on the other hand, also has an HM5434 protection chip.

How the TP4056 module works

The TP4056 uses the CC/CV algorithm, constant current and constant voltage, typical of lithium-ion batteries. Charging happens in three phases. First, below about 2.9 V, it applies a reduced current (trickle charge) to bring the cell back to a safe level. Then it delivers the set current, up to 1 A. Finally, when the battery reaches 4.2 V, it holds the voltage and gradually reduces the current until charging ends.

The module is preset to 1 A, suitable for cells such as the 18650. The input is Micro USB or USB Type-C at 5 V. Two LEDs also show the status: red while charging, blue or green when charging is complete. The dimensions are 22 × 17.3 × 3.6 mm, the weight 2 g.

• input: 4.5 to 5.5 V;
• charge current: up to 1000 mA, adjustable with a resistor;
• end-of-charge voltage: 4.2 V with 1% tolerance;
• protections: overcharge at 4.3 V, deep discharge at 2.4 V, overcurrent at 150 mV;
• operating temperature: -10 to +85 °C.

The schematic: TP4056, DW01A and FS8205A

In the charging section the TP4056 is a linear controller for single cells. Resistor R3, 1.2 kΩ, sets the current to about 1 A. Two LEDs with 1 kΩ resistors indicate charging and end of charge, while a 0.1 µF capacitor stabilises the chip. Protection is handled by the DW01A, which monitors the cell, and by the FS8205A, a dual MOSFET. When the DW01A detects an abnormal condition, it turns off the MOSFETs and isolates the load.

There are three pairs of terminals. IN+ and IN- take the 5 V, as an alternative to the USB connector. B+ and B- go to the battery, while OUT+ and OUT- power the load. The load must be connected to OUT+ and OUT-, not directly to the battery, otherwise the protections will not kick in.

Setting the charge current

The current depends on resistor Rprog on pin 2 of the TP4056. The formula is I = Vprog / Rprog × 1200, with Vprog equal to 1 V. With 1.2 kΩ you get 1 A. With 2 kΩ it drops to about 580 mA and with 3 kΩ to 400 mA. With 5 kΩ the current is 250 mA, with 10 kΩ it is 130 mA. For a small battery, for example 500 mAh, it is better to raise Rprog: the current falls and damage is avoided.

Practical hookups and use with Arduino

In the basic hookup the battery goes to B+ and B-. The 5 V comes in from USB or from IN+ and IN-. Also, only one battery is charged at a time, respecting the polarity. At 1 A the chip can get hot, so it is better to mount it in a ventilated spot. While charging, powering a heavy load such as a motor is not recommended. The module might in fact fail to recognise the end of charge.

For a 3.3 V microcontroller, the OUT+ and OUT- output feeds a CN3903 DC/DC converter. The converter keeps the voltage stable even when the battery drops from 4.2 to 3.0 V. The solution is intended for ESP8266, ESP32-C3, STM32 and IoT sensors. For higher voltages the same output can feed an MT3608 step-up, adjustable from 5 to 28 V. It is useful for custom power banks and portable instruments. In both cases the converter must be connected to OUT+ and OUT-.

With an Arduino UNO you read the charge status from pins CHRG (7) and STDBY (6) of the TP4056. A low level indicates charging in progress and charge complete respectively. With a network-connected board such as an ESP32-C3, the battery can also be monitored remotely.

If the battery does not charge, check the voltage on VCC, which must be between 4.0 and 8.0 V. Then check the value of Rprog and the connection to the BAT and GND pins. If instead the chip gets hot, reduce the current or improve the heat dissipation.

There is the 1A charging module for lithium battery, Type-C, with protection and USB Type-C input.

Source: the original article by AdriRobot also includes the sketch for Arduino UNO and the TP4056 pin table.

Related products

• 1A charging module for lithium battery – TYPE-C

The post TP4056 Module with Protection: Li-Ion and Li-Po Charger appeared first on Open Electronics.