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🧐 Запрошуємо на методичний семінар “Перевірка робіт в епоху ШІ” kpi вт, 05/19/2026 - 16:33

КПІшники на благодійному марафоні MHP Run4Victory kpi вт, 05/19/2026 - 16:24

There is a growing architectural tension at the heart of modern AI infrastructure. The processors that enabled the deep learning revolution—graphics processing units (GPUs)—remain the dominant engines of large-scale training and inference. Yet the computational profile of frontier language models is evolving in ways that increasingly expose the structural assumptions embedded in GPU design.

Memory wall undermining GPU efficiency in large language models

A profound bottleneck lies on the memory wall, the growing performance gap where processors can execute arithmetic operations far faster than memory systems can supply data, causing increasingly powerful compute units to sit idle while waiting on bandwidth- and latency-limited data movement.

Using the Nvidia H100 as a reference point, modern GPUs deliver multiple petaflops of FP8 tensor throughput and several terabytes per second of high-bandwidth memory access. On paper, arithmetic capacity is immense. In practice, trillion-parameter-class large language models (LLMs) are frequently memory-bound. Arithmetic intensity during inference can fall below 10 FLOPs per byte, which means that performance is limited less by compute units and more by how quickly parameters can be fetched and activations moved.

Energy considerations reinforce this imbalance. A floating-point multiply-accumulate is inexpensive relative to a high bandwidth memory (HBM) access, and cross-chip communication can cost orders of magnitude more energy than local arithmetic. See Table 1.

Table 1 Here is a comparison among capacity, energy consumption, bandwidth and latency in a typical memory hierarchy. Source: Author

As model size grows, an increasing share of system energy is spent moving data rather than computing on it. The arithmetic units stall while waiting for weight tensors to arrive, and effective throughput becomes a function of bandwidth and latency rather than raw FLOPS. The challenge compounds when models exceed single-device memory capacity and must be distributed across multiple accelerators.

Frontier LLMs challenging foundations of GPU architecture

The historical success of GPUs in machine learning emerged from an unusually strong alignment between hardware structure and model behavior. Modern GPUs from companies such as Nvidia and AMD are fundamentally throughput-oriented processors built around the single instruction multiple threads (SIMT) execution model.

Groups of threads—warps on Nvidia architectures, wavefronts on AMD architectures—execute instructions in lockstep. Maximum efficiency is achieved when threads follow identical execution paths, access memory in predictable patterns, and sustain dense arithmetic workloads with minimal synchronization overhead.

This design originated in graphics rendering, where millions of pixels or vertices undergo nearly identical operations in parallel. The same architectural assumptions proved highly effective for early deep learning systems, particularly convolutional neural networks and dense transformers. Large matrix multiplications, regular tensor shapes, and high arithmetic intensity mapped naturally onto GPU tensor cores and wide vectorized execution pipelines. Under sufficiently large batch sizes, GPUs can sustain exceptionally high utilization because computation dominates memory latency and control-flow overhead.

Frontier LLMs, however, are evolving away from the dense and homogeneous workloads that originally favored GPU architectures.

Modern LLM systems increasingly incorporate conditional computation: Mixture of experts (MoE) layers, dynamic token routing, retrieval augmentation, speculative decoding, adaptive context management, variable sequence lengths, and sparsity-aware attention mechanisms. These techniques improve scaling efficiency at the model level by reducing the amount of computation performed per token while preserving or increasing representational capacity. They also introduce irregularity into execution patterns, precisely the condition under which SIMT architectures become less efficient.

The key issue is not simply “warp divergence” in the narrow classical GPU sense where threads within a warp follow different branches of a control-flow statement. In many MoE implementations, tokens routed to different experts are regrouped before execution specifically to minimize intra-warp divergence.

The deeper architectural tension is broader: SIMT processors are optimized for spatially and temporally coherent workloads, while modern frontier inference increasingly behave like sparse, dynamically scheduled computation with uneven work distribution and heavy communication dependencies.

In dense transformers, nearly every parameter participates in every token evaluation. Computational intensity remains high, tensor dimensions are regular, and work scheduling is relatively predictable. In sparse MoE systems, by contrast, only a small subset of experts may activate for a given token. A model with 16 experts and top-2 routing, for example, activates only a fraction of total parameters at each inference step. Although this dramatically improves parameter efficiency from a modeling perspective, it also fragments execution into uneven and dynamically changing workloads.

The consequence is reduced effective hardware utilization, not necessarily because every warp is internally diverging, but because the overall system struggles to maintain uniform occupancy, balanced scheduling, and continuous tensor-core saturation. Some experts become overloaded while others sit idle.

Token batches routed to a given expert may be too small to fully utilize matrix engines efficiently. Memory access patterns become less regular. Kernel launch granularity deteriorates. Synchronization overhead increases. The result is that the theoretical arithmetic throughput of the GPU becomes increasingly difficult to translate into sustained application-level throughput.

Furthermore, interactive AI workflows, especially AI agents that respond step by step, are difficult for GPUs to run efficiently. GPUs work best when they can process very large batches of data at once. In LLMs, this usually means combining many user requests together into large matrix operations. Large matrix operations are efficient because they involve much more computation than data movement, keeping the GPU fully occupied.

But interactive systems need low latency: the model must respond immediately instead of waiting to accumulate a large batch of requests. That means the batch size stays small. Small batches create smaller matrix operations that are less efficient on GPUs. The GPU spends more time moving data around and less time doing computation. As a result, GPU utilization drops. So, there is a trade-off. Large batches lead to high GPU efficiency but higher latency. Conversely, small batches cause low latency but worse GPU efficiency.

Agentic workflows usually prioritize responsiveness, which is why they are harder to run efficiently on GPUs.

The resulting inefficiencies are often obscured by headline FLOP metrics. Modern accelerators advertise enormous peak throughput numbers, but peak throughput reflects idealized dense execution under carefully tuned conditions. Real-world frontier inference frequently operates far from these conditions.

Effective utilization may decline substantially when workloads become routing-heavy, communication-bound, latency-sensitive, or dynamically imbalanced. In practice, the limiting resource increasingly shifts from raw arithmetic capability to orchestration efficiency across memory systems, interconnects, and distributed scheduling layers.

The hidden GPU complexity tax

Alongside these architectural mismatches lies another challenge: the growing software and optimization burden required to extract acceptable performance from GPU systems.

GPUs do not automatically deliver near-peak efficiency. High performance requires extensive manual optimization across multiple abstraction layers. Developers must orchestrate host-device memory transfers, optimize tensor layouts, tune kernel launch parameters, manage register pressure, balance shared-memory usage, fuse operations to reduce synchronization overhead, and carefully align workloads with hardware-specific execution characteristics. Small deviations in tensor dimensions, sequence lengths, routing distributions, or batch composition can materially reduce throughput.

As models become more dynamic, optimization itself becomes more fragile. Kernels tuned for one generation of hardware may perform poorly on another. Code paths optimized for dense transformers may degrade under sparse routing conditions. Performance engineering increasingly depends on vendor-specific toolchains such as CUDA, custom compiler stacks, graph schedulers, and specialized communication libraries tightly coupled to a particular hardware ecosystem.

The cumulative effect is a growing “complexity tax” surrounding GPU-centric AI infrastructure. The cost is not merely electrical power or silicon area, but engineering specialization, portability constraints, software maintenance overhead, and system fragility. As frontier models continue shifting toward sparse, distributed, and conditionally executed architectures, the tension between SIMT-oriented hardware assumptions and emerging AI workloads is becoming increasingly difficult to ignore.

Alternative AI processing architectures are mandatory

These pressures have catalyzed interest in alternative accelerator architectures designed explicitly around transformer workloads and data movement efficiency. Systems such as the TPUs developed by Google emphasize systolic arrays and compiler-driven dataflow scheduling to improve determinism and reduce divergence overhead.

Cerebras Systems has pursued wafer-scale integration, placing tens of gigabytes of SRAM directly on-chip in its wafer-scale engine to minimize off-chip memory traffic and reduce partitioning complexity. Graphcore designed its intelligence processing unit (IPU) around fine-grained parallelism and distributed local memory, explicitly targeting irregular and sparse workloads.

Drawing on more than two decades of architectural expertise and 14 silicon tape outs, VSORA developed an approach replacing the SIMT computational model with a dataflow architecture specifically engineered to overcome the memory wall. At its core is a massive flat register file spanning several megabytes, designed to supply data directly to large arrays of compute engines organized into wide, deeply pipelined execution paths.

Anticipating the evolving requirements of edge inference and future AI algorithms such as those for autonomous driving (AD L3-L5) applications, it also designed and embedded highly programmable processing cores capable of executing an extensive library of DSP operations with low latency and high efficiency.

While each approach involves trade-offs and varying degrees of ecosystem maturity, they share a common premise: future AI workloads are constrained less by arithmetic throughput and more by data orchestration, locality, and communication efficiency.

The next compute frontier

The broader trend in AI systems reflects a shift in the dominant bottleneck. During the convolutional era, compute capacity measured in TFLOPS was the primary metric. Early transformer models balanced compute and memory bandwidth. Frontier LLMs at trillion-parameter scale are now constrained primarily by memory movement and interconnect efficiency. As sparsity and conditional activation become central architectural features, the efficiency of routing and dataflow scheduling begins to outweigh peak arithmetic density.

GPUs remain foundational to AI infrastructure, particularly in training. Their ecosystem maturity, programmability, and unmatched dense training throughput ensure continued relevance, particularly during large-scale pretraining where arithmetic intensity remains high and workloads are relatively regular. However, as models grow more conditional, more distributed, and more memory-bound, the architectural friction becomes increasingly visible.

The future of AI acceleration will likely reward designs that privilege data locality, minimize cross-device communication, and execute sparse patterns natively rather than emulating them within a dense SIMT framework.

The decisive question for next-generation systems is no longer how many floating-point operations per second can be delivered in isolation. It is how efficiently data can be moved, routed, and scheduled across increasingly complex and sparsely activated models.

Lauro Rizzatti is a business development executive with VSORA, a technology company offering silicon semiconductor solutions that redefine performance. He is a noted chip design verification consultant and industry expert on hardware emulation.

Related Content

• Strategies to Dominate the AI Accelerator Market
• A closer look at LLM’s hyper growth and AI parameter explosion
• The role of AI processor architecture in power consumption efficiency
• AI GPU computing delivers data-center performance on the factory floor
• The truth about AI inference costs: Why cost-per-token isn’t what it seems

The post GPUs: A high-throughput architecture confronting a workload shift appeared first on EDN.

Ground-referenced loads are common in industry. This circuit implements current loop conversions for them.

Recently, there have been several published Design Ideas on converting 0/20mA to 4/20mA current and 4/20mA to 0/20mA current as full-circle current loop conversions. However, these circuits have all focused on floating loads. It’s common to also come across loads that are ground-referenced. The circuit in Figure 1 addresses this alternative requirement, converting 4/20mA current to 0/20mA current for feeding grounded loads.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Figure 1 In this 4/20mA to 0/20mA converter for grounded loads, R4 and RB can be replaced by multi-turn potentiometers for tuning purposes.

How does it work? Input current of 4-20mA feeds into R1 and is converted into 0.4V – 2.0V, which is buffered by U2A. U1 generates a reference current of 1mA which is is fed into R4, and which converts it to 0.4V. This converted current is buffered by U2B. U2C subtracts the two voltages.

Next, let’s look at the positive input of U2D. There are two currents:

• One current going through Ra=
• Another current going through Rb= –

Since the negative input of U2D is grounded, these two currents must be same:

= where I ref*R4 is 0.4V

Iout =

Select the values of Rb and Rc such that Rb/Rc =124. Substituting the values of Ra, Rb, Rc and R1 from Figure 1:

Iout =

Hence, Iout= (Iinput-4 mA)*1.25. For example, if the I input is 20 mA, I out= (20-4)*1.25=20mA. And if the I input is 4mA, I out= (4 – 4) * 1.25=0mA.

How do you tune the circuit? Implement R4 and Rb as multi-turn potentiometers. R1 conversely should be a precision 100 ohm resistor. Adjust R4 such that voltage across it is 0.4 V. Feed 20mA current from the precision current source as the Iinput and adjust Rb to get 20mA as Iout. Repeat this exercise by feeding the circuit with 4mA and 12mA.

Simulation test results follow:

Iinput (mA)	4.0	6.0	8.0	10.0	12.0	14.0	16.0	18.0	20.0
Iout (mA)	0.44	2.56	5.06	7.56	10.1	12.6	15.1	17.6	20.1
Calculated Iout (mA)	0	2.5	5.0	7.5	10.0	12.5	15.0	17.5	20.0
Error (%)	2.2	0.3	0.3	0.3	0.5	0.5	0.5	0.5	0.5

These results suggest that the circuit delivers high accuracy, with error no higher than 0.5%, except with a 4mA input. The error and associated accuracy can be improved by selecting high-end operational amplifiers such as instrumentation amplifiers with negligible offset and a high common-mode rejection ratio (CMRR).

Q2 prevents the output current from exceeding a few mA above the 20mA input threshold, as a safety measure. R5, R6, and R7 should be identical in value. And also implement R8 as a multi-turn potentiometer. The resultant tuning capability helps to reduce the output to near-zero for a 4mA input.

Jayapal Ramalingam has over three decades of experience in designing electronics systems for power & process industries and is presently a freelance automation consultant.

Related Content

• Linearly variable two-wire loop current generator
• Full circle current loops: 4mA-20mA to 0mA-20mA
• Another silly simple precision 0/20mA to 4/20mA converter
• Silly simple precision 0/20mA to 4/20mA converter
• Combine two TL431 regulators to make versatile current mirror
• A 0-20mA source current  to 4-20mA loop current converter

The post 4/20mA to 0/20mA loop current converter for grounded loads appeared first on EDN.

Конференція ПТ-2026 про сучасний стан і тенденції розвитку телекомунікаційної галузі kpi вт, 05/19/2026 - 15:00

Обговорення розвитку української науки, її досягненням, викликам і перспективам kpi вт, 05/19/2026 - 13:41

The initiative that helps defense organizations to modernize EW test and simulation with greater speed, flexibility, and minimal risk.

Today, Keysight Technologies Inc. announces a strategic collaboration with SRC UK Limited to support EW customers globally in modernizing their test and simulation environments. The initiative will help accelerate the adoption of Keysight’s EWASP, enabling customers to transition to open, scalable, and software-defined architectures with greater efficiency and minimal operational risk. The collaboration also enables customers to preserve and integrate existing threat libraries and test assets into modern, open architectures, enabling continuity while accelerating modernization.

As EW systems grow increasingly complex, defense organizations are seeking more flexible and high-fidelity test environments to validate performance, shorten development timelines, and ensure mission readiness. Through this collaboration, Keysight and SRC will align their respective strengths in EW simulation, systems integration, and local engineering support to address customer needs across global markets.

The effort centers on supporting customers across key areas, including engineering and integration services, training, and knowledge transfer. By combining Keysight’s expertise in EWASP architecture and scenario generation with SRC UK’s in-country engineering and support, customers gain faster deployment, improved access to expertise, and stronger operational readiness. This approach enables more accurate and repeatable validation of EW systems, and the collaboration helps deliver reliable, high-performance capabilities for increasingly complex electromagnetic environments.

Steve Davies, Managing Director at SRC UK, said: “Collaborating with Keysight allows us to bring advanced EW simulation capabilities closer to UK customers. By combining our proven EW, IMD, Mission Data, and engineering expertise with Keysight’s EWASP platform, we can help organizations optimize their test environments while maintaining alignment with evolving mission requirements.”

Eric Taylor, Vice President, Aerospace, Defense and Government Solutions at Keysight, said: “This effort reflects Keysight’s commitment to supporting our customers across the globe as they modernize EW capabilities. Together with SRC, we are expanding access to scalable, high-fidelity simulation and test solutions that reduce risk, improve efficiency, and accelerate mission readiness across the EW development lifecycle.”

Keysight will also discuss its further EW modernization at the upcoming AOC Europe event.

Resources

• EWASP: Advancing EW Test and Measurement
• EWASP Solution Catalog
• EWASP Solution Brief

About Keysight Technologies

At Keysight, we inspire and empower innovators to bring world-changing technologies to life. As an S&P 500 company, we’re delivering market-leading design, emulation, and test solutions to help engineers develop and deploy faster, with less risk, throughout the entire product life cycle. We’re a global innovation partner enabling customers in communications, industrial automation, aerospace and defense, automotive, semiconductor, and general electronics markets to accelerate innovation to connect and secure the world.

The post Keysight Partners with SRC for Advance EW Test and Simulation appeared first on ELE Times.

I placed order #48116 on 11 February 2026 for a soldering station. As of 19 May 2026, nearly 100 days later, the order has still not shipped. Tracking only shows that a shipping label was created, with no actual carrier movement. Before receiving any response at all, I sent multiple emails to all listed FNIRSI support addresses and also attempted to contact them through their website chat. I received effectively no responses through chat or email for an extended period. The only replies I eventually received came after I mentioned escalating the matter through my bank and making the situation public. Over roughly the following 3 weeks, I received only two short replies stating that the issue was being “escalated to manager”, but there were no further updates, no shipment, no refund, and no meaningful communication afterward. At this point I have neither received the product nor a refund. Based on my experience, I would strongly caution people against ordering directly from FNIRSI unless they are prepared to risk non-delivery and extremely poor customer support. If you want their products, I would recommend purchasing through a platform with strong buyer protection instead. submitted by /u/AdministrativeElk628 [link] [comments]

i think it is so funny how digikey packages their stuff. i ordered a pnp npn transistor pair and one came in the standard antistatic pin cushion the other came in a make shift package id describe as a chunk of plastic cut with four very intentionally placed rubber stoppers. they are trolls and my favorite company submitted by /u/Useful_Major8563 [link] [comments]

What makes a market success? Is there a Swiss-made sensor inside? Or maybe a wrist strap? What happened to the basics: cost-effective reliable functionality? (And yes, get off my lawn, you kids!).

Back in late March, I detailed my experiences setting up TP-Link’s entry-level Tapo H100 smart IoT hub and wirelessly mating it with a Tapo T315 smart temperature and humidity monitor a few rooms over:

along with, for good measure, a Tapo T300 smart water leak sensor downstairs. The Tapo T315 was effective in several respects: proving that the two DREO humidifiers (one of them also “smart”) were functioning effectively, and that whatever humidity sensing technology was being harnessed in conjunction with my furnaces was not functioning effectively and should be ignored going forward.

Display-optional when the data’s already app-visible?

The Kindle-reminiscent 2.7” e-ink display built into the T315 was convenient for at-a-glance monitoring of both humidity and temperature…that said, truth be told, I can count on the fingers of one hand, without using any of them more than once (and maybe even some of them at all) how many times I’ve looked at it since setting it up. To wit, at the end of that late-March writeup, I noted:

I’ve also got a redundant Tapo H100 smart hub and T300 smart water leak sensor, both sitting on the shelf, queued up for teardown, along with a display-less sibling of the T315 hygrometer, the Tapo T310 Smart Temperature and Humidity Sensor.

The Tapo T300 is still sitting on my teardown pile, although I plan to get to it soon (I promise, barring any out-of-my-control delay factors, of course). The Tapo H100 was dissected toward the end of last month. And today, you get the Tapo T310. I’ll as usual start with outer box shots, as usual accompanied by a 0.75″/19.1 mm diameter U.S. penny for size comparison purposes:

Marketing hype? Reality? A bit of both?

The back panel notes that the sensor is “high-accuracy”. The product page further elaborates that it’s “Swiss-made”. What is this, a watch (analogy)?

Snark aside, Google AI Overview informs me that:

Switzerland is a global leader in high-precision humidity sensors, with key manufacturers like Sensirion, Novasina, and IST AG providing advanced capacitive and resistive sensors. These sensors are renowned for high accuracy, long-term stability, and are widely used in HVAC, medical, and industrial applications.

Assuming Gemini’s not hallucinating, I suppose that I could apologize to TP-Link’s marketeers at this point. But I’ll pass :

Open sesame:

Inside, as previously documented on the left-side box panel, is our patient:

along with various mounting, opening and literature bits, plus a wrist strap presumably for sensing-on-the-move purposes, or perhaps just as a fashion statement (???):

Dear friends, we shall never speak of the wrist strap again. Instead, let’s focus our attention on the device itself. Front:

Left side (note to self: must not draw reader attention to the hole for the wrist strap…):

Back, showcasing the translucent aqua bit of plastic intended for the owner to yank out in order to power up and otherwise activate the device:

Right side:

Top, revealing the ventilation and sensing vent (and another view of another wrist strap hole…arrggh…):

And bottom:

Mobile-adjacent in multiple ways

That cellphone SIM card bracket-reminiscent hole is our pathway inside. As you might have noticed from one of the earlier pictures, TP-Link generously included a SIM card bracket removal-reminiscent tool. I instead went “old school” via a nearby paper clip:

Mission accomplished, so far at least:

Next to depart is the battery, a not-terribly-common (therefore nice of TP-Link to bundle with the device from the get-go) CR2450:

And our last step before diving inside is to dispense (temporarily) with the aqua translucent plastic strip. I’m aspiring for this teardown to be non-destructive, so I’ll strive to hold onto it for reinstallation (followed by the battery) afterwards. I could, of course, keep the battery out of the compartment until I’m ready to activate, gift, donate or otherwise deal with it, but I’m more likely to lose the battery, so…

Another simple-therefore-low-cost consumer device

And here we go…

That wasn’t bad at all, and it might even still work after I reassemble it (he says, realizing that he’s just jinxed himself in doing so)!

Now to pop out the PCB:

Starting with the PCB backside, the battery terminals are already a known entity. Aside from the embedded antenna supporting TP-Link’s 900 MHz ISM band wireless proprietary protocol for bidirectional communication with the Tapo H100 smart IoT hub, there’s not much else notable to see (unless you’re into mode switches, such as the toward-the-bottom one labeled SW1, that is). Look back at the earlier pre-case-opening image of the exposed battery compartment and you’ll notice both the switch’s user-accessible hole and a larger manufacturer-tailored opening for test point TP12. And at the time, I guessed that the device at the top edge, PCB-labeled U5, was the temperature sensor (hold that thought).

Highly integrated

Things get more interesting, as they often do with teardowns like these, when you flip the PCB over (and no, I’m not referencing the comparative abundance of test points on this side):

Toward the top (vertically), and toward the center (horizontally) is the system’s “brains”, Cmsemicon’s BAT32G135GE 64 MHz (max) Arm Cortex-M0-based application processor. Below it are, at left, a Hefei Jingweite Electronics (JWT) 26 MHz crystal oscillator, along with an IC labeled as follows to its right:

300A
N997
423

The one (and only) semiconductor-related result emerging from a Google search on that particular three-phrase sequence was a link to the beefy user guide (PDF) for Texas Instruments’ MSP430 embedded controllers. I was initially skeptical re the relevance of that result, but I decided to press on to the product line overview page, where I saw included there the CC1 series, based on the Arm Cortex-M3, which supports “Sub-1 GHz dual-band” wireless. So…mebbe? If so (and regardless, actually), note that the PCB-embedded antenna is interestingly visible on this side of the PCB, too. Maybe so it reliably works in various orientations when the device is leashed to the owner’s wrist…oops…

An identity crisis

Below it, the conceptual teardown image I shared with you earlier had informed me, was the “Swiss-made” humidity sensor, strangely labeled D1 on the PCB and also strangely surrounded by foam (for protective reasons, I initially presumed, since its package was lid-less):

(I’m loving the 5x macro telephoto lens on the Google Pixel 10 smartphone I just got, which I’ll have more to share about in future writeups!)

How the ambient humidity could get through that foam to the sensor, though, was beyond me. Then I noticed the front-side hole in the case, at the same location as D1, and figured that was how. But then I looked at this stock image:

and realized thee things:

• That hole in front was for an LED to shine though, actually
• D1 was that LED, not a humidity sensor, and
• The “temperature” sensor I’d previously noted on the PCB backside? I was half-right. It’s from Sensiron. And it does double-duty, sensing both temperature and humidity. Thereby even more completely explaining the topside vent proximity.

At this point, I could have just concluded that TP-Link’s marketing department has no clue how to draw conceptual images. But then I remembered TP-Link’s propensity for frequent hardware redesigns. And, giving the company the benefit of the doubt, I hit up the FCC certification page (2AXJ4T310) to have a look at the internal photos:

No such luck. The LED and humidity-and-temperature sensor seem to have always been in their current locations. TP-Link’s marketing department has no clue how to draw conceptual images.

With that, I’ll wrap up this writeup and turn it over to my readers for their thoughts in the comments. I’ll keep the device disassembled for a while after this writeup is published, in case you have any further questions, but eventually I’ll give reassembly-and-resurrection a shot.

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

• The Tapo Hub: TP-Link joins the low-bandwidth, long-range RF club
• TP-Link’s Tapo H100: Smart sensing unencumbered
• Tapo or Kasa: Which TP-Link ecosystem best suits ya?
• The Blink Sync Module 2: Faster response and local storage, too
• TP-Link’s Kasa EP10: If at first it doesn’t connect, buy, buy again

The post Smart hygrometers: Still largely useful even without integrated visual monitors appeared first on EDN.

Викладач-науковець і випускник НН ІПСА - новий Chief AI Officer у WINWIN AI Center of Excellence при Мінцифрі kpi пн, 05/18/2026 - 11:19

Вітаємо декана ФЕЛ з присвоєнням почесного звання «Заслужений працівник освіти України» kpi пн, 05/18/2026 - 11:13

Центр космічного зв’язку і радіоастрономії відкрито на Радіотехнічному факультеті kpi пн, 05/18/2026 - 10:58

Resistor networks are a great way to improve the gain accuracy and gain temperature drift of your system compared to designs using discrete resistors. One common motivation for improving gain accuracy and drift is that the initial system accuracy is good enough to skip calibration altogether. A common drawback of resistor networks is that there are a limited number of gain or attenuation options available, unlike discrete designs that can accommodate an essentially unlimited number of gain and attenuations.

This article shows how it’s possible to achieve 340 different gains and attenuations from just 10 resistor network ratios.

Take the case of RES11A, a resistor network that contains two resistor-divider networks (RG/RIN) in each package. The device is available in 10 product variants for different resistor ratios, with each variant identified by a suffix. For example, RES11A90 is the 9-to-1 ratio variant (see Figure 1).

You can use it to set gain on an operational amplifier or as an attenuator. The tolerance and drift of the resistors in the divider track closely, yielding significantly better attenuation accuracy and lower temperature drift than discrete resistors at a comparable price. RES11A, for example, has a worst-case tolerance of ±0.05% and temperature drift of ±2ppm/°C.

Figure 1 The above diagram highlights the functional blocks of the RES11A90 resistor network. Source: Texas Instruments

Swapping the input and output provides two different attenuations

The RES11A resistor network has 10 different resistor ratios, so you might think that you can only get 10 different attenuation values for this device. Keep in mind, however, that it’s not possible to swap the input and output of the attenuator, so each network can achieve at least two different attenuations.

Figure 2 shows how RES11A90 operates first as a 0.1 V/V and then a 0.9 V/V attenuator by simply reversing the connections. Thus, you can get at least 20 different attenuations from the 10 unique networks.

Figure 2 Swapping inputs and outputs on RES11A90 yields two different attenuations. Source: Texas Instruments

Combining both halves unlocks even more options

Generally, only one of the resistor pairs is active at a time when using RES11A as either an attenuator or a single-ended amplifier feedback network. But you can place the unused pair in series or parallel with either RIN or RG. Since all the resistors in the network were deposited in the same wafer processing step, they all have good ratio matching and drift matching.

Thus, the ratio, and drift accuracy of the combined divider will typically be the same as the individual dividers, although the worst-case ratio accuracy widens to ±0.1% with a ratio drift of ±4ppm/°C. Figure 3 illustrates how placing RG2 in parallel with RG1 achieves an attenuation of 0.818 V/V.

Figure 3 Using both halves of RES11A90 helps achieve a unique attenuation. Source: Texas Instruments

10 resistor network ratios, 34 configurations each

Different series and parallel combinations of both halves yield 34 different attenuations. Since there are 10 different variants of the network, the total attenuations possible with RES11A is 340 (34 × 10 = 340). Even accounting for duplicates, there are many unique attenuations. Figure 4 shows all 34 possible configurations.

Figure 4 Here are 34 possible attenuator configurations for the RES11A resistor network. Source: Texas Instruments

Manually sorting through so many options to determine which attenuator configuration meets your requirements isn’t practical. TI’s free Analog Engineer’s Calculator software tool identifies the best RES11A configuration to achieve your target attenuation or gain. Figure 5 illustrates how the calculator can find the resistor configuration for a target attenuation of 0.818 V/V.

Figure 5 The tool determines the RES11A configuration to achieve a 0.818 V/V attenuation. Source: Texas Instruments

Gain applications and compatible devices

While this article focuses on attenuation, RES11A also works well for setting gain on a single-ended or differential amplifier. In the case of a single-ended amplifier, combining both network divider halves results in many different gain values. Figure 6 shows the RES11A gain tool in the Analog Engineer’s Calculator to find different attenuations and gains.

Figure 6 This is how the tool finds gain of 3.5 V/V.

The tool also supports the RES21A and RES31A resistor networks, which share the same ratios as RES11A but scale overall resistance by a factor of 10 and 100, respectively. Thus, you can address your gain or attenuation requirement for RES11A and just substitute RES21A or RES31A if you require a higher overall resistance.

Ten ratio variants. Thirty-four configurations each. Three hundred forty reasons to leave the discrete resistor drawer closed.

Art Kay is applications engineer at Texas Instruments.

 

 

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• Why I’m fine with my calculator’s tiny decimal point
• Choosing and using resistive power splitters and dividers
• Splitting voltage with purpose: A guide to precision voltage dividers

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Пішов з життя Юрій Петрович Зайченко kpi нд, 05/17/2026 - 18:47

I built a scientific calculator from scratch: custom PCB, custom FPGA firmware, and a CPU I designed myself in Verilog. The physical build: a custom main board and keypad PCBs designed in EasyEDA and manufactured by JLCPCB, an Altera Cyclone II FPGA as the brain, an LCD display, battery with charging circuit, and two ROM-flashing connectors on the sides to update the firmware. Under the hood it runs a nibble-oriented CPU I designed specifically for BCD arithmetic: the way decimal calculators should work internally. I then wrote ~4K of machine code implementing the full set of scientific functions: trig, logarithms, complex numbers, statistics, all verified to 14 significant digits against a dedicated test suite. The full stack: Custom CPU in Verilog: Harvard architecture, 12-bit ISA, 8 registers, hardware fault detection Hand-written microcode assembler in Python Verilator + Qt simulation framework for development and debugging Custom PCB (EasyEDA / JLCPCB), battery, charging circuit, 3D printed case The finished device is sitting on my desk. Live WebAssembly demo (runs the actual Verilog + microcode in your browser): https://baltazarstudios.com/files/calculator-d/Calculator.html Write-up: https://baltazarstudios.com Source: https://github.com/gdevic/FPGA-Calculator Hackaday: https://hackaday.com/2026/05/13/build-the-cpu-then-build-the-calculator/ Happy to answer questions about the PCB design, the FPGA setup, or anything else. submitted by /u/gdevic [link] [comments]

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Безпека, стійкість, інформаційні технології та екологічний моніторинг Інформація КП пт, 05/15/2026 - 21:00

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