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Інститут кібернетики НАН України ім. В. М. Глушкова відзначений почесною відзнакою КПІ ім. Ігоря Сікорського kpi чт, 07/10/2025 - 22:32

NUBURU Inc of Centennial, CO, USA — which was founded in 2015 and develops and manufactures high-power industrial blue lasers — says that its stockholders have overwhelmingly approved key proposals in support of its financing strategy, a pivotal milestone in its strategic transformation for defense-tech and operational resilience through its Defense & Security Hub initiative...

There are multiple means of generating analog sawtooth waveforms. Here’s a method that employs a single supply voltage rail and is not finnicky about passive component values. Figure 1 shows a pair of circuits that use a single 3.3-V supply rail, one producing a ground-referenced sawtooth and the other a supply voltage-referenced one.

Figure 1 The circuitry to the left of the 3.3 V supply implements a ground-referenced sawtooth labeled “LO”, while that to the right forms a 3.3V-referenced one labeled “HI”.

Wow the engineering world with your unique design: Design Ideas Submission Guide

For the LO signal, R1 supplies adequate current to operate U1. This IC enforces a constant voltage Vref between its V+ and FB pins. Q1 is a high beta NPN transistor which passes virtually all of R2’s current (Vref/R2) through its collector to charge C1 with a constant current, producing the linear ramp portion of this ground-referenced sawtooth. (U1’s FB current is typically less than 100 nA over temperature.) M1 is a MOSFET that is activated for 100 ns every T seconds to rapidly discharge C1 to ground. Its “on” resistance is less than 1 Ω and so yields a discharge that lasts more than 10 time constants.

The sawtooth’s peak amplitude A is Vref × T / (R2 × C1) volts, where Vref for U1 is 1.225 V. For a 3.3-V rail, the amplitude (A) should be less than an Amax of 2.1 V, which requires T to be less than a Tmax of  R2 × C1 × 2.1V / Vref. With the availability of a U1 Vref tolerance of 0.2% and a 0.1% tolerance for R2, the circuit’s overall amplitude tolerance is mostly limited by an at best 1% C1 combined with the parasitic capacitance of M1.

M2, C2, Q2, R3, R4 and U2 work much like the circuit just described, except that they produce an “upside-down” 3.3-V supply-referenced sawtooth. Both waveforms can be seen in Figure 2. With the exception of U2, the tolerance contributions of these components are those previously mentioned for the “right side-up” design respectively. U2’s reference current is typically less than 250 nA over temperature, but its Vref of 1.24 V has at best a 1% tolerance. Figure 2 depicts both sawtooth waveforms.

Figure 2 The waveforms shown have peak values which are slightly less than the largest recommended. The period T is 34 µs.

These circuits do not require any precision or matched-value passive components. And there is no need to coordinate these component values with any active component’s parametric values or with the switching period T, as long as T is kept less than Tmax. The only effect that the non-zero tolerances of the passive components and of certain active parameters has been on the peak-to-peak amplitude of the sawtooth waveforms.

Christopher Paul has worked in various engineering positions in the communications industry for over 40 years.

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• Voltage-controlled triangle wave generator

The post Converting pulses to a sawtooth waveform appeared first on EDN.

Taking place from October 28 to 30, 2025 at the Shenzhen World Exhibition & Convention Center (Bao’an), NEPCON ASIA is the premier platform to discover the latest technologies and market trends, connect with new suppliers and products, and explore potential partnerships and distribution opportunities.

Featuring an ever-expanding showcase of automation equipment and technologies, the show empowers you to optimize your supply chain, reduce costs, and ensure quality and yield — all driving sustained growth in the electronics manufacturing industry.

Hundreds of New Product Launches

NEPCON ASIA 2025 will showcase hundreds of new products and solutions across SMT, testing and measurement, soldering, dispensing, semiconductor packaging, and automation. The show will feature over 600 leading exhibitors, including Yamaha, Hanwha, Fuji, Kurtz Ersa, Rehm, Tamura, Koh Young, TRI, ALEADER, Unicomp, Anda, and Axxon, connecting them with millions of buyers from high-growth sectors such as automotive electronics, semiconductors, and new energy.

The event aims to engage more than 2,000 buyers from emerging fields like low-altitude flight, embodied robotics, and AI, offering exhibitors invaluable exposure to new sectors.

Breakthrough Areas Driving Innovation

Several standout themed areas will debut, integrating industry resources and cutting-edge technologies, while showcasing packaging, testing, flexible manufacturing, assembly, and key components.

Key themed areas include:

• AI Smart Glasses Disassembly Area
• Flexible Manufacturing and Intelligent Transport System Area
• Low-Altitude Flight Components Disassembly Area
• Embodied Intelligence Robot Core Parts Disassembly Area
• Electronic Finished Products Automated Packaging Demonstration Area
• IGBT & SiC Packaging and Testing Demo Line

Conferences Empowering Industry Growth

NEPCON ASIA 2025 will host 40 high-level conferences covering advanced manufacturing, semiconductors, power electronics, robotics, and AI, empowering businesses to explore future technologies and seize new growth opportunities.

The SMTA South China High-Tech Workshop will feature global experts from China, the US, Japan, and Thailand, providing forward-looking insights for businesses.

The post NEPCON ASIA 2025: Innovating Smart Manufacturing Ecosystems and Bridging Global Opportunities appeared first on ELE Times.

👍🏰 Відкрито реєстрацію на молодіжні обміни «ВідНОВА:UA» – 2025! kpi чт, 07/10/2025 - 14:43

Discrete device designer and manufacturer Nexperia of Nijmegen, the Netherlands (which operates wafer fabs in Hamburg, Germany, and Hazel Grove Manchester, UK) has added two 1200V 20A silicon carbide (SiC) Schottky diodes to its portfolio of power electronics components...

Researchers at the Helmholtz-Zentrum Dresden-Rossendorf (HZDR) laboratory in Germany have developed e-skin with magnetic-sensing capabilities, which they refer to as magnetoreception. They incorporated giant magnetoresistance effect and electrical resistance tomography technologies to achieve continuous sensing of magnetic fields across an area of 120 × 120 mm2 with a sensing resolution of better than 1 mm. Instead of focusing on sensor readings at specific points, the magnetoreceptor captures electrical resistance information across the entire measurement domain.

Read the full story at EDN’s sister publication, Planet Analog.

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The post How spiders and eels inspired a magnetoreceptive sensor appeared first on EDN.

КПІ ім. Ігоря Сікорського співпрацюватиме з Ю+МАГ kpi чт, 07/10/2025 - 10:25

For second-quarter 2025, AXT Inc of Fremont, CA, USA — which makes gallium arsenide (GaAs), indium phosphide (InP) and germanium (Ge) substrates and raw materials — expects preliminary revenue of $17.5–18m, below the guidance of $20–22m provided on 1 May and down from $27.9m a year ago. This is due primarily to slower-than-expected issuance of export control permits for its GaAs products in Q2 and a weaker demand environment in China...

Студентка НН ІАТЕ Тетяна Гаврилюк про творчість, математику і страх kpi чт, 07/10/2025 - 01:35

Singapore’s Minister-in-charge of Energy and Science & Technology Dr Tan See Leng has officially opened the National Semiconductor Translation and Innovation Centre for Gallium Nitride (NSTIC (GaN)) as Singapore’s first national facility dedicated to gallium nitride...

Lively discussions have sprung up here in editor Aalyia Shaukat’s Design Ideas regarding the limitations and quirks of, and design tricks for, the current control topologies shown in Figure 1.

Figure 1 How to control amps of Iout with mA of Ic using legacy voltage regulators as current regulators where Iout  = (Vadj – IcRc)/Rs.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Reader Ashutosh Sapre contributed a disturbing observation about the likely effect on regulator reference accuracy of temperature rise from self-heating, as illustrated in Figure 2.

Figure 2 LM317 reference variation with junction temperature as seen in page 5 of LM317 datasheet.

As shown in Figure 2, the temperature stability of these legacy devices is fairly good. Nevertheless, there are situations where the tempco can be problematic. 

For example, consider a scenario that begins with programming for 100% of full-scale output current (e.g., 1 A) so that regulator heat dissipation is high. Assume it’s maintained long enough for the regulator’s junction temperature to rise from 25oC to 125oC. Figure 2 predicts that this large temperature swing will cause Vref to drift from 1.25 V to 1.2375 V, causing the output current to decline by about 1% of full scale. 

This 1% corresponds to 10 mA out of 1000 mA and is somewhat less than 3 LSB of an 8-bit setting. That’s perhaps not great, but it’s not horrible either. But what if the output is then reprogrammed for 10% of full scale (e.g., 100 mA) while the regulator is still hot?

Then that 1% of full-scale error would become 10% of setting is what. It will manifest as a very lengthy thermal settling tail lasting many seconds as junction temperature gradually cools from 125oC, allowing Vref to (slowly) return to its initial 1.25 V and output current to settle at the correct 100 mA. It will happen eventually, but the time required will be objectionable. It may be unacceptable.

Fortunately, Ashutosh also contributed a simple and practical solution to the problem in the form of an auxiliary current shunt transistor. The shunt would allow most of the output current and, consequently, most of the self-heating to bypass the regulator entirely. This would leave its junction unheated and its Vref undrifted. Problem solved!

Or is it? Ashutosh also pointed out that the bypass transistor, while handily solving the thermal problem, would unfortunately also bypass other things. Specifically, the nifty fault protection features (e.g., automatic current limiting and overheating shutdown) built into LM317 and LM337 chips would be lost. While these assets could potentially be added to the transistor shunt, that would lose much of the simplicity that made it attractive in the first place.

So, I wondered if Ashutosh’s shunt idea could be implemented in a way that would inherently retain the desirable 317/337 features while staying simple. The obvious thing (I like obvious!) might be to just make the shunt out of another LM3xx. Figure 3 shows just that: A design that cross-connects complementary regulators using U1’s 317 for control and U2’s 337 for shunt. Control and shunt currents are then summed back together before passing through Rs to provide feedback to U1 where Iout = (I2 + I3) = (Vadj_U1 – IcRc)/Rs and I3 >> I2. Notice how the shunt gets turned “upside down.”

Figure 3 Cross connection reduces self-heating error because shunt regulator U2 carries most of the current, getting relatively hot, while U1, whose Vref is in control, stays relatively cool and accurate.

Figure 3’s U1 is connected mostly per Figure 1, except for Rx. The signal developed by Rx * I2 feeds U2’s ADJ pin so that when U1 input current I2 rises above about 10 mA, U2’s ADJ pin will drop enough to make it start conducting. This causes the I3 current component to rise and ultimately comprise the majority of total current I1 = I2 + I3. Thus, U2 dissipates most of the self-heating Watts, ensuring that U1 remains relatively cool and its Vref remains accurate. 

The 1N4001 in parallel with Rx protects Rx and U2’s ADJ pin if U2’s over-temp or over-current shutdown feature kicks in. That would leave U1 trying to shoulder the whole load, dropping enough voltage across Rx to likely damage U2 and fry the resistor. The diode prevents that. 

Figure 4 shows the idea working as a negative current source.

Figure 4 If the 317 and 337 swap places and the diodes reverse, Figure 3’s circuit can work for negative current, too.

If more current capability is needed, more U2 shunts and higher capacity diodes can be added (Figure 5).

Figure 5 Boost current handling capacity with beefier diodes and more U2s.

Figure 6 integrates this idea into a complete PWM controlled negative current source as detailed in: “A negative current source with PWM input and LM337 output.”

Figure 6 Negative current source circuit incorporates means for compensating component tolerances, including those of U1 and Z1 references. Note Rs = 1.1 Ω and should be rated for more than 1 W.

The one-pass adjustment sequence is:

1. Set Df = 100%
2. Adjust CAL pot for 1 amp output current
3. Set Df = 0%
4. Adjust ZERO pot for zero output current.

Done. Iout = 1.1 Df /Rs, where Df = PWM duty factor.

In closing, thanks go (again) to savvy reader Ashutosh for his suggestions and (likewise again) to editor Aalyia for the fertile DI environment she created, which makes this kind of teamwork workable.

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

Related Content

• 1 A, 20V PWM DAC current source with tracking preregulator
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The post Cross connect complementary current sources to reduce self-heating error appeared first on EDN.

Under the scheme of the Ministry of Electronics and Information Technology (MeitY), the Government of India has given an in-principle approval to set up a ₹417 crore Electronics Manufacturing Cluster (EMC 2.0) in Gautam Buddha Nagar, Uttar Pradesh. Located on a vast, opulent 200-acre piece of land that is overseen by the Yamuna Expressway Industrial Development Authority (YEIDA), the project is estimated to garner investments of around ₹2,500 crore and generate approximately 15,000 direct jobs.

The cluster enjoys strategic location along the corridors of Yamuna Expressway, Eastern Peripheral Expressway, and the upcoming Palwal-Khurja Expressway. The Noida International Airport, which is being developed in Jewar, and the essential logistics hub of a railway station are both conveniently located nearby. Adjacent to this will be complementary zones like the Medical Device Park, MSME & Apparel Park, and planned Aviation Hub which will enhance things up in the regional industrial ecosystem.

Targeted Areas in the EMC 2.0:

Sectors	Examples
Consumer Electronics	TVs, Audio Systems, Smart Appliances
Automotive Electronics	Sensors, EV Controllers, Infotainment
Medical Devices	Diagnostics Devices, Monitors, Wearable Tech
Communication Equipment	Routers, Base Stations, 5G Infrastructure
Computer Hardware	Laptops, Servers, Data Storage Devices

 

The clusters are essentially ready-to-use factory sheds, supported by substantial power supply, water supply, sewage treatment, on-site accommodations, a healthcare system, and skill development centres.

Increasing Employment and Innovation:

Union Minister Ashwini Vaishnaw mentioned that components like this, conceived to generate 15,000 jobs and also enhance innovation and manufacturing excellence. It is furthered by this project to reduce the country’s import dependence by fostering high-growth sub-sectors such as semiconductors, IoT devices.

Government’s Vision:

Union Minister Ashwini Vaishnaw commented that this project is in alignment with PM Modi’s vision of Atmanirbhar Bharat and is a catalyst toward making India into a global electronics hub.

Besides, the upliftment of Uttar Pradesh in the electronics manufacturing sector is an emerging proposition on account of some of the really well-conceived policy initiatives, such as the UP Semiconductor Policy 2024, that encourage strategic location near burgeoning logistics and transport corridors.

Road Ahead:

With nearly ₹30,000 crore invested under the National EMC Scheme so far, more than 520 companies, and 86,000-plus jobs, the Noida EMC is yet another important tier towards India becoming a global electronic manufacturing hub.

While infrastructure and bureaucratic efficiency remain focal areas, UP’s consistent policy support, along with multimodal connectivity and cluster synergy, strongly position it to capture a significant share of India’s electronics future.

India’s digital production ecosystem has observed rapid growth over recent years. Over 55% of India’s smartphone production occurs in Uttar Pradesh, showcasing the state’s dominance in the sector. More than 86,000 jobs have been created, and more than 520 companies have come into existence across the country under the EMC initiatives. It further got a boost with the approval of the Foxconn-HCL Joint Venture near Jewar wherein an amount of ₹3,706 crore is being invested, and by 2027, this joint venture is expected to chip out 36 million semiconductor chips per month

Conclusion:

The ₹417 crore EMC in Noida is not just an infrastructure project but the cornerstone for creating a sustainable, job-rich, and globally competitive electronics ecosystem. With strong support from the state and union governments, this cluster will turn UP into a national leader in the electronics value chain.

The post Government-Backed EMC in UP to Accelerate India’s Electronics Growth appeared first on ELE Times.

Phlux Technology — which was spun off from the University of Sheffield in 2020 — is offering an evaluation board for its Aura family of Noiseless InGaAs avalanche photodiodes (APDs). The APDs are used as 1550nm infrared sensors and claim 12x greater sensitivity than traditional devices in applications spanning laser rangefinders, optical networks and test equipment, and LiDAR...

Anritsu Corporation announced that its receiver test (SINK Test) solution for the latest DisplayPort 2.1 standard has been certified by the Video Electronics Standards Association (VESA), the international standards organization. Combining Anritsu’s Signal Quality Analyzer-R MP1900A with automation software from Granite River Labs (GRL) or Teledyne LeCroy achieves automated verification of data transmission quality and calibration.

DisplayPort 2.1 enables the digital transmission of high-definition and high-refresh-rate video, such as 8K. The standard is still being developed. Recently, the integration of the USB Type-C specifications has led to a significant expansion in the versatility of DisplayPort 2.1 and its adoption across a wide range of applications. However, a challenge facing the development of products that comply with the new standard is that manually verifying transmission signal quality and calibrating are time-consuming due to the complexity of the test equipment settings and the lengthy configuration and test procedures. This solution improves development efficiency and ensures the quality of video data transmission by automating the testing and calibration processes.

The post Anritsu Gains Certification for Latest DisplayPort 2.1 Video Interface Standard Testing Solution appeared first on ELE Times.

Infineon Technologies AG is expanding its offering for universal serial bus (USB) tokens, dongles, security keys, and other hardware authenticators with the introduction of the new Infineon ID Key family. The newest member, the ID Key S USB is a highly secured and versatile product designed for a wide range of USB- and USB/NFC-token devices and applications. It combines the security, performance, and reliability of the Infineon SLC38 security controller with a USB bridge controller in one single package. It is a unique system-in-package solution that enables high flexibility and simplifies complex application deployments while reducing the bill of materials and related costs. Certified to highest security levels, it supports a range of use cases, including certificate-based authentication, Fast Identity Online (FIDO) authentication with device-bound passkeys, digital signatures, encryption, access control, software protection, and cryptocurrency hardware wallets.

The increasing need for secured online transactions and the growing threat of cyber-attacks have created a surge in demand for secured and hardware-backed authentication solutions. “As the market shifts towards more secured and convenient authentication methods, we see a growing trend towards the adoption of advanced security solutions,” said Maurizio Skerlj, Senior Vice President and Product Line Head Authentication & Identity Solutions at Infineon’s Connected Secure Systems Division. “With the ID Key S USB, we are well-positioned to address this trend and provide our customers with a robust solution that meets their needs.”

The ID Key S USB offers a range of key features that support its secured and versatile design and boasts a comprehensive array of features. Its high-performance capabilities are driven by a 32-bit CPU clocked at 100 MHz and a large 24 kB RAM, enabling ultra-fast and secured execution of applications and delivering excellent operating system performance for a wide range of use cases. The device also offers sufficient memory, with non-volatile memory sizes of up to 800 kB providing ample storage for large amounts of data, cryptographic keys, software, and multiple applications. Furthermore, the ID Key S USB has achieved highest security levels, with certification to CC EAL 6+ (high) and compliance with FIPS 140-3 hardware requirements, allowing customers to apply for FIPS 140-3 certification for their product. The ID Key S USB features a compact footprint of 4 x 4 x 0.85 mm, making it ideal for integration into space-critical token devices.

The post Infineon expands security controller portfolio for USB tokens with new ID Key S USB for more security and versatility appeared first on ELE Times.

Dhruva Space Private Ltd of Hyderabad, India (which provides satellites coupled with Earth stations and launch services) has entered into a strategic partnership with Bengaluru-based space data company and spacecraft manufacturer Pixxel, which is building the world's highest-resolution hyperspectral imaging satellite constellation (enabling the detection, monitoring and prediction of critical global phenomena across agriculture, oil & gas, mining, environment, and other sectors, with what is reckoned to be 50x richer detail than conventional satellites). This India-based collaboration will see Dhruva joining forces with Pixxel to integrate space-grade solar panels into their next satellite fleet...

💛💙 Навчання ветеранів у КПІ ім. Ігоря Сікорського kpi ср, 07/09/2025 - 10:37

System-level test (SLT), once used largely as a stopgap measure to catch issues missed by automated test equipment (ATE), has evolved into a necessary test insertion for high-performance processors, chiplets, and other advanced computational devices. Today, SLT is critical for ensuring that chips function correctly in real-world conditions, and all major CPUs, APUs, and GPUs now go through an SLT insertion before shipment.

Adding SLT in production is being considered for network processors and automotive processors for driver assistance. However, implementing SLT techniques effectively at scale poses key challenges in terms of managing costs, test times, and manufacturers’ expectations.

One of the biggest misconceptions about SLT is that it functions like ATE. ATE primarily uses pre-defined test patterns to stimulate circuit paths and check expected responses within individual cores or circuit blocks. On the other hand, SLT focuses on system interactions that occur between those cores or outside the chip.

That includes software, power management, sensor integration, and communication between internal cores and peripheral devices. Since SLT is often used to test cutting-edge chips, the test environment needs to be flexible so that it can handle application-specific conditions and different interface protocols.

This distinction is particularly relevant as the industry shifts toward chiplet-based architectures. With chiplets, manufacturers need to test how signals propagate across multiple interconnected dies, rather than just validating individual components in isolation.

Test pattern creation for traditional ATE methods, used for chip package-level testing, offers limited access to internal interactions within a multi-chip package. SLT, on the other hand, can exercise how data flows between chiplets and how this influences performance, power consumption, and overall system functionality.

However, this approach comes with its own unique complications, especially since many SLT methodologies are implemented manually.

Test coverage challenges

Using conventional design for test (DFT) techniques to generate test patterns ahead of production ramp, chip designers are lucky to get 99% coverage of all the transistors. However, for devices with 100 billion transistors, such as today’s advanced artificial intelligence (AI) processors, 1 billion transistors still go untested. Using purely ATE test methods, achieving that last 1% of test coverage could take months of development and significant tester time.

Moreover, today’s complexity of integrating heterogeneous chiplets into one large package challenges the stability and repeatability of the electromechanical stack-up in a high-volume test environment. There are limited test access points to the outside world that must stimulate pathways through multiple dies.

Because the packages are large, there may be warpage and restricted mechanical compression points for actuating the device-under-test (DUT) connections in the socket. Exercising processors and memories inside the same package under extreme test conditions, there are inevitable hot spots that must be managed to prevent damage to the device.

To provide a durable automated system-level tester with high availability in manufacturing, the customer test content must be tightly integrated with socket actuation and thermal control, along with power management and test sequencing.

Compounding the complexity of test content development is how many parties may be involved in optimizing the SLT insertion. Vendors of SLT equipment, sockets, and design and test IP must collaborate with the silicon designer/integrator, custom ASIC end-user, outsourced semiconductor assembly and test providers (OSATs), board designers, and even customers—for example, manufacturers of data centers, computer vendors and cellphone devices—to make sure the test station represents the real-world application it’s intended to test.

As the demand for processing power increases, chip designs have evolved to meet market requirements. This increase in processing power results in higher energy consumption and heat generation. So, test time for a typical SLT insertion can be a half hour or more, requiring many test stations to meet the monthly volume demands.

The buildings built to test the parts must have special facilities for electrical power and thermal control. Therefore, these test facilities aim to maximize their investment by testing as many devices in the smallest floor space as possible. However, the devices and their test application boards are getting bigger and consume more power.

Emerging developments in chip testing

Chip designers and EDA vendors have developed and introduced new DFT techniques that allow structural test content to be delivered as packetized data over standard high-speed serial ports like USB and PCIe. During SLT, these ports must be enumerated at the application level so that the port operates as intended.

Once this connection is made, the test program can switch into a test mode using a small number of high-speed pins to run structural test patterns or other built-in self-test functions. Once these serial data ports are working, the test content can be reused and correlated either to ATE with similar test stations (such as Link Scale) or post-silicon validation test stations (such as SiConic) to improve time to market and reuse.

Managing the heat dissipation of these high-power devices under extreme workload is a ubiquitous problem being addressed at the engineering, bench, ATE and SLT test insertions, and even in data-center-wide operation. Air, liquid, and refrigerants are all utilized, with an eye on environmental sustainability. Production test handlers have the added challenge of cycling heat and mechanical engagement multiple times per day.

The use of AI and machine learning (ML) is also being applied to semiconductor testing. Sharing the test result data between different test insertions, including ATE, burn-in, and SLT, feeds into AI and ML tools to improve yield, accelerate test-program development, and optimize test times.

Looking ahead

As semiconductor manufacturing becomes more complex, SLT will continue to grow in importance. For it to be truly effective, companies must integrate it into their overall testing strategy rather than treating it as a separate, isolated step. And the next generation of system-level testers must focus on addressing the challenges cited above. Success will require collaboration across design, test, and high-volume manufacturing teams, as well as a willingness to rethink traditional approaches to validation.

In an era defined by multi-chip packages, heterogeneous integration, and ever-tightening performance demands, SLT will remain a crucial tool for ensuring that cutting-edge chips perform as expected in real-world applications.

Davette Berry is senior director of Customer Programs & Business Development at Advantest.

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• System-level verification tool rolls
• 3 tips for system-level test-driven development
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The post System-level test’s expanding role in producing complex chips appeared first on EDN.