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Learning about LLC resonant power supplies and micropython for Pico W. submitted by /u/coderlogic [link] [comments]

🎥 Студенти КПІ відвідали Броварський завод котельного устаткування ARDENZ kpi чт, 05/29/2025 - 22:20

The ESP32 C3 is connected to a DHT11 and a 4x 8x8 MAX7219 LED matrix. The cable management wasn't remotely as relaxing as I imagined it in my fantasy. submitted by /u/satina_nix [link] [comments]

Aeluma Inc of Goleta, CA, USA — which develops compound semiconductor materials on large-diameter substrates — has announced an advance in silicon photonics that could accelerate the adoption of quantum computing and communication at commercial scale, it is reckoned...

Built on a 22-nm process, Silicon Labs’ SiXG301 and SiXG302 wireless SoCs deliver improved compute performance and energy efficiency. As the first members of the Series 3 portfolio, they target both line- and battery-powered IoT devices.

Designed for line-powered applications such as LED smart lighting, the SiXG301 integrates an LED pre-driver and a 32-bit Arm Cortex-M33 processor running at up to 150 MHz. It supports concurrent multiprotocol operation with Bluetooth, Zigbee, and Matter over Thread, and includes 4 MB of flash and 512 kB of RAM. Currently in production with select customers, the SiXG301 is expected to be generally available in Q3 2025.

Extending the Series 3 platform to battery-powered applications, the SiXG302 features a power-efficient architecture that consumes just 15 µA/MHz when active—up to 30% lower than comparable devices. It is well-suited for battery-powered wireless sensors and actuators using Matter or Bluetooth. Sampling is expected to begin in 2026.

The SiXG301 and SiXG302 families will initially include two types of devices: ‘M’ variants (SiMG301 and SiMG302) for multiprotocol support, and ‘B’ variants (SiBG301 and SiBG302) optimized for Bluetooth LE.

Series 3 product page 

Silicon Labs 

The post Wireless SoCs drive IoT efficiency appeared first on EDN.

ST offers three antenna-matching companion chips for STM32WL33 wireless MCUs to help streamline the development of IoT, smart metering, and remote monitoring systems. The MLPF-WL-01D3, MLPF-WL-02D3, and MLPF-WL-04D3 integrate impedance matching and harmonic filtering on a single glass substrate to boost RF performance.

By integrating antenna protection, matching, and filtering, the devices simplify RF routing, improve reliability, and reduce BOM cost by replacing multiple discrete components. The three Series 3 chips will be joined by four new variants, supporting radio optimization across high-band (826–958 MHz) and low-band (413–479 MHz) ranges, high-power (16/20 dBm) and low-power (10 dBm) modes, and 2-layer or 4-layer PCB designs.

The MLPF-WL-01D3, MLPF-WL-02D3, and MLPF-WL-04D3 antenna-matching ICs are available now in 5-bump chip-scale packages, priced from $0.15 each in 1000-unit quantities. Release dates for the additional variants were not available at the time of this announcement.

MLPF-WL-0xD3 product page

STMicroelectronics

The post Antenna-matching ICs cut RF design complexity appeared first on EDN.

The NTAG X DNA from NXP is an ISO/IEC 14443-4 Type 4 NFC tag that enables secure authentication of NFC-enabled mobile devices. It features 16 kB of memory, high-speed data transfer, and Secure Unique NFC (SUN) authentication to protect devices across healthcare, smart home, consumer electronics, and industrial markets.

Supporting device-only, device-to-device, and device-to-cloud authentication, the NTAG X DNA secures data transfer via NFC or I²C interfaces at speeds up to 848 kbps and 1 MHz, respectively. A direct MCU connection enables device diagnostics, while the tag’s memory allows access to stored authentication data—even without power. Sensitive information can also be erased in power-off conditions to protect user privacy.

Designed to combat counterfeits and support Digital Product Passport (DPP) compliance, the NTAG X DNA offers strong security with Common Criteria EAL 6+ certification and PKI-based asymmetric cryptography. It is backed by NXP’s EdgeLock 2GO service for UID and certificate delivery, as well as on-demand certificate generation.

NTAG X DNA product page

NXP Semiconductors 

The post IC safeguards NFC communication appeared first on EDN.

Qorvo’s QPA3311 and QPA3316 hybrid power doubler amplifiers are optimized for DOCSIS 4.0 downstream operations up to 1.8 GHz. They support the transition to Unified DOCSIS and smart amplifier architectures that enhance visibility, efficiency, and adaptability in hybrid fiber-coax (HFC) systems.

Based on a GaAs/GaN die, the devices operate from 45 MHz to 1794 MHz and provide 23 dB of gain. They are well-suited for DOCSIS 4.0 CATV nodes and amplifiers. High total composite power and improved signal integrity reduce cascade requirements and enhance end-of-line performance, helping lower infrastructure costs by eliminating the need for booster amps.

The QPA3311 and QPA3316 power doublers operate from 24-V and 34-V supplies, respectively, with power consumption of 12.5 W and 18 W. At 51 dB CNN, total composite power reaches 74 dBmV for the QPA3311 and over 75 dBmV for the QPA3316.

Both the QPA3311 and QPA3316 power doubler amplifiers are housed in SOT-115J packages and are now in production.

QPA3311 product page

QPA3316 product page 

Qorvo

The post Power doublers enable smooth DOCSIS 4.0 upgrades appeared first on EDN.

Asahi Kasei has developed the Sunfort TA series of dry film photoresist for next-generation semiconductor packages requiring circuit patterns with line/space widths of 2/2 µm or less. The film offers high resolution with conventional stepper and laser direct imaging (LDI) systems—used to transfer circuit patterns onto substrates—enhancing precision in back-end processes.

The TA series supports fine wiring formation in panel-level packages and related applications. It enables patterning with a 1.0-µm resist width using LDI exposure in a 4-µm pitch design, as required for redistribution layer (RDL) formation (Figures a and b). The resulting fine resist pattern can be plated by a semi-additive process, then stripped to yield a 3-µm wide plating pattern within the same 4-µm pitch (Figure c).

Asahi Kasei states that Sunfort dry film photoresist will remain integral to advancing panel-level packaging technology as panel sizes increase. With its ability to achieve finer wiring and improve production efficiency, the TA series addresses the rising demand for advanced semiconductor package substrates and interposers in AI, automotive, communications, and IoT markets.

TA series product page

Asahi Kasei 

The post Dry film photoresist enables fine circuit formation appeared first on EDN.

Макулатура зі змістом: КПІ передає списану літературу на переробку на благо природи та розвитку Університету kpi чт, 05/29/2025 - 18:21

Україна – Європа: жіноче обличчя Інформація КП чт, 05/29/2025 - 17:44

Hi everyone! I'm a second-year Electrical & Electronics Engineering student, and this is my EMG (Electromyography) sensor project, built as part of the Analog System Design course in my curriculum. The circuit is designed to pick up muscle activity using surface electrodes. It starts with a differential amplifier stage using an LF356 op-amp to extract the low-amplitude bioelectric signals I made all the calculations and simulation using an Instrumentation Amplifier but had to change it to this becuse the INA was not remotely available. These signals are then processed through active filters and a precision rectifier using TL084 and TL081 op-amps, ultimately providing a DC output that indicates muscle contraction. The left side three screw terminals are the input from surface electrodes, right side three screw terminals are the power input VDD, VEE and Ground, the double screw terminals is the DC output signal. I soldered the components on a perf board for the first time ever, focusing on compactness, clean signal routing, and minimal noise. Sharing it here to showcase the design and gain insight from the community on areas like soldering quality, layout decisions, and analog design. submitted by /u/TheArtShack-22 [link] [comments]

The code is based on the work of Johnathan Chiu which he posted here. I am using an ESP-32 with a potentiometer joystick, power is supplied trough a 18650 battery and I used a chep USB Type C charging module. I only modified Johnathan Chius code to include a part for reading from the potmeter. My experience with the remote: I built the remote itself about a year ago and since the used it a couple of times, so far without any trouble. Since I didn't add the code necesary to auto-pair the remote to the board, every time I turn on the remote I have to pair it to the board. The banana shape isn't as comfortable to hold as I thought it would be and I have to press on the deadman switch pretty hard, but it looks awesome. If you have any questions I'm glad to answear them! submitted by /u/thebananamanforever [link] [comments]

The typical regulator output network

Many voltage regulator chips, both linear and switching, use the same basic two-resistor network for output voltage programming. Figure 1 illustrates this feature in a typical switching (buck type) regulator, see R1 and R2, where:

Vout = Vsense(R1/R2 + 1) = 0.8v(11.5 + 1) = 10v

Figure 1 A typical regulator output programming network where the Vsense feedback node and values for R1 varies from type to type.

Quantitatively, the Vsense feedback node voltage varies from type to type and recommended values for R1 can vary too, but the topology doesn’t. Most conform faithfully to Figure 1. This de facto uniformity is useful if your application involves PWM control of Vout. 

Wow the engineering world with your unique design: Design Ideas Submission Guide

The three-component PWM-to-regulator solution

Figure 2 shows the simple three-component solution that the above topology makes possible. Note, the PWM duty factor (DF) is from 0 to 1, where:

Vout = Vsense(R1/(R2/DF) + 1) = DF(11.5)0.8 + 0.8 = DF*9.2 + 0.8v

Figure 2 Three parts comprise a circuit for linear regulator programming with PWM.

To introduce linear PWM control to the Figure 1 regulator, all that’s required is to add three discrete components: the PWM switch Q1, and the ripple filter capacitors C1 and C2. Note that Vout will go to Vsense(C1/C2 + 1) = 10v for about 6 ms during power up while C1 and C2 are charging, but that should be okay.

The C2 capacitance required for 1 lsb (0.4%) PWM ripple attenuation is C2 = 2(N-2)/(R1*Fpwm), where N is number of PWM bits, and Fpwm is the PWM frequency (10 kHz illustrated).

Then, to avoid messing with U1’s designed loop gain, possibly reducing stability, C1 = C2*R2/R1. This capacitance ratio also provides protection for U1’s Vsense input, since it ensures that even a sudden short of Vout to ground can’t drive Vsense dangerously negative.

 This combination of time constants yields a first-order 8-bit settling time of T8 = R1C2ln(256) = 37ms. More on this lengthy number shortly.

A cool feature of this simple topology is that, unlike many other schemes for digital power supply control, only the precision of R1, R2, and the regulator’s internal voltage reference matter for regulation accuracy. Precision is therefore independent of external voltage sources, e.g., logic rails. Precision, measured as percentage of Vout, is also independent of Df, and remains equal to Vsense precision (e.g., ±1%) for all output voltages.

Speeding up the settling time

What if a 37-ms settling time is too lengthy for your application? What if you wouldn’t mind investing a couple more parts to speed it up? Figure 3 shows what.

Figure 3 Add R3 and C3 to get analog ripple subtraction, second-order filtering, and a 7-ms settling time. The symbol “*” represents a precision of 1% or better.

First disclosed in EDN Design Idea (DI), “Cancel PWM DAC ripple with analog subtraction,” a thrifty way to implement second-order PWM ripple filtering is through the analog subtraction of the AC component in the logic inverse of the PWM signal from the DC result. Figure 3 shows how that can be accomplished by simply adding R3 and C3 to the Figure 2 topology. Note that the impedance ratios of the added parts are equal to the ratio of the 5-Vpp PWM signal at Q1’s gate to the 0.8-Vpp logic complement at its drain = 5v/0.8v = 6.5.  This is why R3 = 6.5*R2 and C3 = C2/6.5.

In closing: This DI revises an earlier submission, “Three discretes suffice to interface PWM to switching regulators.” My thanks go to commenters oldrev, Ashutosh Sapre, and Val Filimonov for their helpful advice and constructive criticism. And special thanks go to editor Shaukat for her creation of an environment friendly to the DI teamwork that made this possible.

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

 Related Content

• Three discretes suffice to interface PWM to switching regulators
• Cancel PWM DAC ripple with analog subtraction
• PWM power DAC incorporates an LM317
• 1-A, 20-V, PWM-controlled current source
• 0 V to -10 V, 1.5 A LM337 PWM power DAC
• Tracking preregulator boosts efficiency of PWM power DAC
• Another PWM controls a switching voltage regulator
• Control an LM317T with a PWM signal

The post Revisited: Three discretes suffice to interface PWM to switching regulators appeared first on EDN.

At the IEEE MTT-S International Microwave Symposium (IMS 2025) in Moscone Center, San Francisco, CA, USA (15–20 June), MACOM Technology Solutions Inc of Lowell, MA, USA is showcasing its portfolio of high-performance RF, microwave and millimeter-wave (mmWave) solutions and foundry services, with technical experts available to highlight performance advantages, plus a full lineup of technical presentations throughout the show...

Акредитація освітніх програм КПІ ім. Ігоря Сікорського 2025/05/28 kpi чт, 05/29/2025 - 14:48

Infineon Technologies AG of Munich, Germany has announced the first of a new family of radiation-hardened gallium nitride (GaN) transistors, fabricated at Infineon’s own foundry, based on its proven CoolGan technology. Designed to operate in harsh space environments, the new product is the first in-house-manufactured GaN transistor to earn the highest quality certification of reliability assigned by the US Defense Logistics Agency (DLA) to the Joint Army Navy Space (JANS) Specification MIL-PRF-19500/794...

The chip market for micro-LED display applications is rising at a compound annual growth rate (CAGR) of 93% from US$27.9m in 2024 and US$39m in 2025 to US$744.7m by 2029, forecasts TrendForce...

For decades, we heard silicon was the only answer. However, while the world’s largest fabs were busy taping out silicon, the communities of engineers and scientists working on non-silicon technologies continued pushing forward. Compound semiconductors—semiconductors made from two or more periodic table elements—include indium phosphide (InP), silicon nitride (SiN), gallium arsenide (GaAs), germanium (Ge), indium gallium arsenide (InGaAs), cadmium telluride (CdTe), gallium nitride (GaN), and silicon carbide (SiC).

Once Tesla introduced SiC MOSFETs in its EVs in 2018, SiC would no longer go unnoticed. The market has grown to more than $2.5 billion in 2024, and despite the temporary slowdown in 2025, is expected to continue growing at a staggering pace according to Yole and TrendForce.

Most EV electronics suppliers now offer SiC power ICs, creating a new ecosystem of material suppliers, capital equipment, fabless companies, foundries, and outsourced semiconductor assembly and test (OSAT) service suppliers.

Some integrated device manufacturers (IDMs)—including Bosch, Denso, Infineon, onsemi, Rohm, SanAn, STMicroelectronics, and Wolfspeed—went fully vertical starting with the SiC powder and ending with multi-die power modules.

Figure 1 SiC’s bubble size indicates its manufacturing volume and annual growth. Source: Author

Many newcomers got into the substrate business because of the high cost of the raw material. They invested heavily in mergers and acquisitions and organic growth and are now faced with the challenge of returning investment to shareholders. In this highly competitive environment, manufacturers are pushed to new levels in yield, quality, efficiency, and capacity.

Benefits are costly

SiC offers benefits to designers and consumers. Thanks to the material properties, SiC transistors can be operated at much higher voltages with lower resistance, showing less performance degradation with temperature, making SiC electronics appealing for power conversion and charging applications in vehicles and power grid applications.

However, the raw material is substantially more expensive than silicon. Crystal growth is orders of magnitude slower than silicon—its hardness, second only to diamond, makes it hard to slice, polish, and dice. High operating voltages require thick epitaxial layers that exhibit high defectivity. Next, vertical transistor architecture requires substantial wafer backside processing. All this translates to higher defectivity and lower yield with frequent yield excursions.

To the consumer, it’s higher product cost and lower reliability in the field.

Years behind silicon

“SiC is decades behind silicon,” is the common cliché among manufacturers. Here, the dominant wafer size is a good indication of material platform maturity. Historically, as silicon manufacturing matured, the industry transitioned to a larger wafer size, going through 100-, 150-, 200- and 300-millimeter (mm) wafers over the four decades, as shown in the figure below.

Figure 2 Most of the high-volume manufacturing capacity for SiCs is expected to remain on 150-mm wafers. Source: Author

Presently, SiC is made predominantly on 150-mm substrates. Meanwhile, several companies announced a transition to 200-mm substrates. While Chinese substrate supplier SICC demonstrated 300-mm substrate in 2024, use of such a large substrate is beyond the horizon. In the next several years, most of the capacity is expected to remain on 150-mm wafers.

Yes, SiC is 30 years behind silicon, judging by the substrate sizes in volume manufacturing.

Complexity of SiC circuits resembles silicon chips in the 1980s—integration into complex circuits today is at the package level rather than on a monolithic IC as seen in silicon. While the most complex silicon ICs count billions of transistors, SiC ICs are nowhere near such complexity. The reason is simple—die yield scales exponentially with the die area. At high defectivity levels, this becomes detrimental, and the only answer is going with a smaller die, integrating known good die at the package level into a more complex circuit.

However, while SiC seems decades behind silicon, it does not need decades to catch up.

The big data platform

Methodologies developed over the decades in silicon IC manufacturing are now available. One example is a solution that deploys data analytics for silicon utilized to streamline innovation. The benefits are numerous:

• Breaking the silos: The technology cycle from IC design to high-volume manufacturing is long with many players and data silos across operations. That’s where end-to-end big data platforms can connect all data end-to-end and make it available to a broad range of functions.
• Smart factory: Front-end factories are different from their predecessors. Today’s manufacturing ecosystem offers a variety of software capabilities from dozens of suppliers with well-established interoperability.
• Standardization: Thanks to several organizations—including SEMI, Global Semiconductor Alliance (GSA), and Semiconductor Industry Association (SIA)—there is a broad landscape of industry standards covering everything from equipment connectivity to data formats and specifications. Standards enable better interoperability between tools and suppliers, streamlining equipment and software deployments to support yield ramps.
• Material traceability: Whether the need is for tracing wafers in a fab or die in an assembly line, the task is complex and ranges from multiple substrate IDs and rework at different steps to substrate grading to cherry-picking. In an assembly line, it’s a challenge solved with traceability standards.
• Data models: A data model details material data, inline data from the fabs, and assembly and test data from OSATs. It describes physical entities such as equipment, wafers, dies and modules, processes including fab, assembly and test, and their relationships in the context of manufacturing flow.
• Artificial intelligence/machine learning (AI/ML): Decades ago, scientists had to develop analytical relationships between causes and effects, while software developers came up with software specifications. A myriad of data-centric frameworks and the ubiquity of AI/ML now shorten this cycle, eliminating numerous bottlenecks.
• Too much data: Vast amounts of data are generated per wafer throughout the manufacturing operations, though most of that data is never used. At the same time, engineers in the automotive segment are putting more stringent requirements on their chip and module suppliers regarding data collection and retention. The data platform must enable a good mix of storage options allowing tradeoffs between performance and cost and provide the knobs for data caching and aging.

Adopting an industry-standard solution allows manufacturers to improve efficiency and ramp yields faster than the competition.

What’s next

According to Yole, TrendForce, McKinsey and SEMI, growth is forecasted for most compound semiconductor devices, with silicon carbide at the top of that list. Following Gartner’s terminology of the “hype cycle,” it’s past disillusionment. Both silicon and GaN have been carving out more space in the power IC market. This change will push SiC for performance and cost.

At the same time, more suppliers are stepping into the market in each segment—material suppliers, foundries, fabless and IDMs. Competition will intensify, pushing manufacturers for higher yields, faster development cycles, and higher levels of integration.

Under pressure for cost and performance, designers and manufacturers must start adopting big data platforms.

Steve Zamek, director of product management at PDF Solutions Inc., is responsible for manufacturing data analytics solutions for foundries and IDMs. Prior to this, he was with KLA (former KLA-Tencor), where he led advanced technologies in imaging systems, image sensors, and advanced packaging.

Related Content

• The Road to 200-mm SiC Production
• Silicon carbide (SiC) counterviews at APEC 2024
• Wolfspeed to Build 200-mm SiC Wafer Fab in Germany
• Silicon carbide’s wafer cost conundrum and the way forward
• Reducing Costs, Improving Efficiency in SiC Wafer Production with CMP

The post Accelerating silicon carbide (SiC) manufacturing with big data platforms appeared first on EDN.

Випускник КПІ Владислав Бойко: "Інженерія – справа мого життя!" kpi чт, 05/29/2025 - 12:13