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It's your old basic digital clock project but with simple gates made of diodes and transistors. Left - minutes 00-59 logic with 7490s and diode-transistor logic Middle - PCB for hour 00-23 logic Right - 1Hz clock module with 4060 counter and transistor divide-by-2 latch and "pseudo-sawtooth" output submitted by /u/ZaznaczonyKK [link] [comments]

Toshiba Electronic Devices & Storage Corp of Kawasaki, Japan has started volume shipments of four new 650V silicon carbide (SiC) MOSFETs (TW031V65C, TW054V65C, TW092V65C and TW123V65C), equipped with its latest third-generation SiC MOSFET chips and housed in a compact 8mm x 8mm x 0.85mm DFN8x8 package...

As introduced last October, the summer of 2024 was once again brutal from a lightning-induced electronics-culling standpoint at the Dipert household. I’ve already covered the hot tub control board that got zapped, as well as documenting the laundry list of other now-DOA devices:

Once again, several multi-port Ethernet switches (non-coincidentally on the ends of those exterior-attached network cable spans) got fried, along with a CableCard receiver and a MoCA transceiver (both associated with exterior-routing coax). My three-bay QNAP NAS also expired, presumably the result of its connection to one of the dead multi-port Ethernet switches. All this stuff will be (morbidly) showcased in teardowns to come.

Those teardown showcases start today with the last item on the list, the QNAP TS-328, which I’d purchased on sale for $169.99 back in January 2019 and fired up for service the following September in 2020. Here again to start are the stock photos I shared back in December 2020 when I editorially covered the TS-328 in detail for the first time (dimensions are 5.59” (H) × 5.91” (W) × 10.24” (D), and its net weight absent HDDs is 3.62 lbs.):

The NAS (network-attached storage device) is tipped over on its left side for “show” in that second photo, if not already obvious. In normal operation, it’s the HDDs that are on their sides.

Now for some real-life snapshots of today’s patient, as usual, accompanied by a 0.75″ (19.1 mm) diameter U.S. penny for size comparison purposes. Front (various status and activity LEDs along the left side, with the power and USB copy buttons, the latter with an integrated USB 3.0 connector for a tethered external storage device, below them):

(Bland) top:

(Even more bland, at least on the outside…hold that thought) left side:

Right side:

Back, with the fan dominating the landscape at upper left, a Kensington security lock site at lower left, the “full range” system speaker (vs the PCB buzzer, which you’ll see later) to its right, and (top-to-bottom along the right side) the recessed reset switch, an undocumented-details (TS-328 user manual is here) “maintenance port”, an audio line-out jack, two RJ45 Gigabit Ethernet ports, side-by-side USB 2.0 (left) and 3.0 (right) connectors, and the power input:

And last, but not least, bottom:

Before I forget, here’s the external power supply (which still seems to be fully functional):

Those three thumbscrews you may have noticed on the NAS’s back panel are our path inside:

Voila:

For orientation purposes, what you’re looking at here is the inside of the right-side shell, with the front of the NAS to the right in the photo:

And here are the now-exposed guts of the NAS, tipped over on its left side and looking down on the primary PCB mounted to the left side’s inside:

Here’s another perspective on the internal assembly, with the NAS still sideways:

And three more views, with the NAS back in its “normal” orientation. Top:

Bottom:

and front:

As it turns out, there are two PCBs in this design, the main one we’ve already caught a glimpse of, and another associated with the three SATA connectors at the back of the HDDs’ “cage” (I’ve briefly “jumped to the future” for the following shot, showing the “cage” already detached):

Back to the present moment. Detaching the “cage” involves removing seven screws, two each at the top and bottom:

And three more that normally mate with the back panel:

With them removed, all that’s left is to detach the two halves of the connection between the two PCBs:

and the “cage” (with PCB still attached) is now free:

Four more screws to go, to detach the PCB from the cage:

Mission accomplished:

Notice what looks like corrosion on this rectangular metal region?

Sorry for ruining the surprise, but this won’t be the last time you see it. I was unable to remove any of it with my fingernail, and trust me, the NAS was never exposed to moisture, so it’s not rust. I don’t know whether it’s an artifact of being lightning-zapped, or (my suspicion) just the outcome of long-term exposure to three heat-generating fast-spinning HDDs in a tiny enclosure.

The dominant IC at the bottom is unsurprising given the PCB’s function, an ASMedia ASM1062 PCI-to-SATA bridge and SATA controller. That said, I’m still somewhat surprised, because the ASM1062 supposedly only supports “two ports of Serial ATA 6Gbps”, but there are obviously three SATA connectors (therefore three SATA ports) in this design. Ideas, readers?

In the ASM1062’s lower left corner is a Macronix 25L4006E 4 Mbit serial interface (SPI, to be precise) NOR flash memory. Given the 25L4006E’s low capacity, not to mention its location on the other side of a PCI interface from the host CPU (whose heatsink you may have already glimpsed in a previous photo), I’m assuming that it only houses the firmware for the ASM1062, not the entire system. And no, it isn’t a NVM cache for the HDDs’ contents, either…

The other side of this PCB is comparatively unmemorable apart from a whole lot more of what looks like corrosion. Given that this side is more directly exposed to the heat coming off the HDDs, coupled with the fact that the HDDs remained fully functional after the NAS’s demise, my working theory as to the discoloration’s root cause (high temperatures) is seemingly bolstered.

Now for the main system PCB (look, more corrosion!):

Before diving in, here are some close-ups of the front while the PCB is still installed, showing the light pipes from the LEDs to the front panel, along with the USB3 port and switch assemblies:

In that earlier overview photo, you might have glimpsed five red marker-augmented (presumably to tip off the company to warranty-voiding owner removal) screw heads. Unfortunately, removing them didn’t enable the PCB to budge. But then I noticed a bulge in the warranty sticker in one corner:

Sneaky, QNAP. Very sneaky!

That further loosened the PCB, but I still couldn’t get it to fully detach from the metal bracket surrounding it, so I removed those four screws too:

Getting closer:

And finally, after disconnecting it from the zip cable-clustered multi-harness morass above it (which in retrospect may have been what kept it stuck in place after the initial six-screw removal process):

The PCB was finally free:

Before diving in, a brief diversion; let’s look more closely at the inside of the back panel, rotated 90° from its “normal” position in the images that follow. That’s the system fan to the left (duh) and the mounting bracket for the speaker to the right:

Remove the two screws that normally hold the mounting bracket in place:

And there’s your transducer!

Back to the PCB. There was, you may have already noticed from the earlier overview image, nothing of particular note on the backside…unless you’re into solder points (or corrosion patches), that is. The front side, however, was more interesting. Here’s the far-right end:

Top-to-bottom along the right edge, again, are the recessed reset switch, the mysterious “maintenance port”, an audio line-out jack, two RJ45 Gigabit Ethernet ports, side-by-side USB 2.0 and 3.0 connectors, and the power input. At the bottom left is the black-color connector, which originally mated with the SATA PCB. And the right-most two off-white colored ones above it go to the speaker (two-pin) and fan (four-pin). Curiously, as you may have already noticed, the other four-pin connector, directly above the upper right corner of the Faraday Cage, seems to be unused in this particular system design.

Speaking of the Faraday cage:

There’s another seemingly unused connector above it, eight-pin and black in color. And the IC in its upper left corner is where, I believe, the primary system firmware resides; it’s a Toshiba (now Kioxia) THGBMNG5D1LBAIL 4 GByte eMMC NAND flash memory module.

Shifting over once more to the left…

At far left is the earlier alluded-to PCB “buzzer”. Above it is a Weltrend Semiconductor WT61P803, which appears to be a microcontroller optimized for power management. Above that is another unpopulated four-pin connector. To the right of the buzzer is the RTC (aka, CMOS) battery (which, by the way, I confirmed post-NAS failure was still functional but swapped anyway, not that it helped…sometimes a dead battery can thwart a successful system start).

Let’s get that heatsink off, shall we? Needle-nose pliers did the trick:

The system CPU, a Realtek RTD1296 based on a 64-bit Arm Cortex-A53 four-core 1.4 GHz cluster, is now exposed to view.

And under the remainder of the Faraday cage:

are four Samsung K4A4g165We BCRC 4 Gbit DDR4-2400 SDRAMs, together comprising the NAS’s 2 GBytes of (non-expandable, obviously) system volatile memory:

I’ll close with a couple of PCB end shots:

and a premise, attempting to answer the fundamental question, “What caused the NAS to fail?” As I’ve mentioned in past coverage of the QNAP TS-328, this NAS doesn’t have a particularly stellar long-term reliability record; see, for example, this Reddit thread or this one, both of which are reminiscent of what I experienced. So, it may have just coincidentally chosen that point in time to expire, driven by long-term heat-induced failure of some component on the PCB, for example. But the chronological proximity to last summer’s lightning debacle is hard to ignore, given that it’d been reliably running for a few weeks shy of four years at that point.

I don’t think the DC power input was the failure point, as the PSU still seems fully functional (as I mentioned earlier). The only other thing physically connected to the NAS was its upper Gigabit Ethernet port; I’d wager that was the Achilles’ Heel, instead. Subsequent non-operation characteristics (a brief twitch of the system fan on each powerup attempt, for example) are past-history reminiscent to me of a PC whose CPU has gone awry. Fundamentally, after all, what is a NAS but a tailored-function, Arm- and Linux-based (in this case) computer? Although I’m unable to find a detailed datasheet on the Realtek RTD1296 online, the overview information I’ve dug up makes repeated mention of dual-port Gigabit Ethernet support, suggesting that, at minimum, the RTD1296 integrates the MAC, thereby providing the requisite failure path.

Agree or disagree with my premise? Anything else that jumps out at you from my dissection? Sound off with your thoughts in the comments!

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The post Analyzing a lightning-zapped NAS appeared first on EDN.

At the SID Display Week 2025 conference in San Jose, CA, USA (13–15 May), micro/nanotechnology R&D center CEA-Leti of Grenoble, France presented the paper ‘Co-Integration of Organic Photodetector with MicroLED Dedicated to Multifunctional Display Application’, representing a step toward multi-functional displays that combine both display and sensing capabilities...

US-based Raytheon (a business of aerospace & defense company RTX of Arlington, VA) has delivered the first AN/TPY-2 radar to the US Missile Defense Agency (MDA) with a complete gallium nitride (GaN)-populated array. The AN/TPY-2 is a missile defense radar that can detect, track and discriminate ballistic missiles in multiple phases of flight...

US-based Raytheon (a business of aerospace & defense company RTX of Arlington, VA) has delivered the first AN/TPY-2 radar to the US Missile Defense Agency (MDA) with a complete gallium nitride (GaN)-populated array. The AN/TPY-2 is a missile defense radar that can detect, track and discriminate ballistic missiles in multiple phases of flight...

The speed, efficiency and overall performance of any computing device are all measured by its CPU (central processing unit). A few of the most popular CPU brands, which have made unique inventions and contributed to market value, are headquartered in the USA. Below is an overview of the top 10 CPU brands in the USA, including their popular models.

1. Intel

The Santa Clara, California, headquartered semiconductor giant Intel was founded in 1968 and is framed for its powerful Core and Xeon processors that have enabled it to maintain a dominant market share.

Popular Model:

Intel Core i9 -14900k – 24 cores (8P+ 16E), 32 threads, boost clock up to 6.0 GHz, Intel Thread Director, PCle Gen 5 support.

Intel Core Ultra 9 285K – Processing with AI, 24 cores, 24 threads, 5.7 GHz boost clock, PCle Gen 5 support.

Intel Xeon W9-3495X – Workstation grade, 56 cores, 112 threads, high-performance computing.

2. AMD

AMD is short for Advanced Micro Devices, was founded in 1969 and has its corporate headquarters in Santa Clara, California. Its Ryzen and EPYC processors are favorites in high-performance computing and gaming.

Popular Model:

AMD Ryzen 9 9950X – 16 cores, 32 threads, 5.7 GHz boost, 3D V-Cache tech, PCle Gen 5 compatibility.

AMD Ryzen 7 9800X3D- 8 cores, 16 threads, 5.2GHz boost, tuned for game performance.

AMD EPYC 9754 – Server grade CPU, 128 cores, 256 threads, data center intent.

3. Qualcomm

Qualcomm is headquartered in San Diego, California and is a global leader in the mobile industry. Its Snapdragon CPUs are the brains of smartphones and tablets across the globe.

Popular Model:

Snapdragon 8 Gen 3 – ARM architecture, AI-optimized processing, 5G capabilities, Adreno GPU for visuals.

Snapdragon X Elite – 12 high-performance CPU core, AI-based computing, 45 Tops NPU performance.

Snapdragon 8cx Gen 4 – Engineered for Windows laptops, AI-driven efficiency, ultra-low power consumption.

4. Apple
   

Apple, based in Cupertino, California, develops its own in-house M-series processors such as the M3 Pro and M3 Max that drive MacBooks and Mac desktops. These chips are recognized for their seamless integrations with macOS, offering high performance, energy efficiency and advanced GPU capabilities optimized for creative and professional workloads.

Popular Models:

Apple M3 Pro – 12-core CPU, 18-core GPU, optimized for macOS.

Apple M3 Max – Up to 16 CPU cores, 40 GPU cores.

5. NVIDIA

NVIDIA has its headquarters in Santa Clara, California, USA. It was established in 1993 and has evolved into a worldwide leader in graphics processing units (GPUs), artificial intelligence (AI) hardware, high-performance computing and data center CPUs, such as the Grace Hopper and tegra families.

Popular Model:

NVIDIA Grace Hopper CPU – Server-class, AI processing

Tegra X1+ – Used in consoles such as Nintendo Switch

6. IBM

IBM, Armonk, New York is legacy tech titan famous for its enterprise-level processors, specifically in mainframes and high-performance computing. IBM POWER and z-series processors are very popular among data centers, cloud computing and AI workloads.

Popular Models:

IBM Power10 – 15-core, high security enterprise CPU

IBM z16 – Mainframe chip, for banking and analytics

7. Marvell Technology

Santa Clara, California, based Marvell Technology is a cloud-optimized and networking- centric CPU specialist with scalable ARM-based solutions like ThunderX3 and OCTEON for data centers.

Popular Models:

ThunderX3 – 96-core ARM CPU for data centers.

OCTEON 10 – 5nm AI-optimized networking chip.

8. SiFive

San Mateo, California- based SiFive is a top player in RISC-V architecture, with high-performance, customizable CPUs for many applications, such as embedded systems and data centers.

Popular Models:

Performance P670 – Efficient edge device RISC-V core with high performance

Intelligence X280 – AI inference processing for AI applications.

9. Ampere Computing

Santa Clara, California, based Ampere Computing creates ARM-based server processors such as Altra Max and AmpereOne, designed to provide performance along with power savings in contemporary clouds.

Popular Models:

Ampere Altra Max – 128-core ARM CPU

AmpereOne – Cloud-native CPU for next-generation systems

10. Tenstorrent

Austin, Texas, based Tentorrent is a high-performance and AI company that designs RISC-V CPUs and AI accelerators. It is headed by Jim keller, a highly acclaimed chip architect. The company is looking to transform AI computing by combining high-performance CPUs and AI accelertors.

Popular Models:

Wormhole & Black Hole – High throughput AI datacenter CPUs

 

Brand	Price Range
Intel	$460-$7,103
AMD	$519-$4,998
Qualcomm	$849-$1,598
Apple	$1,499-$2,899
NVIDIA	$42,500
IBM	$41,00-$135,300
Ampere Computing	$2,299-$5,000+

 

Conclusion:

Intel and AMD lead the CPU markets, with their extensive lines of processors designed to support gaming, professional use cases and business applications. Qualcomm leads the space for mobile computing with Snapdragon chips optimized for artificial intelligence-based computing. Apple uses a high-end pricing model for its M-series chips, optimized for integration in macOS. NVIDIA and IBM are also interested in high-performance computing, AI processing and enterprise-level solutions like Grace Hopper and Power10 CPUs. Marvell, SiFive, Ampere and Tenstorrent are new entrants dealing with cloud computing, AI acceleration and RISC-V architecture, but their pricing details for processors are limited.

The post Top 10 CPU Brands in USA appeared first on ELE Times.

Today’s system-on-chip (SoC) designs integrate unprecedented numbers of diverse IP cores, from general-purpose CPUs to specialized hardware accelerators, including neural processing units (NPUs), tensor processors, and data processing units (DPUs). This heterogeneous approach enables designers to optimize performance, power efficiency, and cost. However, it also increases the complexity of on-chip communication, synchronization, and interoperability.

At around the same time, the open and configurable RISC-V instruction set architecture (ISA) is experiencing rapid adoption across diverse markets. This growth aligns with rising SoC complexity and the widespread integration of artificial intelligence (AI), as illustrated in figure below. Nearly half of global silicon projects now incorporate AI or machine learning (ML), spanning automotive, mobile, data center, and Internet of Things (IoT) applications. This rapid RISC-V evolution is placing increasing demands on the underlying hardware infrastructure.

The above graph shows projected growth of RISC-V-enabled SoC market share and unit shipments.

NoCs for heterogeneous SoCs

A key challenge in AI-centric SoCs is ensuring efficient communication among IP blocks from different vendors. These designs often integrate cores from various architectures, such as RISC-V CPUs, Arm processors, DPUs, and AI accelerators, which adds to the complexity of on-chip interaction. So, compatibility with a range of communication protocols, such as Arm ACE and CHI, as well as emerging RISC-V interfaces like CHI-B, is critical.

The distinction between coherent networks-on-chip (NoCs), primarily used for CPUs that require synchronized data caches, and non-coherent NoCs, typically utilized for AI accelerators, must also be carefully managed. Effectively handling both types of NoCs enables the design of flexible, high-performance systems.

NoC architectures address interoperability and scalability. This technology delivers flexible interconnectivity, seamlessly integrating the expanding variety and number of IP cores. Approximately 10% to 13% of a chip’s silicon area is typically dedicated to interconnect logic. Here, NoCs serve as the backbone infrastructure of modern SoCs, enabling efficient data flow, low latency, and flexible routing between diverse processing elements.

Advanced techniques for AI performance

The rapid rise of generative AI and large language models (LLMs) has further intensified interconnect demands, with some now surpassing trillions of parameters and significantly increasing on-chip data bandwidth requirements. Conventional bus architectures can no longer efficiently manage these massive data flows.

Designers are now implementing advanced techniques like data interleaving, multicast communication, and multiline reorder buffers. These methods enable widened data buses with thousands of bits for sustained high-throughput and low-latency communication.

In addition to addressing bandwidth demands, new architectural approaches optimize system performance. One technique is AI tiling, where multiple smaller compute units or tiles are interconnected to form scalable compute clusters.

These architectures allow designers to scale CPU or AI-specific processing clusters from dozens to thousands of cores. The NoC infrastructure manages data movement and communication among these tiles, ensuring maximum performance and efficiency.

Beyond tiling, physical and back-end design challenges intensify at advanced nodes. Below 10 nanometers, routing and layout constraints significantly impact chip performance, power consumption, and reliability. Physically aware NoCs optimize placement and timing for successful silicon realization. Early consideration of these physical factors minimizes silicon respin risk and supports efficiency goals in AI applications at 5 nm and 3 nm.

Reliability and flexibility

Hardware-software integration, including RISC-V register management and memory mapping, streamlines validation, reduces software overhead, and boosts system reliability. This approach manages coherent design complexity, meeting performance and safety standards.

Next. safety certifications have become paramount as RISC-V-based designs enter safety-critical domains such as autonomous automotive systems. Interconnect solutions must deliver high-bandwidth, low-latency communication while meeting rigorous safety standards such as ISO 26262 up to ASIL D. Certified NoC architectures incorporate fault-tolerant features to enable reliability in AI platforms.

Modularity and interoperability across vendors and interfaces have also become essential to keep pace with the dynamic demands of AI-driven RISC-V systems. Many real-world designs no longer follow a monolithic approach.

Instead, they evolve over multiple iterations and often replace processing subsystems mid-development to improve efficiency or time to market. Such flexibility is achievable when the interconnect fabric supports diverse protocols, topologies, and evolving standards.

Andy Nightingale, VP of product management and marketing at Arteris, has over 37 years of experience in the high-tech industry, including 23 years in various engineering and product management positions at Arm.

 

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The post Boosting RISC-V SoC performance for AI and ML applications appeared first on EDN.

Researchers have developed an extremely thin, flexible imager that could be useful for noninvasively acquiring images from inside the body. The new technology could one day enable early and precise disease detection, providing critical insights to guide timely and effective treatment.

Picked up this DARPA translator today and busted it open to view the shiney bits submitted by /u/Normal-Gur-6432 [link] [comments]

build + demo: https://youtu.be/7fNYj0EXxMs submitted by /u/Dull-Pressure9628 [link] [comments]

WIN Semiconductors Corp of Taoyuan City, Taiwan — which provides pure-play gallium arsenide (GaAs) and gallium nitride (GaN) wafer foundry services for the wireless, infrastructure and networking markets — has announced the inclusion of microwave & millimeter-wave product firm Viper RF of Newton Aycliffe, UK in its WIN Alliance Program...

Infineon Technologies AG Munich, Germany is to supply silicon carbide (SiC) and silicon (Si) power modules from its HybridPACK Drive G2 family for traction inverters in the R2 platform of electric vehicle (EV) manufacturer Rivian Automotive Inc of Irvine, CA, USA. Supply is expected to start in 2026. Infineon will also supply other products for the platform, including AURIX TC3x micro-controllers and power management ICs. HybridPACK Drive is Infineon’s power module family for electric vehicles, with more than 10.5 million units sold since 2017...

Impact of ADC resolution and its reference

Engineers always want to get all they can from their circuits; this holds for analog-to-digital converters (ADCs). To maximize performance from an ADC, resolution is perhaps the primary spec to focus on. However, the sad fact is that we have defined the maximum single-read resolution once we pick the ADC and its reference. For example, let’s say we use a 10-bit ADC with a 5-V reference. This means that our reading resolution is 5 V / (1023) or 4.888 mV per digital step. But what if we had this ADC system and had to apply it to a sensor that had an output of 0 to 1 V? The ADC resolution stays at 4.888 mV, but that means there are only 1 V /4.888 ms, or ~205 usable steps, so in essence, we have lowered the sensor’s resolution to 1 part in 205.

What if we were designing a device to measure the voltage across an inductor when a DC step voltage is applied through a series resistor? You can see in the curve below (Figure 1), in the first couple of seconds we probably would get decent data point readings, but after that, many of the data points would have the same value since the slope is shallow. In other words, the relative error would be high.

Figure 1 Sample inductor voltage versus time curve for a circuit measuring the voltage across an inductor when a DC step voltage is applied through a series resistor. Note the flat slope after 3 seconds, which will increase the relative error of the measurement.

Wow the engineering world with your unique design: Design Ideas Submission Guide

There are two basic ways to change this:

• Change the ADC to one with more bits (such as 12, 14, or 16 bits) or,
• Change the ADC’s reference voltage.

(There are also more exotic ways to change resolution, such as using delta-sigma converters.) Changing the number of bits would mean an external ADC or a different microcontroller. So, what if we designed a system with an adjustable reference? This resolution could change automatically as needed—let’s call this adaptive resolution.

Adaptive resolution demo

Let’s look at an easy method first. The Microchip ATMEGA328P has three settings for the internal ADC reference: the Vcc voltage, an internal 1.1-V reference, and an external reference pin (REF). So, for demonstration, the simplest setup is to use an Arduino Nano, which uses the ATMEGA328P.

The demonstration uses one of the analog inputs, which can connect to a 10-bit ADC, to measure voltage or the sensor output. The trick here is to set the reference to Vcc (+5 V in this design) and take an ADC reading of the analog input.

If the reading, after being converted to a voltage, is greater than 1.1 V, use that value as your measurement. If it is not greater than 1.1 V, change the reference to the internal 1.1-V band-gap voltage and retake the reading. Now, assuming your sensor or measured voltage is slow-moving relative to your sample rate, you have a higher-resolution reading than you would have had with the 5-V reference.

Referring to our inductor example, Figure 2 illustrates how this adaptive resolution will change as the voltage drops.

Figure 2 Change in adaptive resolution using the Microchip ATMEGA328P’s internal ADC with either reference Vcc voltage of 5 V or internal reference of 1.1 V.

Adaptive resolution code

The following is a piece of C code to demonstrate the concept of adaptive resolution.

[An aside: As a test, I used Microsoft Copilot AI to write the basic code, and it did a surprisingly good job with good variable names, comments, and offered a clean layout. It also converted the ADC digital to the analog voltage correctly. As I was trying to get Copilot to add some logic changes, it got messier, so at that point, I hand-coded the modifications and cleanup.]

// Define the analog input pin const int analogPin = A0; // Variable to store the reference voltage (in mV) const float referenceVoltage5V = 4753.0; // Enter the actual mv value here const float referenceVoltage1p1V = 1099.0; // Enter the actual mv value here // Types and variable to track reference state enum ReferenceState {Ref_5, Ref_1p1}; ReferenceState reference = Ref_5; void setup() { // Initialize serial communication at 9600 bits per second Serial.begin(9600); // Set the analog reference to 5V (default) analogReference(DEFAULT); reference = Ref_5; // Set reference state } void loop() { int sensorValue = 0; int junk = 0; float voltage = 0; sensorValue = analogRead(analogPin); // Take a reading using the current reference if (reference == Ref_5) { voltage = (sensorValue / 1023.0) * referenceVoltage5V; //Convert reading if (voltage < 1100) { // Check if the voltage is less than 1.1V // Change the ref voltage to 1.1v and take a new reading analogReference(INTERNAL); // Set the analog reference to 1.1V (internal) reference = Ref_1p1; // Set reference state junk = analogRead(analogPin); // Take a throw-away read after ref change sensorValue = analogRead(analogPin); // Take a new reading using 1.1v ref voltage = (sensorValue / 1023.0) * referenceVoltage1p1V; //Convert reading } } else // Reference is currently set to 1.1v voltage = (sensorValue / 1023.0) * referenceVoltage1p1V; //Convert reading if (sensorValue == 1023) { // Check if the ADC is at maximum (>= 1.1v) // Voltage is 1.1 volts or greater, so change to 5v ref and reread analogReference(DEFAULT); // Set the analog reference to 5V (default) reference = Ref_5; // Set reference state junk = analogRead(analogPin); // Take a throw-away read after reference change sensorValue = analogRead(analogPin); // Take a reading using the 5v reference voltage = (sensorValue / 1023.0) * referenceVoltage5V; //Convert reading } // Print the analog value and voltage to the serial monitor if (reference == Ref_5) Serial.print("Analog value with 5V reference: "); else Serial.print("Analog value with 1.1V reference: "); Serial.print(sensorValue); Serial.print(", Voltage: "); Serial.println(voltage / 1000,4); // Delay for a moment before the next loop delay(1000); }

This code continuously reads the ADC connected to analog pin A0. It starts by using Vcc (~5 V) as the reference for the ADC. If the reading is less than 1.1 V, the ADC reference is switched to the 1.1-V internal reference. This reference is continued to be used until the ADC returns its maximum binary value of 1023, which means the A0 voltage must be 1.1 V or greater. So, in this case, the reference is switched to Vcc again. After taking a valid voltage reading, the code prints the reference value used along with the reading.

The 5 V and 1.1 V references must be calibrated before use to get accurate readings. This should be done using a reasonably good voltmeter (I used a calibrated 5½ digit meter). These measured voltages can then be entered into the code.

Note that towards the top of the code, the 5-V reference voltage variable (“referenceVoltage5V”) is set to the actual voltage as measured on the REF pin of the Arduino Nano, when the input on A0 is greater than 1.1 V. The 1.1-V reference voltage variable (“referenceVoltage1p1V”) should also be set by measuring the voltage on the REF pin when the A0 voltage is less than 1.1 V. Figure 3 below illustrates this concept.

Figure 3 This code continuously reads the ADC connected to analog pin A0. If A0 voltage < 1.1 V, the ADC reference is switched to 1.1 V. If A0 > 1.1 V, the ADC reference is switched to Vcc.

Relative error between 1.1 V and 5 V references

A few pieces of data showing the improvement of this adaptive resolution are as follows: Around 1.1-V, the 5-V referenced reading can have a resolution error of up to 0.41% while the 1.1-V reference reading can have up to a 0.10% error. At 100 mV, a reading that references 5 V could have up to a 4.6% error, while a 1.1-V referenced reading may have up to a 1.1% error. When we reach a 10-mV input signal, the 5 V reference may err by 46% while the 1.1 V reference reading will be 10.7% or less.

Expanding reference levels External DAC method

If needed, this concept could be expanded to add more levels of reference, although I wouldn’t go more than 3 or 4 levels on a 10-bit ADC due to diminishing returns. The following are a few examples of how this could be done.

The first uses a DAC with its own reference tied to the Nano’s REF pin. The DAC controlled by the Nano could then be adjusted to give any number of reference values. An example of such a DAC is the MAX5362 DAC with I2C control (although its internal reference is 0.9xVcc, so the max reading would be roughly 4.5 V). In this design, the Nano’s REF pin would be set to “EXTERNAL.” See Figure 4 below for more clarity.

Figure 4 Using an external DAC (MAX5362) controlled by the Arduino Nano to provide more reference levels.

Nano’s PWM output method

Another way to create multiple reference voltages could be by using the Arduino Nano’s PWM output. This would require using a high-frequency PWM and very good filtering to obtain a nice flat DC signal, which is proportional to the 5-V reference value. You would want a ripple voltage of about 1 mV (-74 dB down) or less to get a clean, usable output. The outputs would also need to be measured to calibrate it in the code. This technique would require minimal parts but would give you many different levels of reference voltages to use. Figure 5 shows a block diagram of this concept.

Figure 5 Using the Arduino Nano’s PWM output and a lowpass filter to obtain the desired DC signal to use as a voltage reference.

Resistor ladder method

Another possibility for an adjustable reference is using a resistor ladder and an analog switch to select different nodes in the ladder. Something like the TI TMUX1204 may be appropriate for this concept. The resistor ladder values can be selected to meet your reference requirements. Figure 6 shows that two digital outputs from the Nano are also used to select the appropriate position in the resistor ladder.

Figure 6 Using a resistor ladder and an analog switch, e.g., TI TMUX1204, to select different nodes on the ladder to generate tailored voltage reference values.

You get the idea

There are other ways to construct the reference voltages, but you get the idea. The bigger picture here is using multiple references to improve the resolution of your voltage readings. This may be a solution looking for a problem, but isn’t that what engineers do—match up problems with solutions?

Damian Bonicatto is a consulting engineer with decades of experience in embedded hardware, firmware, and system design. He holds over 30 patents.

Phoenix Bonicatto is a freelance writer.

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The post Adaptive resolution for ADCs appeared first on EDN.

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Conclusion:

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The post Redefining Semiconductor Excellence: India Sets the Stage with 3nm Designs appeared first on ELE Times.

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