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Nvidia’s CEO Jensen Huang has made waves by saying that his company’s most advanced artificial intelligence (AI) chip, Blackwell, will transition from CowoS-S to CoWoS-L advanced packaging technology. That also shows how TSMC’s advanced packaging technology—chip on wafer on substrate (CoWoS)—is evolving to overcome interconnect battles inside large, powerful chips for AI and other high-performance computing (HPC) applications.

The CoWoS-S advanced packaging technology uses a single silicon interposer and through-silicon vias (TSVs) to facilitate the direct transmission of high-speed electrical signals between the die and the substrate. However, single silicon interposers often confront yield issues.

On the other hand, CoWoS-L, TSMC’s latest packaging technology, uses a local silicon interconnect (LSI) along with an RDL interposer to form a reconstituted interposer (RI) to enhance chip design and packaging flexibility. It also preserves the attractive feature of CoWoS-S in the form of TSVs while mitigating the yield issues arising from the use of large silicon interposers in CoWoS-S.

According to Reuters, Nvidia is selling its Blackwell chips as quickly as TSMC can manufacture them, but packaging has become a bottleneck due to capacity constraints. That’s startling because, as Huang noted, the amount of advanced packaging capacity at TSMC is probably four times the amount available less than two years ago.

Figure 1 CoWoS-L marks a significant advancement over CoWoS-S in terms of performance and efficiency for AI and HPC applications. Source: TSMC

Huang also told Taiwanese reporters that Nvidia is still producing Blackwell’s predecessor, Hopper, using TSMC’s CoWoS-S advanced packaging technology. “It’s not about reducing capacity. It’s actually increasing capacity into CoWoS-L.”

Advanced packaging in flux

Nvidia’s foray into new technology is a stark reminder of how quickly advanced packaging needs are changing. Apparently, the semiconductor industry is eying a new set of advanced packaging building blocks to dramatically increase the bandwidth and interconnect density of AI chips.

TSMC’s CoWoS is a 2.5D semiconductor packaging technology that increases the number of I/O points while reducing interconnect length between logic and memory components. However, emerging HPC workloads, particularly those related to AI training, demand even higher memory bandwidth due to frequent memory accesses.

CoWoS-L can stack up to 12 HBM3 devices at a lower cost than CoWoS-S and thus has the potential to become the mainstream CoWoS technology for future AI chips. Beyond CoWoS-L, TSMC is warming up to co-packaged optics (CPO), which replaces traditional electrical signal transmission with optical communications.

Figure 2 TSMC has made significant progress in its silicon photonics strategy by integrating CPO with advanced semiconductor packaging. Source: TrendForce

The current AI chips use copper interconnects, which increasingly face bottlenecks as bandwidths widen. In CPO, optical interconnect signals can achieve higher bandwidth than their electrical counterparts. For instance, CPO supports up to 1.6 Tbps bandwidth, which is 1.8 times wider than Gen 4 NVLink interconnect used by Nvidia in its current GPUs. Moreover, power consumption is also up to 50% lower.

According to Taiwanese media outlet UDN, TSMC has completed the development of CPO, and it plans to provide CPO samples to two of its major customers, Broadcom and Nvidia, later this year. Furthermore, UDN reports that TSMC plans to scale up the production of CPO in 2026.

AI chips constituting high logic-to-logic and logic-to-memory bandwidth are driving innovations in the advanced packaging realm. The move from CoWoS-S to CoWoS-L and the advent of CPO are harbinger of this pivot in the semiconductor industry ecosystem, which is now increasingly driven by AI applications.

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