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Since i'm planning to build a bigger batch of USBpwrMe i actually need to test each unit in a fast and repeatable way. Therefore i have designed a test jig that will measure all functions. There are 2 voltage regulators that will supply the test jig itself with 5V but also a 6V regulator to be able to make a test of an over voltage circuit with a threshold of 5.6-5.7V. INA139 will monitor the current of the DUT thru a shunt of 0.5 ohm or less. This will be optimized depending on what the DUT will actually consume. On the test jig board a PIC Mcu will control and manage the whole test and test instructions and results will be presented on a 2x16lcd display. The test is not high tech but the DUT must be manipulated with external resistors and voltages to be tested. This is mostly handled by 3 relays. Connection to the DUT will be easy using the banana connectors and the USB outputs which has corresponding mating connectors on the test jig. Following steps will be performed 1 It will measure the current consumption of the board to see if there is excessive power consumption 2 It will change polarity on the DUT and measure if there is any voltage on the output. 3 It will will apply resistors on the D+ and D- lines och the USB-A connector and measure so that expected voltage appears. 4 It will apply resistors on the CC1 and CC2 line for the USB-C connector. Vbus1, Vbus2, CC1 and CC2 are measured. If negotiation is correct it will enable Vbus. 5 It will change input voltage from 5V to 6V and test so that the OVP protection works. 6 Finally it will test the OVP mode switch by telling user to turn of OVP. And measures that Vbus goes on. The test will hopefully test a unit under 5s. The Gerber files are already sent to manufacturer and are in production. Now you might wonder why a choose a to small board that won't fit the display. Well at first i did. And when i uploaded the gerbers files it was around 40Usd to get it manufactured and shipped. By reducing the height of the board with 3cm the cost was 12Usd. Since it's only a testjigg and will be put into a casing i rather save some money!!! The PCB has 4 layer stack up. Not really needed but it's much easier to route the signals and takes less time. The schematic and routing took around 5hours. Funny thing is that the test jig is way more advanced than the product it is itended to test :) :) submitted by /u/KS-Elektronikdesign [link] [comments]

Photonic application-specific integrated circuit (PASIC) chip designer and manufacturer OpenLight of Goleta, near Santa Barbara, CA, USA (which launched as an independent company in June 2022, introducing the first open silicon photonics platform with heterogeneously integrated III-V lasers, modulators, amplifiers and detectors) has announced sample availability of its first heterogeneously integrated silicon photonics-based 3.2T DR8 photonic integrated circuit (PIC)...

For fourth-quarter 2025, epitaxial deposition and process equipment maker Veeco Instruments Inc of Plainview, NY, USA has reported revenue of $165m, down 9.4% on $182.1m a year ago but roughly flat on Q3/2025’s $165.9m...

Photonic application-specific integrated circuit (PASIC) chip designer and manufacturer OpenLight of Goleta, near Santa Barbara, CA, USA (which launched as an independent company in June 2022, introducing the first open silicon photonics platform with heterogeneously integrated III-V lasers, modulators, amplifiers and detectors) has announced the first volume production orders by a customer on its PH18DA indium phosphide (InP) on silicon photonic platform, developed in collaboration with specialty analog foundry Tower Semiconductor Ltd of Migdal Haemek, Israel. Based on NewPhotonics 800G and 1.6T laser-integrated photonic integrated circuit (PIC) solution, this marks a step towards bringing highly integrated, laser-enabled photonic ICs into high-volume production for AI and hyperscale data-center networks...

У КПІ ім. Ігоря Сікорського розпочав роботу уповноважений підрозділ з питань запобігання та виявлення корупції kpi пт, 03/20/2026 - 15:19

It was with humble spirit and a good dose of Mea Culpa that a semiconductor company, from whom some very large-scale digital large-scale integration (LSI) chips were purchased, had a problem (later corrected, thank goodness) in that their chips would malfunction when powering up if their +5V rail voltage rose too slowly as the system was being turned on.

The vendor’s recommendation was to apply a 0 V (off) to +5 V (on) rail voltage with a steeper rise time (< 45 ms) than our power supply could deliver. We decided that we needed a switching arrangement that would operate as follows in Figure 1.

Figure 1 Providing a steep +5-V rail voltage rise time. 

One problem with making something like this was that the input voltage could indeed rise very slowly through ½ volt to 1 volt to 2 volts, and so forth, which were voltage levels that were well below specification limits for any voltage monitoring IC we could find.

The resulting operations were erratic and unpredictable at arbitrarily low input voltages. This did not help the LSI situation even one little bit. (Yes, I am aware of the pun.)

Remedy was achieved using the following circuit in Figure 2. 

Figure 2 Rail voltage switch, four loads.

The result obtained was as follows:

Figure 3 Rail voltage delay and rise time speedup.

This worked predictably down to arbitrarily low power supply voltages because there would be no response whatsoever, as long as the TLV431 didn’t see some voltage high enough to get itself conducting.

When the power supply voltage did get high enough to turn on the TLV431 at the time we’re calling “t1”, the power MOSFETs would turn on, and there would be a downward but very short-duration transient voltage drop from the power supply, which would be recovered from very quickly. The rail voltage thus presented to the LSI chips had a sufficiently quick rise time of its own to make those chips happy.

The end result made a bunch of human beings happy, too.

John Dunn is an electronics consultant and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

Related Content

• Silly Simple Supply Sequencing
• Power-Supply Sequencing for Low-Voltage Processors
• Shunt Regulator Eases Power-Supply Start-Up Woes
• Use a TL431 Shunt Regulator to Limit High AC Input Voltage
• Fundamentals of Designing with MOSFET Power Switches

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The Electronic Industries Association of India (ELCINA), India’s leading association of electronics manufacturers, welcomes the Government’s announcement of the Bharat Audyogik Vikas Yojana (BHAVYA) scheme, with a Rs. 33,600 crore outlay, aimed at developing India’s industrial manufacturing ecosystem. The BHAVYA scheme would support India’s transformation into a globally competitive, self-reliant electronics, components, and semiconductor ecosystem.

Welcoming the BHAVYA scheme, Rajoo Goel, Secretary General, ELCINA, said: “The Government has announced the BHAVYA scheme at an opportune time and stands to significantly strengthen the ecosystem and the value chain. Through cluster-based promotion, BHAVYA can co-locate OEMs, component suppliers, logistics providers, and service providers within the same industrial park, which is exactly what a deeper ecosystem for electronics and semiconductors requires. At ELCINA, we are excited to see how this scheme will transform the industry over the next few years.”

ELCINA President, Dr Sasikumar Gendham, lauded the scheme as “it would complement the EMC Schemes of MeitY under which several Electronics Manufacturing Clusters had been initiated and industries set up. BHAVYA would catalyse this further and suggested that existing Clusters should also be allowed to benefit from the Scheme and enhance their infrastructure further”.

The plug-and-play industrial ecosystems will help industry players – both existing and new – cut down on the setup phase and move more quickly towards production. Additionally, with streamlined approvals, effective single-window systems, and investor-friendly reforms led by states, the industry would be in a better position to address the critical need to reduce import dependence and position the country as a credible export and supply-chain hub.

ELCINA also lauds the Government’s broader goals of job creation, investment, and economic growth across states. BHAVYA is expected to enhance the supply chain while creating new opportunities for Indians who stand to benefit from the country’s manufacturing growth, particularly in the electronics sector.

The post Government’s Rs. 33,600 crore BHAVYA Scheme Strengthens India’s Electronics, Components, Semiconductor Manufacturing Industries: ELCINA appeared first on ELE Times.

Part 1 of this article series on gallium nitride (GaN) fundamentals described crystal structures and the formation of the two-dimensional electron gas (2DEG), along with material figures of merit and the transition from depletion-mode to enhancement-mode GaN HEMTs.

Part 2 will outline hybrid structures and the RDS(on)  penalty, as well as provide further details on GaN HEMTs and substrate choices for GaN. It will also make the case for the path to monolithic integration while showing how ohmic contacts, metallization, and packaging advantages are facilitating this design roadmap.

Figure 1 Schematic of low-voltage enhancement-mode silicon MOSFET is shown in series with a depletion-mode GaN HEMT: Cascode circuit (a) and enable/direct-drive circuit (b). Source: Efficient Power Conversion (EPC)

An alternative to monolithic enhancement-mode GaN transistors is the hybrid cascode configuration, pairing a low-voltage enhancement-mode silicon MOSFET with a high-voltage depletion-mode GaN HEMT in series. Figure 1 above illustrates two variants.

The cascode configuration, in particular, is highlighted as a pragmatic intermediate solution: a low-voltage enhancement-mode Si MOSFET is connected in series with a high-voltage d-mode GaN HEMT. The MOSFET gate is the external control terminal; when it turns on, the GaN gate-source is pulled close to zero and the HEMT conducts. When the MOSFET turns off, the GaN gate sees a negative bias through the MOSFET, turning off the high electron mobility transistor (HEMT) and providing normally-off behavior at the system level.

A natural question is how much extra RDS(on) the silicon MOSFET adds to the GaN device. Figure 2 shows a useful plot of the percentage contribution of the MOSFET to total RDS(on) versus the rated voltage of the cascode system. At high voltage, the GaN device dominates, and the MOSFET contribution becomes small.

Figure 2 Percentage RDS(on) contribution from the low-voltage MOSFET in a cascode configuration is shown as a function of the rated breakdown voltage of the composite device. Source: Efficient Power Conversion (EPC)

From this chart, a 600-V cascode device adds only around 3% extra RDS(on) due to the low-voltage MOSFET, because the GaN HEMT’s drift resistance dominates at such high voltage. At lower voltages, the GaN device resistance drops rapidly with VBR, so the MOSFET contribution becomes increasingly significant. For this reason, cascode solutions are practical and attractive for higher voltages (above roughly 200 V), whereas for 100–150 V class devices, monolithic e-mode GaN is generally preferable.

The direct-drive (enable) variant exposes the depletion-mode GaN gate directly to the external driver (typically 0 V on, -12 to -14 V off). The silicon MOSFET serves as a safety “enable” switch, connected to the gate driver’s undervoltage lockout (UVLO). During normal operation, the silicon device remains on and experiences no switching; it only blocks the GaN gate if supply fails. This configuration offers precise control of GaN dynamics but requires bipolar drive capability.

Reverse conduction in HEMT transistors

Reverse conduction behavior is a clear advantage of enhancement-mode GaN HEMTs. The source potential increases in relation to the gate when current is forced from the source to drain while the device is nominally off.

This process continues until the threshold condition for the formation of 2DEG is reached beneath the gate region. The channel now reorganizes and conducts in the opposite direction. Unlike the body diode of a silicon MOSFET, which depends on minority-carrier injection and storage, this is a majority-carrier mechanism. So, there is no stored minority charge and consequently no reverse-recovery penalty.

A positive gate voltage establishes the 2DEG channel during forward conduction, enabling current to move from the drain to the source. When reverse conduction occurs, as it does during a synchronous rectifier’s dead time, current moves from the source to the drain when the drain is at least the threshold voltage lower than the gate.

Conduction is then determined by channel resistance, and the device functions similarly to a low-drop diode. In contrast to silicon MOSFETs, which suffer reverse-recovery losses because of charge storage effects, current almost immediately stops once the reverse bias is eliminated.

Vertical GaN and substrate choices

Instead of using lateral 2DEG transport, vertical GaN transistors employ a conduction path perpendicular to the wafer surface. In a typical structure, p-GaN regions linked to the source extend from the surface toward the drain, and the drain contact is positioned at the bottom of a thick n-GaN drift region. When a negative gate voltage is applied, the n-GaN between the p-regions beneath the gate is depleted, preventing current flow.

The depleted region collapses and electrons move vertically from source to drain when the gate is positively biased. This architecture has the potential to compete with high-voltage SiC devices because it can support breakdown voltages above 1000 V while maintaining quick switching. The sub-650 V market is dominated by lateral GaN, mainly because silicon substrates are more affordable and scalable.

The cost of standard 200-mm silicon wafers is only a few tens of dollars per wafer, which enables direct reuse of established CMOS fabs and high-volume manufacturing, including the potential for monolithic integration of sensing circuits and drivers. Bulk GaN substrates for vertical devices, on the other hand, are still restricted to small diameters (usually ≤150 mm) and cost several hundred to over a thousand dollars per wafer, or tens of dollars per cm². This severely limits cost competitiveness at mid voltages.

From a performance perspective, lateral GaN HEMTs benefit from the creation of a high-density 2DEG, which offers exceptionally high electron mobility and low channel resistance. This translates into excellent light-load efficiency and high-frequency operation, which are essential for applications like DC-DC converters, server power supplies, telecom, and consumer fast chargers.

Vertical architectures, currently dominated by SiC MOSFETs, continue to be the preferred solution for voltages above ~900 V because they provide superior robustness at high electric fields and decouple blocking voltage from lateral device dimensions. While SiC and future vertical GaN aim for high-voltage applications, lateral GaN emphasizes cost-performance optimization over voltage scaling in this regime, solidifying its leadership in the mid-voltage range.

Building a GaN HEMT transistor

Fabrication of a GaN HEMT begins with epitaxial growth of the GaN/AlGaN heterostructure on a foreign substrate. Unlike silicon devices, where the active layer matches the substrate, GaN HEMTs require heteroepitaxy, growing a wurtzite crystal on a substrate with mismatched lattice constant and thermal expansion.

Four substrate materials dominate: bulk GaN, sapphire (Al₂O₃), silicon carbide (SiC), and silicon (Si). Each offers trade-offs in lattice mismatch, thermal expansion coefficient, thermal conductivity, and cost. Silicon (111) orientation substrates have emerged as the commercial workhorse due to their low cost ($1–2 per 200 mm wafer) and compatibility with existing CMOS fabrication infrastructure, despite a 17% lattice mismatch (a_GaN = 3.189 Å vs. a_Si = 3.84 Å) and thermal expansion difference of 3 × 10⁻⁶ K⁻¹.

Heteroepitaxy grows one crystal on a dissimilar substrate. Metal-organic chemical vapor deposition (MOCVD) deposits the GaN/AlGaN layers. The process starts with an AlN seed layer on the substrate to initiate nucleation. An AlGaN buffer layer creates the transition to pure GaN crystal structure. A thick GaN layer forms the semi-insulating base. Finally, a thin AlGaN barrier layer induces strain that forms the 2DEG conduction channel.

Figure 3 illustrates the complete epitaxial stack from substrate to 2DEG interface. For enhancement-mode devices, a p-GaN cap layer grows atop the AlGaN barrier, introducing positive charge to deplete the 2DEG at zero gate bias (Figure 4). This stack enables lateral electron transport parallel to the surface, distinguishing GaN HEMTs from vertical silicon MOSFETs.

Figure 3 The illustration highlights basic steps involved in creating a GaN heteroepitaxial structure: Starting silicon substrate (a), aluminum nitride (AlN) seed layer grown (b), various Al GaN layers grown to transition the lattice from AlN to GaN (c), GaN layer grown (d), and AlGaN barrier layer grown (e). Source: Efficient Power Conversion (EPC)

Figure 4 An additional GaN layer, doped with p-type impurities, can be added to the heteroepitaxy process when producing an enhancement-mode device. Source: Efficient Power Conversion (EPC)

Ohmic contacts and metallization

Source and drain electrodes must form low-resistance ohmic contacts to the 2DEG, penetrating the AlGaN barrier. Multiple metal layers and high-temperature annealing create reliable shunts. The gate electrode sits atop the AlGaN (or p-GaN), modulating the channel via electric field.

Back-end processing adds multilevel copper interconnects with tungsten vias, scaling gate width across thousands of parallel cells. Final passivation (SiNₓ) protects the surface and shapes electric fields to prevent premature breakdown.

Chip-scale packages (BGA and LGA) minimize parasitics, supporting megahertz switching with minimal ringing. Recent advances in QFN (Quad, Flad, No-Lead) have brought packaging alternatives that have minimal compromises in parasitic inductance, resistance, and thermal conductivity.

In either chip-scale of QFN packages, lateral conduction enables bottom-side cooling and ultra-low inductance packaging. Ball grid array (BGA) formats use SnAgCu micro-bumps (150 µm pitch) for 100–650 V devices (1.5 × 1.0 mm² footprint). LGA variants (3.9 × 2.6 mm²) handle 100 V half-bridges at 10 A continuous. Package loop inductance drops below 0.2 nH, supporting dI/dt >2000 A/µs without significant ringing—impossible in wire-bonded discrete packages

The path to monolithic integration

The lateral architecture of GaN HEMTs—where current flows parallel to the surface—eliminates the need for deep vertical vias or trenches, enabling unprecedented levels of monolithic integration. Unlike vertical silicon or SiC devices, multiple passive and signal-level transistors and passive components occupy the same epitaxial plane, with interconnects formed in overlying metal layers. This allows fabrication of complete power stages on a single die smaller than a grain of rice.

Figure 5 A typical process creates solder bars on an enhancement-mode GaN HEMT (not to scale). Source: Efficient Power Conversion (EPC)

Monolithic GaN stages eliminate interconnect parasitics that plague discrete implementations:

• No bond wires: Package inductance <0.2 nH vs. 1–5 nH with discrete multi-chip QFN
• Zero common source and gate loop inductance
• Pin count reduction: 99% fewer external connections vs. discrete half-bridge + drivers

Compared to silicon DrMOS (driver + MOSFET), GaN integration yields:

• 10× lower QG → MHz switching without excessive gate losses
• Zero QRR → no reverse recovery in synchronous rectification
• 25× smaller die area → lower cost at equivalent performance

Maurizio Di Paolo Emilio is director of global marketing communications at Efficient Power Conversion (EPC), where he manages worldwide initiatives to showcase the company’s GaN innovations. He is a prolific technical author of books on GaN, SiC, energy harvesting and data acquisition and control systems, and has extensive experience as editor of technical publications for power electronics, wide bandgap semiconductors, and embedded systems.

Editor’s Note:

The content in this article uses references and technical data from the book GaN Power Devices for Efficient Power Conversion (Fourth Edition) authored by Alex Lidow, Michael de Rooij, John Glaser, Alejandro Pozo Arribas, Shengke Zhang, Marco Palma, David Reusch, Johan Strydom.

Related Content

• SiC vs. GaN: Who wins
• The advantages of Vertical GaN Technology
• A brief history of gallium nitride (GaN) semiconductors
• A new IDM era kickstarts in the gallium nitride (GaN) world
• New GaN Technology Makes Driving GaN-Based HEMTs Easier

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HENSOLDT of Taufkirchen near Munich, Germany (which develops sensor solutions, electronics and software for the air, land, sea, cyber and space domains) has signed a long-term supply agreement with United Monolithic Semiconductors GmbH (UMS, which designs and produces RF and millimeter-wave components and ICs at its facilities in Villebon sur Yvette, France and Ulm, Germany). By 2030, UMS will supply a total of 900,000 gallium nitride components for HENSOLDT radars...

The University of Warwick has secured new funding to boost the UK’s ability to test the reliability of advanced semiconductors used in electric vehicles, renewable energy, and other critical technologies...

Партнерство із юридичною компанією «Мережа Права» kpi пт, 03/20/2026 - 10:12

The UK Semiconductor Centre (UKSC) has welcomed a new £6.6m investment from the UK Government Department for Science, Innovation and Technology (DSIT) to bolster the county’e core strengths in semiconductor innovation...

Blue Moon Metals Inc of Toronto, ON, Canada has agreed to acquire the Gage Project in Washington County, Southern Utah, USA, from a subsidiary of Liberty Gold Corp in exchange for 420,935 common shares of Blue Moon and a 2.0% net smelter return royalty (NSR) on certain concessions...

The post Microchip Announces New BZPACK mSiC Power Modules with HV-H3TRB Reliability Standards appeared first on ELE Times.

submitted by /u/SaintLuke1 [link] [comments]

Efficient Power Conversion Corp (EPC) of El Segundo, CA, USA — which makes enhancement-mode gallium nitride on silicon (eGaN) power field-effect transistors (FETs) and integrated circuits for power management applications — has released its Phase 18 Reliability Report, providing new insights into eGaN device reliability. ..

Wolfspeed Inc of Durham, NC, USA — which makes silicon carbide (SiC) materials and power semiconductor devices — has entered into separate, privately negotiated subscription agreements with investors pursuant to which it will place (i) $379m of its 3.5% convertible 1.5 lien senior secured notes due 2031 and (ii) 3,250,030 shares of common stock at a purchase price of $18.458 per share, and pre-funded warrants to purchase up to 2,000,000 shares of common stock at a price of $18.448 per pre-funded warrant. The issuance and sale of the notes, shares and fre-Funded warrants is expected to settle on 26 March, subject to customary closing conditions. Funds managed by new and existing investors participated in these private placements...

A DC/DC power delivery board from Navitas Semiconductor enables direct conversion from 800 V to 6 V in a single stage. Showcased at NVIDIA GTC 2026, the design eliminates the conventional 48-V intermediate bus converter stage within compute server trays, simplifying power delivery for NVIDIA AI infrastructure.

Using GaNFast power ICs, the board reaches 96.5% peak efficiency at full load with 1-MHz switching and a power density of 2.1 kW/in³. The primary side integrates sixteen 650-V GaNFast FETs in DFN 8×8 packages with dual-side cooling in a stacked full-bridge topology, while center-tapped outputs use 25-V silicon MOSFETs. High-frequency switching enables smaller passives and planar magnetics, increasing power density.

The Navitas power delivery board is about 20% thinner than a mobile phone. Its ultra-low profile allows close placement to the GPU board, minimizing loop inductance to improve transient response and power distribution efficiency.

For more information, contact a Navitas representative or email info@navitassemi.com. A timeline for availability was not provided at the time of this announcement.

Navitas Semiconductor 

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The ST64UWB family of ultra-wideband SoCs from ST provides increased range and processing capability for automotive applications. Backward compatible with IEEE 802.15.4z, the chips also support the emerging IEEE 802.15.4ab UWB standard, enabling device localization and tracking at distances of several hundred meters. Target use cases include hands-free digital keys and high-accuracy vehicle localization.

Enhancements such as multi-millisecond ranging (MMS) and narrow-band assistance (NBA) provide greater operating range and improve link robustness, particularly for devices carried in bags or rear pockets. These features also facilitate close-range direction finding for more accurate interpretation of user position and movement. In addition, IEEE 802.15.4ab strengthens radar mode for more reliable in-vehicle child presence detection.

The ST64UWAB-A100 and ST64UWB-A500 are built on an 18-nm FD-SOI process, increasing link budget by nearly 3 dB versus bulk technologies and boosting range by up to ~50% beyond IEEE 802.15.4ab. Both devices integrate an Arm Cortex-M85 core, while the ST64UWB-A500 adds AI acceleration and DSP capabilities for edge AI-based radar applications. A third device, the ST64UWB-C100, expands the lineup to cover industrial and consumer applications.

The devices are now sampling to leading Tier 1 suppliers and OEMs.

ST64UWB product page 

STMicroelectronics

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Semtech’s 224-Gbps/lane TIAs and drivers power 800G–3.2T transceivers and optical engines for AI/ML clusters, hyperscale data centers, and cloud infrastructure. Compliant with CEI‑224G‑Linear and LPO‑MSA, they support half-retimed (LRO), linear pluggable (LPO), next‑gen (XPO), near‑packaged (NPO), and co‑packaged (CPO) optics.

The 224G TIA family—GN1834L, GN1834DL, and GN1838DL—offers quad- and octal-channel architectures with flexible layouts. On-chip equalization, high linearity, and low noise boost signal integrity for LPO and next-generation linear optics.

The 224G Mach-Zehnder Modulator (MZM) drivers—quad GN1877 and octal GN1887—support SiPho, InP MZM, and TFLN optical transmitters with tunable gain and output swing. A CEI‑224G‑Linear host-side equalizer covers a wide range of host interfaces, from compact NPO/CPO to varied LRO/LPO/XPO trace lengths.

Both the TIA and driver series integrate real-time link monitoring and telemetry, enabling proactive diagnostics to reduce link flapping and improve network reliability.

The GN1834L, GN1834DL, and GN1887 are available now; GN1838DL and GN1877 are expected in April 2026.

For more information, visit Semtech’s optical page.

Semtech

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