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Efinix offers the Sapphire RV64, a configurable 64-bit RISC-V soft SoC optimized for the company’s Trion and Titanium FPGAs. The SoC incorporates a cached RISC-V processor core and optionally includes a DDR DRAM controller interface. It also supports a range of peripherals. 

Sapphire RV64 is designed for embedded and edge AI applications that require more addressable memory, cache, and I/O capability than 32-bit cores can provide while still demanding the small footprint and low power of an FPGA-based solution. It extends the architecture of the 32-bit Sapphire RV32 SoC in several key areas:

• Seven-stage pipeline implementing the RISC-V64IM ISA, with optional A, F, D, C, Zba, Zbb, Zbs, and Zicbom extensions.
• Configurable memory hierarchy with 4 to 512 KB of on-chip RAM, multi-way L1 instruction and data caches, and optional L2 cache, branch predictor, and hardware and software prefetchers.
• Linux support with an optional SV39 memory management unit.
• Memory performance and flexibility for AI workloads, with an optional controller supporting DDR3, HyperRAM, and LPDDR4x at up to 3,200 Mbps.
• Debug capabilities with extensive debug support and native FPGA co-debug.

Sapphire SoCs are configured through the IP Manager and supported by the Efinity IDE and Eclipse-based RISC-V Embedded Software IDE.

Sapphire RV64 product page 

Efinix

The post 64-bit soft SoC expands FPGA processing appeared first on EDN.

AgentEngineer domain-specific, long-horizon agents from Synopsys accelerate engineering across silicon-to-system design. Built on the Autopilot open platform for autonomous engineering, the agents apply AI to workflows spanning verification, implementation, analog, manufacturing, simulation, and analysis in a single unified environment.

Long-horizon agents can reason, plan, and execute complete engineering workflows, allowing teams to achieve faster closure across critical tasks while optimizing token efficiency and reducing latency. Task-level agents apply Synopsys engineering expertise to targeted execution across areas such as autonomous coverage closure, software bring-up and validation, multi-die 3DIC assembly, PPA closure, and analog layout synthesis and design migration.

According to Synopsys, engagements with leading companies have demonstrated up to 50× faster verification closure, 20% higher coverage, and a 30% productivity increase. More than 50 engagements are underway using Synopsys AgentEngineer solutions and the Autopilot Platform, with general availability planned for the end of 2026.

AgentEngineer product page 

Synopsys

The post AI agents speed silicon-to-system engineering appeared first on EDN.

Advanced Energy’s DF150 160-W AC/DC power supply is built for extreme environments in defense and industrial applications. The first entry in the Defiant Future (DF) series of ruggedized, high-reliability power supplies, the DF150 is certified to MIL-STD-810H, withstanding shock, vibration, altitude variations, and temperature extremes. It also provides enhanced EMC performance and complies with MIL-STD-461G requirements.

According to Advanced Energy, the DF150 combines the performance and MIL-STD certifications often associated with custom-designed solutions with the availability and lead-time advantages of a standard commercial product. With its IP67 rating, the unit can withstand submersion in up to 1 m of water for 30 minutes and exceeds MIL-STD ingress protection requirements for dust and liquids.

The DF150 delivers a nominal output of 27 VDC at 6 A (160 W) over an extended operating temperature range of -46°C to +60°C. Fanless operation supports both conduction and convection cooling options for long-term reliability in challenging operating conditions. Full-load efficiency is up to 91%. The power supply operates with no minimum load and leakage current of 275 µA at 230 VAC.

DF150 product page 

Advanced Energy Industries 

The post 160-W power supply withstands harsh conditions appeared first on EDN.

Diodes’ automotive Field-Plated Super Barrier Rectifiers (SBRFP) provide low forward voltage and low reverse leakage current. The 2-A SBRFP2M60P1Q and SBRFP2M60SAFQ, 3-A SBRFP3M60SAFQ, and 8-A SBRFP8A60P5Q are drop-in replacements for comparable Schottky and PN junction diodes. Based on a MOS manufacturing process, Diodes’ SBRFP technology overcomes the limitations of conventional Schottky and PN junction technologies.

The SBRFP8A60P5Q has a maximum forward voltage (VF) of 0.55 V at 8 A, helping reduce conduction losses in high-current applications. The SBRFP2M60P1Q and SBRFP3M60SAFQ offer low reverse leakage currents (IR), with maximum currents of 12 µA and 7 µA, respectively, at 25°C. These characteristics can contribute to improved efficiency and reduced thermal stress under high-temperature operating conditions.

Avalanche energy ratings reach up to 145 mJ, depending on the device, providing additional capability for handling surge events, load dumps, and other transient conditions in automotive electrical systems. The devices operate across a -55°C to +175°C junction temperature range for demanding automotive applications.

Prices for the SBRFP family range from $0.08 to $0.26 each in 1000-piece quantities.

SBRFP2M60P1Q product page

SBRFP2M60SAFQ product page

SBRFP3M60SAFQ product page

SBRFP8A60P5Q product page

Diodes Inc.

The post SBRFP rectifiers cut losses in automotive systems appeared first on EDN.

At just 1.155×1.155 mm, the Renesas GreenPAK SLG46801 configurable mixed-signal IC is small enough for use in smart rings and watches. Its 9-ball WLCSP makes it the smallest device in the GreenPAK family, combining an ultra-compact footprint with multi-time programmability (MTP). The SLG46801 integrates commonly used functions that complement an MCU or replace multiple discrete components in analog signal-processing applications.

Along with two high-speed analog comparators, the SLG46801 integrates configurable lookup tables, two oscillators (10 kHz and 25 MHz), and counters/delays. MTP non-volatile memory is programmed in-system via an I2C serial interface, allowing bug fixes and updates. The device supports operation and programming across a supply range of 1.71 V to 5.5 V for low-cost sensing, control, and glue-logic functions.

In addition to the WLCSP, the SLG46801 is available in a 12-lead, 1.6×1.6-mm STQFN package. The WLCSP provides seven GPIO pins, one of which is voltage-tolerant. The STQFN provides 10 GPIO pins, two of which are voltage-tolerant. GPIO pins used for the I2C interface can also be reconfigured, maximizing flexibility in designs with limited pin availability.

The SLG46801 is sampling now in the STQFN package, with mass production of the WLCSP package planned for November 2026. Renesas Go Configure Software Hub is available for programming, emulation, and simulation.

SLG46801 product page 

Renesas Electronics 

The post Tiny IC packs analog and logic functions appeared first on EDN.

As 5G networks expand in scale, complexity, and societal importance, the underlying timing infrastructure that keeps them synchronized has become a strategic technology domain. While radio access innovations—massive multiple‑input multiple‑output (MIMO), beamforming, millimeter‑wave deployments—often dominate public discussion, the stability and accuracy of network timing are just as critical. Without precise timing, 5G’s most advanced features simply cannot function.

At the center of this timing ecosystem are cesium atomic clocks, technology that has existed for decades but is now more relevant than ever. These devices, long used in national laboratories and scientific institutions, are increasingly essential for ensuring the reliability, resilience, and performance of modern 5G networks.

This article explores why cesium clocks matter, how they fit into 5G timing architectures, and why their role is expanding as operators confront new challenges in synchronization, global navigation satellite system (GNSS) dependence, and critical‑infrastructure reliability.

Figure 1: Next-generation networks link devices and data around the world. (Source: Adobe Stock) The timing imperative in 5G networks

5G networks rely on extremely tight synchronization across thousands of distributed radios. This is especially true for time-division duplex (TDD) systems, which alternate between uplink and downlink transmissions in precisely defined time slots. If radios fall out of alignment, interference increases, throughput drops, and, in severe cases, entire sectors can fail.

The tolerance for timing error in 5G TDD is typically about ±130 ns. Maintaining this level of precision across a geographically distributed network is no small feat.

Critical requirements for precision timing include:

• A stable and accurate frequency reference
• A precise phase reference
• A reliable time‑of‑day reference
• A distribution mechanism that preserves these qualities across fiber, microwave, and radio backhaul

Historically, operators have relied heavily on GNSSes such as GPS, Galileo, or BeiDou to provide the primary timing source. GNSS signals offer global coverage and excellent accuracy, making them a natural fit for telecom synchronization. However, GNSS dependence introduces vulnerabilities.

Figure 2: A satellite in low Earth orbit supports GNSS signals, enabling precise positioning, navigation, and timing for critical systems on the ground. (Source: Adobe Stock) The GNSS challenge: reliability, security, and availability

GNSS signals are extraordinarily weak by the time they reach Earth’s surface. This makes them susceptible to disruptions and even outages from events, including:

• Jamming, both accidental and intentional
• Spoofing, in which false signals mimic legitimate ones
• Environmental blockage, especially in dense urban areas
• Indoor limitations, affecting small cells and private networks
• Regulatory or geopolitical disruptions, which can affect availability

As 5G is integrated into critical infrastructure from transportation to energy and emergency services, the consequences of GNSS disruption become more serious. A timing outage in a 5G network can cascade into failures in dependent systems.

This has led operators and governments to seek GNSS‑independent timing anchors that can maintain network synchronization even when satellite signals are degraded or unavailable. That’s precisely why cesium atomic clocks play a pivotal role.

Cesium atomic clocks: a stable, autonomous timing source

Cesium clocks are among the most stable and accurate timing devices. Their operation is based on the natural resonance frequency of cesium atoms, which is extraordinarily consistent over time. This stability allows cesium clocks to maintain precise timing for months without an external reference.

Some standout characteristics include exceptional long‑term frequency stability, minimal drift over time, deterministic behavior under environmental changes, and autonomous operation without GNSS.

In telecom networks, cesium clocks serve as primary reference sources (PRS) or as part of enhanced primary reference time clock systems. Their role is to provide a stable, traceable timing foundation that other network elements, such as grandmasters, boundary clocks, and radio units, can rely on.

Holdover: the critical advantage of cesium

One of the most important contributions of cesium clocks to 5G is holdover performance. Holdover refers to a clock’s ability to maintain accurate timing when its external reference, typically GNSS, is lost.

High‑quality cesium clocks can maintain frequency accuracy within extremely tight tolerances, phase alignment within 100 ns, and traceability to UTC for extended periods. This can last weeks or even months, depending on the clock design and environmental conditions.

For 5G networks, this means TDD radios remain synchronized, massive MIMO and beamforming continue to function, high‑order modulation schemes remain viable, and network stability is preserved during GNSS outages. In an era where GNSS interference is increasingly common, this capability is not merely beneficial; it is essential.

Cesium in modern 5G timing architectures

Cesium clocks are typically deployed in centralized timing hubs within the operator’s core network. These hubs serve as the authoritative source of time and frequency for the entire network.

The key elements of a typical 5G architecture include:

• PRS: Cesium clocks provide baseline frequency and time reference with outputs of 10 MHz and 1 pps, which feed into timing distribution systems.
• GNSS receivers: GNSS is still used when available, providing traceability to global time standards. Cesium clocks blend GNSS input with their own stability to create a composite reference.
• Grandmaster clocks: Grandmasters distribute timing using IEEE 1588 Precision Time Protocol (PTP), often following telecom profiles such as G.8275.1 or G.8275.2.
• Boundary clocks and transparent clocks: These devices propagate timing deeper into the network while compensating for delays and jitter.
• Radio units: At the edge, radios rely on distributed timing to maintain TDD alignment and support advanced radio features.

In this model, cesium clocks act as the anchor that ensures stability even when GNSS is compromised.

The rise of virtualized timing

As networks evolve toward cloud‑native architectures, timing distribution is also becoming more virtualized. Virtualized primary reference time clock (vPRTC) systems allow operators to centralize timing sources and distribute them over fiber using PTP.

Cesium clocks remain essential in these architectures because they provide the long‑term stability required to maintain traceability and resilience.

vPRTC offers several advantages:

• Centralized GNSS reception in secure locations
• Reduced exposure to spoofing and jamming
• Simplified timing distribution
• Improved control over timing quality
• Enhanced resilience through redundant cesium sources

This approach is increasingly adopted in national telecom networks and critical‑infrastructure deployments.

Figure 3: A stylized cesium atom symbolizes the atomic transitions that form the foundation of ultra-stable timekeeping used in modern synchronization systems. (Source: Adobe Stock) Why cesium matters for advanced 5G features

Several of 5G’s most important capabilities depend directly on precise timing. Techniques such as massive MIMO and beamforming rely on tightly phase‑aligned transmissions across large antenna arrays, where even minor timing deviations can weaken beamforming accuracy and reduce overall spectral efficiency. High‑order modulation schemes such as 256‑QAM and 1,024‑QAM similarly require exceptionally clean, well‑synchronized signals to maintain their performance advantages. Network slicing depends on deterministic latency and predictable behavior across shared infrastructure, both of which are achievable only when timing remains stable throughout the network.

Ultra‑reliable low‑latency communications applications—including industrial automation, robotics, and autonomous systems—push these requirements even further, demanding precise, low‑jitter timing to ensure consistent and safe operation. Together, these capabilities illustrate how deeply 5G’s most advanced functions depend on robust synchronization.

The strategic importance of cesium in national infrastructure

As 5G becomes intertwined with national critical infrastructure, timing resilience becomes a matter of public safety and national security. Governments and standards bodies increasingly emphasize the need for GNSS‑independent timing sources.

Cesium clocks are well-suited for supporting resilient 5G timing because they deliver stable, autonomous operation without relying on external signals, maintain predictable long‑term performance, and remain resistant to interference that can disrupt satellite‑based timing. Their ability to stay aligned with international time standards while continuing to function accurately during GNSS outages makes them a dependable foundation for critical network synchronization.

In many countries, cesium clocks form part of national timing centers that support telecom networks, power grids, transportation systems, and scientific institutions.

A technology whose importance is growing

Cesium atomic clocks have been part of the scientific landscape for decades, but their role in modern telecommunications is expanding rapidly. As 5G networks become more complex and more critical to society, the need for stable, resilient, GNSS‑independent timing grows accordingly.

Cesium clocks deliver long‑term stability, exceptional holdover, deterministic performance, and independence from GNSS vulnerabilities, making them a highly resilient foundation for precise network timing. They are not a replacement for GNSS but instead a complement forming the backbone of timing architectures that must remain operational under all conditions.

In the broader story of 5G, cesium clocks may not be the most visible technology, but they are one of the most essential: Their quiet precision ensures that the world’s most advanced wireless networks remain synchronized, resilient, and ready for the demands of the future.

The post Cesium atomic clocks: The backbone of precise 5G timing appeared first on EDN.

Виробництво ортезів і навчання, як спосіб повернути ветеранів до повного життя KPI4U-2 ср, 09/30/2026 - 16:30

Salim Benbouziyane has built a cyberdeck that fits inside an Altoids tin. The pocket computer has a physical keyboard, an LCD screen, and runs Doom. The project combines the nostalgia of the mints with the challenge of miniaturizing an entire working PC.

The key to the project is the Raspberry Pi Compute Module Zero. This compact board replaces a traditional SBC and frees up precious space.

Four PCBs for a compact cyberdeck

The project uses four PCBs in total. The first is a custom two-layer carrier board that handles connections and support for the hardware. The second PCB connects the LCD screen with a ribbon cable, allowing the box to open like a hinge.

In addition, a third empty PCB acts as a spacer between components. The fourth contains the dome switches for the keyboard. Each layer has a precise role, and the vertical arrangement uses every millimeter of the tin.

3D-printed covers and front panels protect the PCBs. These pieces also form the screen bezel and the keyboard keys. The Creality Ender-3 V3 SE 3D printer is a suitable choice for anyone wanting to recreate the project, thanks to its 22x22x25 cm print volume.

How the mini PC in a tin works

The Raspberry Pi Compute Module Zero plugs into the carrier PCB, which routes all connections to the screen and keyboard. The ribbon cable passes through the hinge of the tin, so the lid opens without disconnecting components. The system boots Doom directly from the module.

The dome keyboard uses physical switches, giving precise tactile feedback. The 3D-printed keys mount on top of the domes, and the tin acts as a rigid shell. The result is a sturdy, portable device that fits in a pocket.

For the screen, the project uses an LCD compatible with the module. An SPI 256×64 OLED display can be an interesting alternative for those who want to experiment, thanks to its high contrast and low power consumption. The choice of display depends on the space and resolution desired.

Salim Benbouziyane’s project is an example of extreme engineering in minimal space. The challenge is not just running Doom, but integrating keyboard, screen, and board into a mint tin. Every component is chosen to reduce bulk without sacrificing functionality.

The combination of custom PCBs and 3D printing makes the project replicable. The project video documents the main steps, and anyone with KiCad experience can adapt the design. The cyberdeck is a tribute to maker culture and retrogaming.

• Raspberry Pi Compute Module Zero for maximum compactness
• Two-layer carrier PCB for connections
• Four PCBs for screen, keyboard, and spacers
• 3D printing for bezel and keys
• Tin box as the shell

For those who want to try it, SMD soldering and PCB design skills are needed. The project requires patience, but the result is a unique computer that runs Doom. The nostalgia of tin boxes meets modern technology, and the cyberdeck becomes a collector’s piece.

Source: https://youtu.be/Ajft97gAxV8?si=fmr4b5Vugi0B8wXn

The post Cyberdeck in a Tin Box: Doom on Raspberry Pi appeared first on Open Electronics.

A curious connection of control buttons makes a simpler-is-better digital potentiometer interface possible.

Two recent submissions to the Design Ideas kitchen (see Related Content) have shown different basic step-per-push pushbutton interfaces for up/down digital potentiometers. Since they have the same purpose and perform the same function, they mostly can only meaningfully differ in their respective part counts. Which they did.

Wow the engineering world with your unique design: Design Ideas Submission Guide

But we engineers generally agree that, keeping other factors equal, simpler yet is even better yet. Therefore Figure 1, with only two resistors, one capacitor, and one logic gate, is offered as a small, but still noticeable, further improvement in the breed.

Figure 1 NC (normally closed) push-to-open momentary pushbutton switches connected in series are the basis for an unusually simple digital pot interface.

Here’s how it works.

Figure 1’s series connection of control switches lets them share a single pullup resistor. Pushing either the DOWN or UP button releases R1, pulls up R2, and begins charging C1. The resulting ~5ms low-pass bounce-filter connection to Schmitt inverter U1’s pin 1, generates a debounced, clean, and sharp pot clock edge on U1 pin 2. This will either increment or decrement the pot setting.

Which action actually happens depends, of course, on which button got pushed. Pushing UP pulls up and asserts U2’s U/-D pin 2, making the clock pulse increment the pot’s setting. Pushing DOWN leaves it low and the pot therefore decrements. The R2C1 debounce delay gives any initial pin 2 switch bounce adequate time to rattle around, settle down, set up, and stabilize before the clock drops and U2 samples it.

Releasing the button discharges C1. The associated R2C1 debounce timeconstant and Schmidt trigger action keep the discharge ramp and clock pin transition as clean and snappy as was the charge side. This is of course necessary if we’re going to avoid generating spurious trailing clock transitions that would corrupt the pot setting. Which we would never allow.

And that’s it. Which might just possibly be as simple as it can get. But I wouldn’t bet on it.

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

Related Content

• DPOT push up/down
• Push to increase, decrease a digital potentiometer
• Extend monolithic programmable-resistor-adjustment range with active negative resistance
• Op-amp wipes out DPOT wiper resistance
• Dpot pseudolog + log lookup table = actual logarithmic gain

The post Wire pushbuttons in series to simplify DPOT up/down circuit appeared first on EDN.

Mouser Electronics, Inc., the authorized global distributor of the newest electronic components and industrial automation products, now stocks the HARTING ix Industrial PushTrigger IP20 connectors. The ix Industrial PushTrigger IP20 connectors are an alternative to HARTING’s PushPull solutions and are available with type A, B and C coding. With their compact design, PushTrigger connectors deliver high-performance connectivity for the most demanding industrial Ethernet applications, including automation, robotics, control systems, smart infrastructure and transportation systems.

Technical features and benefits

The HARTING ix Industrial PushTrigger IP20 connectors, currently available from Mouser, feature a vibration-resistant push-pull locking mechanism and IDC termination, which allows for quick assembly that requires no soldering. The PushTrigger IP20 connectors are compatible with all ix Industrial female connectors; installation procedures remain the same even when moving from standard ix products. With dimensions up to 75% smaller than traditional RJ45 connectors, the PushTrigger IP20 series frees up space for additional connectors and assemblies, while supporting Cat 6A Class EA transmission up to 500 MHz and data transfer rates up to 10 Gbit/s.

Ruggedness and reliability

The ix Industrial PushTrigger IP20 connectors are fully shielded against electromagnetic interference and shocks, and are vibration resistant according to IEC 61373 Category 1, Class B. They offer IP20 protection, high-durability mating cycles and an operating temperature range from -40 °C to +85 °C.

Availability and resources

For more information on these high-performance connectors, visit the dedicated page on the Mouser website. For more news about Mouser and our latest product news, visit the Mouser newsroom.

As an authorized global distributor, Mouser offers the widest selection of semiconductors, the latest electronic components and the newest industrial automation products. Mouser customers can count on original, 100% certified and fully traceable products from each of its partner manufacturers. To help speed up customer designs, the Mouser website hosts a vast library of technical resources, including a Technical Resource Center, and offers product datasheets, supplier-specific reference designs, application notes, design technical data, engineering tools and other useful information.

Mouser offers thousands of industrial automation products, available in stock and ready for immediate shipment. From predictive maintenance devices and control panels to a complete range of industrial power products, sensors and safety devices, Mouser’s portfolio is available to customers to help them design, build and maintain complete industrial automation solutions. For more information, visit the industrial automation section.

The post HARTING ix Industrial PushTrigger IP20 Connectors Now in Stock at Mouser appeared first on Open Electronics.

Just wanted to share with you this gem that I have found on aliexpress: Buck converter Mini560. According to the seller this are the specs: 5.5–20V input to fixed outputs of 3.3V, 5V, 9V, or 12V depending on the version. 5A max, >3A with cooling. 99% efficiency Be aware that there are different modules out there and not all of them perform well, so if you get lucky you'll get an awesome dc-dc converter, but it seems that is easy that you'll get the bad ones. The photo belongs to the actual module that I have tested. This little thing has capabilities beyond belief, I have thrown in the trash bin all my old and bulky buck converters as they cannot do half what this small buck converter can do in such small footprint. I have tested it at 10V input and 5V output. It has maintained the output voltage without issues in any case. Under 5A always at ~100mVpp ripple, at 6 and 7 amps the ripple has stood below 300mVpp. I have tested it naked at 28C room temperature, without cooling, with 2 small heatsinks for the chip and the inductor (even though the inductor does not heat up that much), and with the heatsinks plus a fan. I have pushed the module well beyond what the seller recommends. Every test has been measured after 10 minutes ON. These are the results: Current Efficiency T not cooling T heatsinks T heatsinks+fan 3A 95.8 59C --- --- 4A 95 --- 63.3C 42.2C 5A 94 --- 80C 50C 6A 93.4 --- --- 59C 7A 92.2 --- --- 70C I have not tried going further, just tested it extensively to know how can I push it safely. So I would not use it over 5A, just to be clear. So yeah, one of the best modules I have gotten my hands on. submitted by /u/venumdk [link] [comments]

У кого питали, коли не було Гуглу? Інформація КП ср, 09/30/2026 - 12:00

This project builds a complete DIY AI voice assistant on an ESP32 board. The system listens with an I2S microphone, records the voice, transcribes it with the OpenAI Whisper API, generates a response with GPT, and plays it back through an amplifier and speaker. An OLED display animates two expressive eyes that follow the state of the conversation. Everything runs on a standard ESP32, with no complex additional hardware.

jayesh_nawani’s Hackster.io page collects all the project details. The build requires common components: an ESP32 development board, a MAX98357A amplifier, a 0.96-inch OLED display, an I2S microphone, and a 3W speaker. For those who want to start with a ready-made base, the ESP32-C6-Zero board offers a compact and modern alternative, even though the original project uses the classic Development Board.

How the main loop works

The main loop continuously listens to the I2S microphone. When it detects a sustained volume peak above the threshold of 1000, it starts recording. Recording continues until silence lasts at least 200 ms per 1000 ms of hold, or up to a maximum of 2 seconds. The audio clip is then packaged as a WAV file and sent to the Whisper API for transcription.

The transcription goes to the GPT Chat Completions API, which generates a conversational response. The text is then sent to the TTS API, and the resulting PCM audio is streamed to the I2S amplifier as it arrives. Sampling happens at 16000 Hz, while TTS works at 24000 Hz. The chunk size is 512 bytes, with a speech synthesis rate set to 0.85.

The OLED display runs a separate FreeRTOS task on core 0, dedicated to animating the eyes and showing the system status. The main pipeline instead runs on core 1. This separation prevents blocking HTTP calls from slowing down the animation. The result is a smooth and responsive interface, with eyes that move while the assistant listens and responds.

The most interesting technical challenges

The project tackles real problems that every maker encounters. Heap fragmentation is one of the toughest: every call to the OpenAI APIs requires contiguous memory. The code frees a 32KB block before each request, so the HTTP libraries have enough space. Without this precaution, calls fail randomly.

Handling blocking HTTP calls is another challenge. On an ESP32, a request to an API can block the main loop for seconds. The adopted solution uses both cores: one for logic, one for animation. In addition, hardware debugging was systematic: each component was tested individually before integrating everything. For example, the microphone was verified with an oscilloscope before connecting it to the amplifier.

For those who want to rebuild the project, the breadboard is the ideal starting point. The connections are simple: the microphone uses GPIO 14, 15, and 32, the amplifier uses GPIO 26, 25, and 22, and the OLED display uses GPIO 21 and 19. A 0.96-inch, 128×64 OLED display like the one in the project is perfect for the animated eyes, thanks to its resolution and high contrast.

The code uses the Arduino IDE with the ArduinoJson, Adafruit_GFX, and Adafruit_SSD1306 libraries. The trigger threshold is set to 1000, the silence threshold to 200, with a hold of 1000 ms. Three consecutive chunks are needed to validate a minimum sample of 0.6 seconds. These parameters are tuned for a home environment, but can be adjusted easily.

This project demonstrates that a complete AI voice assistant can run on a simple ESP32. No Raspberry Pi or dedicated computer is needed. The combination of Whisper, GPT, and TTS works in real time with acceptable latency. Moreover, the project teaches how to handle concrete problems like limited memory and blocking network calls.

The most fascinating aspect is the OLED display with animated eyes. It adds personality to the device and makes interaction more natural. The dedicated FreeRTOS task shows how to make the most of the ESP32’s two cores. Finally, the project is completely open-source, so anyone can modify and improve it.

• I2S microphone on GPIO 14, 15, 32
• MAX98357A amplifier on GPIO 26, 25, 22
• OLED display on GPIO 21, 19
• Sampling at 16000 Hz, TTS at 24000 Hz
• Trigger threshold 1000, silence 200, hold 1000 ms
• Max recording 2 seconds, chunk 512 bytes

For audio, an open-source amplifier like ANGELO can replace the MAX98357A, offering more flexibility and a modular design. Alternatively, a TDA7297 stereo amplifier is suitable if you want to expand the project to two channels. The choice depends on power needs and available space.

Finally, the project is an excellent starting point for more advanced experiments. You can add recognition of custom commands, integrate a larger display, or connect environmental sensors. The possibilities are endless, and the solid foundation of this project makes every modification easier.

Source: https://www.hackster.io/jayesh_nawani/ai-voice-assistant-with-esp32-4a3d5f

Related products

• Display OLED I2C 0,96"

The post DIY AI voice assistant with ESP32 and animated OLED eyes appeared first on Open Electronics.

DRFM jammers rely on receiving radar signals, digitizing them and retransmitting them with controlled delay, phase and frequency. As radar systems become more agile and use increasingly complex waveforms, test systems need to measure parameters such as pulse shape, timing, modulation and repeatability, as well as analyze complete pulse trains and pulse-to pulse variations. The R&S FSWX signal and spectrum analyzer addresses these requirements with its dual-channel, phase coherent architecture. With the R&S FSWX-KM700 pulse analysis option, Rohde & Schwarz adds a software extension dedicated to pulsed-signal and DRFM analysis, enabling engineers to evaluate pulse parameters, pulse trains, modulation and the timing behavior of jammer signals.

The R&S FSWX-KM700 pulse analysis option measures key pulse parameters, including pulse width, amplitude, rise time, fall time, pulse repetition interval, duty cycle, pulse shape and overshoot. These measurements can help engineers evaluate the accuracy and consistency of reproduced radar pulses and identify variations in timing, amplitude and other pulse characteristics. Such variations can affect the fidelity of a reproduced signal, making accurate pulse analysis important when testing DRFM-based deception and jamming systems.

The analysis also covers complete pulse trains. The option extracts pulse repetition frequency spectra and pulse-to-pulse variation data, allowing engineers to verify complex pulse sequence behavior and timing patterns. R&S FSWX-KM700 supports chirped pulses, pulse width modulation, pulse position modulation and phase-modulated waveforms. Engineers can use these measurements to check whether a device handles modulation schemes used by modern radar systems, including both the pulse envelope and modulation content.

The system can trigger on amplitude, pulse width, pulse repetition interval or user-defined patterns. This helps engineers isolate selected events inside a pulse train and focus the measurement on the relevant parts of the signal. For longer measurements, R&S FSWX-KM700 aggregates results from many captured pulses. This provides information about repeatability and consistency over time and helps engineers assess whether timing or modulation errors occur only under certain conditions.

The option comes with the following displays: parameter trend for DRFM electronic attack technique analysis, capture vs. time to measure jammer response time and latency between stimulus and response, individual pulse parameter display such as pulse amplitude, frequency, and phase to make sure there are no distortions introduced by the jammer. These measurements connect pulse analysis with the behavior of the jammer under test.

With the new R&S FSWX-KM700 option, the FSWX signal and spectrum analyzer gains a more specialized role in DRFM test workflows. It combines phase coherent multi-channel analysis with pulse, pulse train, modulation and segmented capture functions in one instrument, supporting verification of signal fidelity, timing behavior and consistency in agile electronic warfare scenarios.

 

The post Rohde & Schwarz FSWX-KM700 Adds Pulse Analysis for DRFM Jammer and Radar Testing appeared first on ELE Times.

​A new analysis report presented by EY-IESA estimates that India’s semiconductor market will grow more than threefold by 2035. It states that the market will increase from nearly $64 billion in 2026 to $200 billion by 2035 covering areas such as artificial intelligence, data centres, telecommunications, electric vehicles, and advanced semiconductor manufacturing.

The findings of the report point to the increase in demand for semiconductors in India’s consumer electronics and industrial sectors. Consumer electronics is the largest demand segment accounting for a 30% market share, followed by Automotive (16%) and Industrial (15%).

Semiconductor imports by India have also increased in recent years. According to the report, semiconductor imports have increased fivefold, from $5.7 billion in FY2017 to $30.3 billion in FY2025, representing a compound annual growth rate of 23%. The report also states that increased domestic demand presents a good opportunity to expand India’s manufacturing, research and development, and supply chain capabilities for semiconductors.

Another key strength is India’s ability in chip design. The country has nearly 20% of the global chip design engineers which is a positive point for talent development and there is a huge opportunity for expand semiconductor manufacturing, chip design and commercialisation.

According to the report, key technologies in the semiconductor industry—including advanced packaging, compound semiconductors, photonics and chip-to-system integration—should be the focus for India’s potential growth. It also calls for stronger semiconductor manufacturing clusters, improved infrastructure, specialised talent and closer industry-academic collaboration.

The Indian semiconductor market, projected $200 billion by 2035, indicates the scale of the opportunity for India as it seeks to expanding its footprints across the semiconductor supply chain.

The post India’s Semiconductor Market Projected to Reach $200 Billion by 2035: EY-IESA Report appeared first on ELE Times.

​As India emerges as a global supplier in the semiconductor industry and builds capabilities in chip design and manufacturing, the country could face cybersecurity, geopolitical, and other disruption-related challenges. Union IT Minister Ashwini Vaishnaw gave this warning during a media interview in New Delhi. While speaking to the media on September 19, the minister urged Indian startup companies to be careful against potential cyberattacks, geopolitical risks and other disruptions.

Addressing the media, the minister said that India’s emergence as a country capable of designing and manufacturing chips for semiconductor devices could improve its position in the global semiconductor value chain, potentially drawing attention from established players and opponents of India’s rise. He also stated that he had discussed these concerns with the industry and urged them to prepare for potential cyberattacks, threats, and other possible disruptions.

These risks could extend beyond common business competition to include cyberattacks, physical attacks, misinformation, and other forms of disruption. The country’s push for semiconductors has also attracted increasing investment interest. Recent announcements related to this include Applied Materials, a United States manufacturing company, planning a US$5 billion investment in India through 2035, Lam Research’s proposed ₹10,000 crore investment; and Fujifilm planning to invest approximately ₹800 crore to establish a semiconductor material plant in Dholera. These developments reflect the country’s growing ambition to expand India’s semiconductor ecosystem.

The warning from Union IT Minister reflects the major concern that needs to be cater by Indian semiconductor companies to consider cybersecurity and other broader disruption risks alongside investment in manufacturing capacity, technology and talent.​

The post Vaishnaw Warns India’s Semiconductor Industry of Cyberattacks and Disruptions appeared first on ELE Times.

Vishay Intertechnology has introduced a new Automotive Grade, top-side cooling mount thick film power resistor. The Vishay Sfernice D2TO35S is designed for automotive applications, offering improved thermal performance and reduced PCB space requirements. The resistor provides high power dissipation of up to 35 W at 25°C and is housed in a surface-mount TO-263 (D²PAK) package.

As thermal constraints increasingly become the primary system design limitation, many power components are transitioning from PCB-based cooling to top-side cooled architectures. By transferring heat directly to a heatsink, the D2TO35S released today enables up to nine times greater power dissipation than standard PCB-mounted devices when paired with an appropriate heatsink. Its compact, surface-mount design allows designers to increase power dissipation within the same footprint or provide the same functionality in a smaller footprint, while lowering PCB temperatures, reducing thermal stress on neighboring components, and improving overall system reliability.

Offering a non-inductive design for improved signal integrity and power handling in fast transient conditions, the D2TO35S features a resistance range from 4.7 Ω to 550 kΩ — with tolerances down to ± 1 % — thermal resistance of 4.28 °C/W, TCR down to ± 150 ppm/°C, and a wide operating temperature range from -55 °C to +175 °C. The RoHS-compliant device is solder reflow secure at 270 °C/10 s.

The post Vishay D2TO35S: 35 W Automotive Thick Film Power Resistor with Top-Side Cooling in TO-263 Package appeared first on ELE Times.

AI agents are beginning to change something more fundamental than how organizations use software. They are beginning to receive authority.

A conventional AI system can provide information, summarize data, identify alternatives, or recommend an action. An agent can increasingly go further. It can select an action, execute it, commit resources, change a system, initiate a transaction, and modify an engineering workflow. And potentially make decisions without waiting for a human at every step.

That is a much larger transition than moving from one generation of software to another. It’s a transition from assistance-based AI to authority-based AI. And that raises a different question. It’s no longer enough to ask: What can the agent do?

Organizations must also ask: What authority should the agent have to make this decision? And immediately after that: What evidence and level of risk justify giving it that authority? As AI moves from providing information to making consequential decisions, trust can no longer remain an assumption surrounding the system. In other words, trust must become infrastructure.

From assistance to authority

Consider the following progression:

Assist → Recommend → Decide→ Execute → Commit

These are not simply increasing levels of AI capability. They are increasing levels of delegated authority. At the first level, AI provides information. At the second, it recommends what might be done. At the third, the organization allows it to select an action. At the fourth, it executes that action. At the fifth, it commits something consequential: money, inventory, production capacity, infrastructure, engineering changes, or contractual obligations.

The risk changes dramatically across that progression. A bad recommendation can be rejected. A bad decision that has already been executed may have to be reversed. Some actions may be expensive to reverse. Others may be impossible to reverse.

That creates a fundamental distinction: Capability determines what an agent can do. Trust determines what authority an organization permits it to exercise. Organizations therefore should not think only about whether an agent is intelligent enough to perform a task. They must think about the risk of giving it authority over the outcome.

Every decision has an authority boundary

An agent does not make a decision in isolation. It makes that decision because an organization has explicitly or implicitly allowed it to act within some boundary. That boundary matters. Can the agent spend $100? $100,000? Can it select a supplier? Can it change a production schedule? Can it modify a design? Can it release that design? Can it shut down infrastructure? Can it move capital? Can it enter a contractual commitment?

These are fundamentally different levels of authority. So, the important question is not simply whether AI can make good decisions. It is: Which decisions can be delegated, under what conditions, within what limits, and based on what evidence? That is an organizational architecture problem as much as an AI problem.

Agentic commerce example

An AI shopping agent can search far beyond the handful of websites a person would normally visit. That can be extremely valuable. For instance, a small retailer that previously had almost no chance of being discovered by a particular customer can suddenly compete because the agent evaluates the market rather than simply visiting familiar stores.

But the same capability creates another possibility. What happens when fraudulent merchants begin designing storefronts specifically to attract autonomous agents? The agent now must determine whether the merchant exists, whether the product is authentic, whether the offer is credible, whether fulfillment is reliable, and whether the transaction should be authorized.

The trust decision did not disappear when the human stopped shopping manually. The trust decision moved into the agentic infrastructure. Now extend the same problem into industry. The consequences become much larger.

Authority multiplies consequence

Imagine an agent selecting a supplier. Another changing factory production schedules. Another reallocating inventory. Another configuring computing infrastructure. Another executing financial transactions. Another modifying an engineering design. Another deciding whether that design has satisfied the conditions required to proceed.

Every one of these systems may be highly capable. But capability alone does not answer the most important organizational question: How much consequence should this system be allowed to create? This is why authority changes the risk equation.

The same model may be acceptable for recommending a decision but unacceptable for executing it autonomously. The difference is not necessarily intelligence. The difference is authority and consequence.

Trust has multiple layers

Trust infrastructure cannot be reduced to a model confidence score. An organization allowing autonomous decisions needs multiple layers of evidence and control.

• Identity: Which agent is acting, and on whose behalf?
• Provenance: What information, models, sources, and prior decisions support the action?
• Validation: Has the proposed action satisfied the required technical or business checks?
• Risk: What can happen if the decision is wrong, incomplete, manipulated, or based on incorrect information?
• Authority: Is this agent permitted to make this particular decision?
• Authority: Is this agent permitted to make this particular decision?
• Boundaries: How far can it act without additional approval?
• Traceability: Can the organization reconstruct what happened and why?
• Verification: Did the action produce the intended outcome?
• Accountability: Who ultimately owns the consequence?

These layers are interconnected. And more importantly, they should not remain constant as authority increases. Greater authority requires stronger trust infrastructure.

More intelligence doesn’t eliminate risk

This is particularly important as AI becomes more capable. Greater intelligence can improve decisions. But greater intelligence does not eliminate the underlying risk created by delegated authority. In fact, a more capable agent may be able to operate across more systems, make more decisions, execute them faster, and create larger consequences before a human intervenes.

That means more intelligence does not eliminate the need to manage risk. Greater capability can increase the amount of consequential authority that must be controlled. This is not an argument against autonomy; it’s an argument for matching autonomy to evidence.

The objective should not be to place humans permanently inside every decision loop. The objective should be to determine where autonomous authority is justified and where it’s not.

Evidence and authority must move together

This gives us a useful principle: Authority should expand only as supporting evidence becomes stronger. An agent may begin with recommendation authority. After repeated validated outcomes, it may receive authority to execute narrow and reversible actions.

With stronger evidence, the boundary may expand. More consequential decisions require stronger validation. Highly consequential or irreversible decisions require stronger evidence still. The progression becomes as follows:

Capability → Evidence → Risk assessment → Bounded authority → Decision → Execution → Verification → Accumulated evidence → Expanded authority

This is different from simply trusting an AI system because it performed well on a benchmark. Authority becomes something that is earned through evidence and bounded by risk.

Reversibility changes the evidence requirement

Not all decisions deserve the same trust threshold. Reversibility matters. If an agent makes a software configuration change that can be rolled back immediately, an organization may tolerate a particular level of uncertainty. However, if an agent commits millions of dollars, changes a physical manufacturing process, releases a production order, signs a contractual obligation, or sends a semiconductor design to fabrication, reversal may be extremely expensive—or impossible.

That produces another useful relationship: As consequence increases and reversibility decreases, the evidence required for autonomous authority should increase. This gives decision makers a more useful framework than simply asking whether AI should or should not be autonomous.

In other words, autonomy becomes conditional.

Speed makes trust more critical, not less

AI agents create another complication: speed. Speed is one of their greatest advantages. Agents can search alternatives, evaluate information, coordinate across systems, and execute decisions far faster than conventional organizational workflows. However, speed also compresses the opportunity to detect a bad decision before it becomes an action.

That makes the combination of speed plus authority particularly important. A human organization might take hours or days to progress from information to recommendation to decision to execution. But an autonomous system may traverse that sequence in seconds. If the decision is wrong, speed can turn one error into many actions before anyone recognizes what happened.

So, the faster autonomous authority operates, the less an organization can depend on after-the-fact human intervention as its primary protection. Trust infrastructure must increasingly operate at machine speed with identity, validation, risk boundaries, permissions, traceability, and verification. These attributes cannot sit outside the autonomous workflow; they must travel with it.

Trust can become an industrial advantage

This leads to an important competitive implication. Two organizations may eventually have access to comparable AI capability. Yet one may allow its agents only to recommend actions because it lacks the evidence, controls, and organizational confidence required for greater autonomy.

Another may have built sufficient trust infrastructure to allow agents to make and execute meaningful decisions within carefully defined boundaries. So, the second organization can potentially operate much faster. Not necessarily because its AI is smarter, but because it can safely grant the AI more useful authority.

That means competitive advantage may increasingly come from the combination of AI capability + evidence + risk control + bounded authority + execution speed. In other words, the model alone is not the complete system.

The next question for agentic AI

The first wave of generative AI largely asked: What can AI produce? Agentic AI introduced another question: What can AI do? And now the industry must confront the more consequential question: What decisions should AI be authorized to make?

And behind that question are two more questions: What evidence justifies that authority? What risk is the organization willing to accept when it delegates it? Those questions apply to commerce, finance, supply chains, manufacturing, infrastructure, and engineering. And eventually almost every environment in which autonomous systems can create real-world consequences.

The most capable agent will not automatically be the most valuable. The valuable agent will be one whose capability can be translated into trusted, bounded, and verifiable authority. That is the larger transition now beginning.

AI capability determines what becomes possible. Evidence establishes what can be trusted. Risk determines what must be controlled. Authority determines what the agent is allowed to decide. And when those decisions begin producing consequential outcomes at machine speed, trust becomes infrastructure.

Dr. Moh Kolbehdari is senior director of IC/packaging at Socionext US.

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The post When AI agents make decisions, trust becomes infrastructure appeared first on EDN.

Set your DMM to "Diode test" Mode. Identify the transistor`s three terminals (let BC547 i.e., base, collector, and emitter) by using its part number and datasheet. Connect red probe to base and black probe to collector/emitter, you get ~0.6-0.7 V (result forward bias). This means an NPN transistor is good. Reverse the polarity gives us no reading (i.e., OL). Otherwise, NPN transistor is faulty. submitted by /u/SpecialistRare832 [link] [comments]