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The world is experiencing an insatiable and rapidly growing demand for artificial intelligence (AI) and high-performance computing (HPC) applications. Breakthroughs in machine learning, data analytics, and the need for faster processing across all industries fuel this surge.

Application-specific integrated circuits (ASICs), typically implemented as system-on-chip (SoC) devices, are central to today’s AI and HPC solutions. However, traditional implementation technologies can no longer meet the escalating requirements for computation and data movement in next-generation systems.

From chips to chiplets

Traditionally, SoCs have been implemented as a single, large monolithic silicon die presented in an individual package. However, multiple issues manifest as designers push existing technologies to their limits. As a result, system houses are increasingly adopting chiplet-based solutions. This approach implements the design as a collection of smaller silicon dies, known as chiplets, which are connected and integrated into a single package to form a multi-die system.

For example, Nvidia’s GPU Technology Conference (GTC) has grown into one of the world’s most influential events for AI and accelerated computing. Held annually, GTC brings together a global audience to explore breakthroughs in AI, robotics, data science, healthcare, autonomous vehicles, and the metaverse.

During his GTC 2025 keynote, Nvidia president, co-founder, and CEO Jensen Huang emphasized the need for advanced chiplet designs, stating: “The amount of computation we need as a result of agentic AI, as a result of reasoning, is easily 100 times more than we thought we needed this time last year.”

Despite a wide range of analyst expectations, explosive growth is undisputed; chiplets are becoming the default way to build large AI/HPC dies (Figure 1).

Figure 1 Chiplet market forecast illustrates its explosive growth. Source: Nomura and MarketUS

Figure 1 above represents the center of gravity of several published forecasts. Tools, technologies, and ecosystems are coming together with a 2026-27 inflection point to facilitate designers’ goal of being able to purchase complex chiplet IP on the open market.

These chiplets will adhere to standard die-to-die (D2D) interfaces, allowing them to operate plug-and-play or mix-and-match. This is expected to generate explosive growth in the chiplet market, reaching at least USD 100 billion by 2035, with some forecasts more than doubling this forecast.

Why chiplets?

One increasingly popular approach is to take an existing monolithic die design and disaggregate it into multiple chiplets. A simplistic representation of this is depicted in Figure 2.

Figure 2 Monolithic die (left) is shown vs. multi-die system (right). Source: Arteris

In monolithic implementations, reticle limits impact scalability, and yields fall as the die size increases. It’s also harder to reuse or modify IP blocks quickly, and implementing all the IPs at the same process technology node can be inefficient.

Chiplet-based multi-die systems offer multiple advantages. When the design is disaggregated into various smaller chiplets, yields improve, and it’s easier to scale designs, currently up to 12x of today’s reticle limit. Also, each IP can be implemented at the most appropriate technology node. For example, high-speed logic chiplets may use the 3-nm node, SRAM memory chiplets the 7-nm node, and high-voltage input/output (I/O) interfaces the 28-nm node.

Observe the red bands shown in Figure 2. These represent a network-on-chip (NoC) interface IP. In a multi-die system, each chiplet can have its own NoC. The chiplet-to-chiplet interfaces, known as die-to-die connections, are typically implemented using bridges based on standard interconnect protocols and physical layers such as BoW, PCIe, XSR, and UCIe.

Aggregation, disaggregation, and re-aggregation

As chiplet-based designs gain traction, it’s essential to understand how today’s SoCs are typically assembled. Currently, the predominant method is to gather a collection of soft IPs, represented at the register transfer level (RTL) of abstraction, and aggregate them into a single, monolithic design. Most of these IPs are sourced from trusted third-party vendors, with the SoC design team creating one or two IPs that will differentiate the device from competitive offerings.

To successfully integrate these IPs into a cohesive design, two other aspects are essential beyond the internal logic that accounts for most of an IP block’s transistors. The first is connectivity information, including port definitions, data widths, operating frequencies, and supported interface protocols. The second is the configuration and status registers (CSRs) set, which must be placed appropriately within the overall SoC memory map to ensure correct system behavior.

Because of this complexity, performing this aggregation by hand is no longer possible. IP-XACT is an IEEE standard (IEEE 1685) that defines an XML-based format for describing and packaging IPs. To facilitate automated aggregation, each IP has an associated IP-XACT model.

As SoC complexity continues to rise, it is becoming increasingly common to take an existing monolithic die design and disaggregate it into multiple chiplets. To support this chiplet-based design, the tools must be able to disaggregate an SoC design into multiple chiplets, each of which may contain many original soft IPs. In addition to partitioning the logic, the tools must generate IP-XACT representations for each chiplet, including connectivity and registers.

Technology Is here now

AI and HPC workloads are advancing quickly, driving a fundamental shift toward chiplet-based architectures. These designs provide a practical solution to meet the increasing demands for scalability and efficient data movement. They require new methodologies and supporting technology to manage multi-die systems’ design, assembly, and integration.

Take, for instance, Arteris’ multi-die solution, which automates key aspects of multi-die design. Magillem Connectivity and Magillem Registers support the assembly and configuration of systems built from IP blocks or chiplets. These tools manage both disaggregation of monolithic designs and re-aggregation into multi-die systems across the design flow.

On the interconnect side, Arteris supplies both coherent and non-coherent NoC IP. Ncore enables cache-coherent communication across chiplets, presenting a unified memory system to software. FlexNoC and FlexGen provide non-coherent options that are compatible with monolithic and multi-die implementations.

Andy Nightingale, VP of product management and marketing at Arteris, has over 37 years of experience in the high-tech industry, including 23 years in various engineering and product management positions at Arm

 

Register for the virtual event The Future of Chiplets 2025 held on 30-31 July.

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The post Chiplet design basics for engineers appeared first on EDN.

For coverage of all the key business and technology developments in compound semiconductors and advanced silicon materials and devices over the last month...

India seems to be adjusting its stance toward Chinese investment within the electronics manufacturing space. Government actions indicate a willingness to adopt a flexible and pragmatic posture, weighing both geopolitical and economic concerns.

Change in Engagement Strategy:

China continues to dominate the electronics supply chain globally, engaging in nearly 60% of worldwide electronics manufacturing activities. Under this recognition of interdependence on each other, India seems to be reconsidering its previous hardline approach to allow for strategic collaboration in industries of key importance.

Recent events, namely the restoration of tourist visas for the two countries and diplomatic engagement, have pointed toward a potential gradual thawing of bilateral relations. And this softening of relations on the diplomatic front seems to be reflected now on the industrial policy side, especially for electronics, where global collaboration matters.

The Dixon-Longcheer Deal:

The government turned its gaze onto this matter after it approved the joint venture between Dixon Technologies, a major domestic manufacturer, and Longcheer Intelligence, a Chinese ODM. The agreement states that Longcheer will own 26 percent of the business and Dixon will maintain controlling control. This framework reflects India’s intention to engage with Chinese companies through closely monitored minority-stake agreements.

Following this approval, it is understood that several other Indian electronics companies have developed a keen interest in forming similar joint ventures with Chinese technology partners.

Focus on Value Addition and Technology Transfer

According to the Indian government, Chinese investments will be allowed only if there is significant technology transfer involved and not mere low-level assembly operations. The Ministry of Electronics and IT (MeitY) stated that such collaborations should factor in the improvement of domestic capabilities and local value addition.

Proposal of Policy Reforms

In an attempt to ease out the process and bring down red tape, the NITI Aayog, India’s think tank, has recommended allowing up to 24% foreign direct investment (FDI) by Chinese firms in Indian electronics companies without requiring stringent multi-agency approvals. As these recommendations are being examined, MeitY officials have stated their support for them, citing their importance in attracting high-tech investments without endangering national security.

India is enjoying a window of opportunity with global dynamics undergoing shifts. With U.S. trade policy being uncertain and a reorientation on global supply chains, India seeks to be an important destination for electronics manufacturing. Strategic engagement with select Chinese firms would hasten the process of technology absorption at the component stage and create employment.

Indian leadership, meanwhile, continues to stress that such flexibility will be limited in scope, transparent, and oriented around the national interest. Any lifting of restrictions will be closely scrutinized with country-level mechanisms put in place to ensure that the long-term technological sovereignty and security of the country will not be jeopardized.

Conclusion:

Changing economic realities and investment in China in electronics by India show it as having an evolving approach toward becoming a true manufacturing center. This new stage of pragmatic economic engagement is characterized by an investment model that is more technology-focused and selective.

The post India Eases Curbs on Chinese Investment in Electronics with Strategic Conditions appeared first on ELE Times.

Deposition equipment maker Aixtron SE in Herzogenrath, near Aachen, Germany says that the UK’s University of Cambridge has purchased a Close Coupled Showerhead system for 2D materials for its photonics and optoelectronics R&D...

For now it’s just a led and a resistor. Anode is soldered to the resistor. submitted by /u/Grid_Rider [link] [comments]

Along with introducing Carson's rule for bandwidth estimation, this article explains how to calculate the required transmission bandwidth based on either the sidebands or the total power of the signal.

I made a binary seven-segment wristwatch. Each segment represents a binary multiplier: segment B is 1, C is 2, D is 4, and so on. Project info submitted by /u/olxu [link] [comments]

Yep, I’ve used 1970’s to 1980’s era parts from Japan and Taiwan only. The whole thing is built around a mitsubishi jungle IC. The controller is external though. I have no way of testing it because analog TV was shut down a long time ago here in Czech Republic. Just built it out of love and compassion for RF circuits. Fun fact: I’ve spent 6 hours just soldering all the components into their respective holes. There isn’t a single hole unused on that perfboard. submitted by /u/A55H0L3_WindowsXP [link] [comments]

Hey everyone! I’d like to share a fun and useful project I recently built: a PI-controlled soldering iron system based on a Hakko handle, designed specifically for heat insert pressing into 3D prints. You can enjoy this project from a few different angles: A DIY Tool That Actually Works I originally bought a so-called "digital soldering iron" to make a heat press, but it turned out to be fake—it just used open-loop power control with a 7-segment display. No temperature sensor, no feedback, no reliability. So I decided to build my own closed-loop system using proper RTD feedback, MOSFET switching, and a real PI controller running on an STM32. Now it gives stable heat control, perfect for insert work. A Showcase for My Snapboard Platform This project is also a working demo of Snapboard, my modular prototyping platform for embedded hardware. It’s like a LEGO base for breakout boards—strong and swappable, yet reusable across multiple projects. The potentiometer, OLED display, and power modules all snap into place cleanly with perfboard support. It’s been rock solid for building functional prototypes. A Control-Theory Driven Design Instead of trial-and-error tuning or just using bang-bang control like most DIY temp controllers, I took a full control engineering approach: Collected step response data Fitted it to a first-order model Designed the PI gains using pole placement, not guesswork Analyzed performance metrics like settling time, overshoot, etc. You can get a ready-to-go PI controller without hand-tuning. I even wrote a short doc on the theory and design [Notion link here]. What You See: OLED display shows SP, PV, and OP Potentiometer sets the temperature Serial data logging for step response capture Clean 12 V/24 V DC input with a switching regulator RTD temperature sensing and MOSFET power control submitted by /u/menginventor [link] [comments]

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Credit goes to @i509VCB on the KiCAD Discord submitted by /u/cyao12 [link] [comments]

Images floating around. Heard this is unconfirmed. submitted by /u/RineMetal [link] [comments]

The family brings 18-channel monitoring and SPI-to-TPL bridge to electric vehicle and energy storage applications.

Hello everyone This is my first PCB design from scratch, made in KiCad 9.0 It will serve as a mainboard for my bluetooth remote controlled car Based around an Arduino Nano, it handles Driving motors (with L293D IC) An ultrasonic sensor A servo Rear status LEDs such as REVerse, BRaKe, Left turn signal, Right turn signal (like seen on real cars) Blinking the LEDs (with a 555 IC in the monostable configuration and a 74HC00 AND gate IC) An HC-05 Audio (a horn and an alarm (triggered by the ultrasonic sensor after a certain distance)) It is a 4-layered PCB with In1.Cu being a power plane for +5V, and B.Cu being a power plane for GND, F.Cu and In2.Cu being signal layers Has 4 2.00mm corner mounting holes Here are the KiCad project files in my GitHub repo' if anyone would like to take a closer look: https://github.com/darsh-agrawal71/bt-rc-car-pcb-kicad-prj Image #1: PCB screenshot (Red trace = F.Cu, Orange trace = In2.Cu) Image #2: Schematic Image #3: 3D View screenshot submitted by /u/Practical-Friend-960 [link] [comments]

Micron’s 256-Gb radiation-tolerant SLC NAND meets tight aerospace reliability benchmarks.

MACOM Technology Solutions Inc of Lowell, MA, USA (which designs and makes RF, microwave, analog and mixed-signal and optical semiconductor technologies) has assumed full operational control of the wafer fabrication facility in Research Triangle Park, NC, that it purchased from Wolfspeed Inc of Durham, NC, USA in December 2023...

Luminus Devices Inc of Sunnyvale, CA, USA — which designs and makes LEDs and solid-state technology (SST) light sources for illumination markets — has added to its MP-5050 Series of high-power LEDs with the new MP-5050-240P and MP-5050-810P models, which deliver what is claimed to be industry-leading efficiency and reliability, designed specifically for demanding outdoor and commercial lighting applications...

I've always thought that electronics where expensive and hard but after investing some time learning the basics I made this lil 555 timer PCB and I know there are some things that could be better but I'm really proud of my work submitted by /u/Inside-Ad8295 [link] [comments]

There have been numerous circuits published in EDN as design ideas (DI) for the past few months, centering around the “Flip ON Flop OFF” circuit originally published by Stephen Woodward. These are all designed for DC voltages less than 15 V, since this is the maximum power supply voltage of the CMOS ICs that were used in their design.

Wow the engineering world with your unique design: Design Ideas Submission Guide

There are several applications that use 48 VDC as the supply voltage, such as telecom equipment, solar panel controllers, and EV controllers. In general, DC on/off switches are bulky, as there is no current zero-breaking concept as in the case of AC circuits. A DC on/off switch will break the full load current, leading to arcing and contact erosion. Because of this, bulk-sized switches with higher current capacity are employed.

Figure 1’s circuit can flip on and flop off 48 VDC with a tiny push button. D1 is a 5.6-V Zener diode. It is connected to the base of the Q2 transistor. Its emitter voltage becomes around 5 VDC (Vz-Vbe).

ICs U1 and U2 operate with this 5 VDC voltage. When the pushbutton (PB) is pushed once momentarily, a small pulse is generated, which is counted by U1. Its LSB pin becomes HIGH, which is applied to the gate of Q1. Hence, it conducts, and the output gets 48 VDC. For the next push of PB, the LSB pin of U1 goes LOW, and the gate of Q1 becomes LOW, and Q1 stops conducting. This makes the output voltage go to zero. This action repeats for every push.

Figure 1 The flip on, flop off circuit for 48 V. The output gets 48V DC when you push PB once momentarily. For the next push, output becomes 0 V. U1 and U2 operate at 5VDC only. Connect the Vcc pins of U1 and U2 to VDD and the ground pins to VSS, as shown in the above circuit. Use heat sink for Q1 for higher currents.

Since PB encounters current around a milliamp, the low current, sleek PB is sufficient to switch ON or OFF the 48-V supply with high current. With a proper heatsink on Q1, this circuit can switch ON or OFF DC currents up to several amps as per the data sheet of Q1.

Both R1 and C1 are for PB switch debounce. Both R2 and C2 are for the power-on reset of U1.

If galvanic isolation is needed (this may not always be the case), you may connect an ON/OFF switch prior to the input. In this topology, on-load switching is taken care of by the PB-operated circuit, and the ON/OFF switch switches zero current only, so it does not need to be bulky. You can select a switch that passes the required load current. While switching ON, first close the ON/OFF switch and then operate PB to connect. While switching OFF, first push PB to disconnect and operate the ON/OFF switch.

Jayapal Ramalingam has over three decades of experience in designing electronics systems for power & process industries and is presently a freelance automation consultant.

Related Content

• Flip ON flop OFF
• Latching D-type CMOS power switch: A “Flip ON Flop OFF” alternative
• Flip ON flop OFF without a flip/flop
• Another simple flip ON flop OFF circuit
• Elaborations of yet another Flip-On Flop-Off circuit

The post Flip ON Flop OFF for 48-VDC systems appeared first on EDN.

The Keysight N9048B PXE EMI test receiver, paired with a standalone stream processing unit (SPU), delivers real-time, gapless 1-GHz time domain scan (TDS) bandwidth. With the SPU upgrade, the receiver covers 30 MHz to 1 GHz in a single step—down from three in the previous version—tripling EMI test speed. Together, the units enable faster, more accurate EMI testing.

With 1-GHz FFT bandwidth, the system accelerates EMI scans by covering the CISPR C and D bands in a single pass and supports user-selectable resolution bandwidths of 9 kHz, 120 kHz, and 1 MHz. Real-time, gapless capture ensures no transient events are missed, while high sensitivity and wide dynamic range reveal signals close to the noise floor.

The test setup shortens troubleshooting time from hours to minutes and fully complies with CISPR 16-1-1:2019 requirements. Additionally, the standalone SPU provides a path for future upgrades, offering long-term flexibility.

The Keysight N9048B PXE EMI receiver will be showcased at Techno-Frontier 2025 in Tokyo at the TOYO booth. Learn more about the N9048BSPU stream processing unit by viewing the flyer here.

N9048B PXE product page

Keysight Technologies 

The post 1-GHz TDS upgrade triples EMI test speed appeared first on EDN.