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Researchers have developed a switched-capacitor-based nine-level inverter that achieves a fourfold voltage and up to 96.5% efficiency.

Microchip’s Adaptec SmartRAID 4300 series of NVMe RAID storage accelerators speeds access to NVMe storage in AI data centers. It achieves this through a disaggregated architecture that separates storage software from the hardware layer, leveraging dedicated PCIe controllers to offload CPU processing and accelerate RAID operations. Microchip reports the SmartRAID 4300 achieves up to 7× higher I/O performance compared to the previous generation in internal testing.

In the SmartRAID 4300 architecture, storage software runs on the host CPU while the accelerator offloads parity-based redundancy tasks, such as XOR operations. This allows write operations to bypass the accelerator and go directly from the host CPU to NVMe drives at native PCIe speeds. By avoiding in-line bottlenecks, the design supports high-throughput configurations with up to 32 CPU-attached x4 NVMe devices and 64 logical drives or RAID arrays. It is compatible with both PCIe Gen 4 and Gen 5 host systems.

The SmartRAID 4300 accommodates NVMe and cloud-capable SSDs for versatile enterprise deployments. It uses architectural techniques like automatic core idling and autonomous power reduction to optimize efficiency. The accelerator also provides security features, including hardware root of trust, secure boot, attestation, and Self-Encrypting Drive (SED) support to ensure data protection.

For information on production integration, contact Microchip sales or an authorized distributor here.

SmartRAID 4300 product page 

Microchip Technology 

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EPCOS B3264xH double-sided metallized polypropylene film capacitors from TDK withstand pulse stress up to 6500 V/µs. Suited for resonant topologies—particularly LLC designs—these compact, AEC-Q200-compliant capacitors operate continuously from -55°C to +125°C, ensuring reliable performance in harsh environments.

The capacitors cover a rated DC voltage range of 630 V to 2000 V with capacitance values from 2.2 nF to 470 nF. Their specialized dielectric system, combining polypropylene with double-sided metallized PET film electrodes, enables both high pulse strength and current handling. These characteristics make them well-suited for onboard chargers and DC/DC converters in xEVs, as well as uninterruptible power supplies, industrial switch-mode power supplies, and electronic ballasts.

TDK reports that B3264xH capacitors offer high insulation resistance, low dissipation factor, and strong self-healing properties, resulting in a 200,000-hour service life at +85°C and full rated voltage. They are available in three lead spacings—10 mm, 15 mm, and 22.5 mm—to allow integration in space-constrained circuit layouts.

B3264xH product page

TDK

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With integrated display data channel (DDC) listeners, Diodes’ 3.3-V, quad-channel hybrid ReDrivers preserve HDMI signal integrity for high-resolution video transmission. The PI3HDX12311 supports HDMI 2.1 fixed rate link (FRL) signaling up to 12 Gbps and transition-minimized differential signaling (TMDS) up to 6 Gbps. The PI3HDX6311 supports HDMI 2.0 at up to 6 Gbps.

Both devices operate in either limited or linear mode. In HDMI 1.4 applications, they function as limited redrivers, using a predefined differential output swing—set via swing control—to maintain HDMI-compliant levels at the receptacle. For HDMI 2.0 and 2.1, they switch to linear mode, where the output swing scales with the input signal, effectively acting as a trace canceller. This mode remains transparent to link training signals and, in the PI3HDX12311, supports 8K video resolution and data rates up to 48 Gbps (12 Gbps per channel).

The PI3HDX12311 and PI3HDX6311 provide Dual-Mode DisplayPort (DP++) V1.1 level shifting and offer flexible coupling options, allowing AC, DC, or mixed coupling on both input and output signals. To reduce power consumption, the devices monitor the hot-plug-detect (HPD) pin and enter a low-power state if HPD remains low for more than 2 ms.

In 3500-unit quantities, the PI3HDX12311 costs $0.99 each, and the PI3HDX6311 costs $0.77 each.

PI3HDX12311 product page

PI3HDX6311 product page  

Diodes

The post Hybrid redrivers aid high-speed HDMI links appeared first on EDN.

KAGA FEI is expanding its Bluetooth LE portfolio with two Bluetooth 6.0 modules that offer different memory configurations. Like the existing EC4L15BA1, the new EC4L10BA1 and EC4L05BA1 are based on Nordic Semiconductor’s nRF54L series of wireless SoCs and integrate a built-in antenna.

The EC4L15BA1 offers the highest memory capacity, with 1.5 MB of NVM and 256 KB of RAM. For applications with lighter requirements, the EC4L10BA1 includes 1.0 MB of NVM and 192 KB of RAM, while the EC4L05BA1 provides 0.5 MB of NVM and 96 KB of RAM. This range enables use cases from industrial IoT and healthcare to smart home devices and cost-sensitive, high-volume designs.

EC4L10BA1 product page 

EC4L05BA1 product page 

KAGA FEI

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Toshiba’s TCD2728DG CCD linear image sensor uses lens reduction to cut random noise, enhancing image quality in semiconductor inspection equipment and A3 multifunction printers. As a lens-reduction type sensor, it optically compresses the image before projection onto the sensor. According to Toshiba, the TCD2728DG has lower output amplifier gain than the earlier TCD2726DG and reduces random noise by about 40%, down to 1.9 mV.

The color CCD image sensor features 7500 image-sensing elements across three lines, with a pixel size of 4.7×4.7 µm. It supports a 100-MHz data rate (50-MHz × 2 channels), enabling high-speed processing of large image volumes. This makes it well-suited for line-scan cameras in inspection systems that require real-time decision-making. A built-in timing generator and CCD driver simplify integration and help streamline system development.

The sensor’s input clocks accept a CMOS-level 3.3-V drive. It operates with 3.1- V to 3.5-V analog, digital, and clock driver supplies (VAVDD, VDVDD, VCKDVDD), plus a 9.5-V to 10.5-V supply for VVDD10. Typical RGB sensitivity values are 6.7 V/lx·s, 8.5 V/lx·s, and 3.1 V/lx·s, respectively.

Toshiba has begun volume shipments of the TCD2728DG CCD image sensor in 32-pin WDIPs.

TCD2728DG product page

Toshiba Electronic Devices & Storage 

The post CCD sensor lowers noise for clearer inspections appeared first on EDN.

Micron’s new SSD portfolio delivers faster speeds, more capacity, and better energy efficiency for AI workloads.

The following would apply to any moving vehicle, but just for the sake of clear thought, we will use the word “car”.

Imagine a car coming toward a radar antenna that is transmitting a microwave pulse which goes out toward that car and then comes back from that car in a time interval called “T1”. Then that same radar antenna transmits a second microwave pulse that also goes out toward that still oncoming car and then comes back from that car, but in a time interval called “T2”. This concept is illustrated in Figure 1.

Figure 1 Car radar timing where T1 is the time it takes for a first pulse to go out toward a vehicle get reflected back to the radiating source, and T2 is the time it takes for a second pulse to go out toward the same vehicle and get reflected back to the radiating source.

The further away the car is, the longer T1 and T2 will be, but if a car is moving toward the antenna, then there will be a time difference between T1 and T2 for which the distance the car has moved will be proportional to that time difference. In air, that scale factor comes to 1.017 nanoseconds per foot (ns/ft) of distance (see Figure 2).

Figure 2 Calculating roundtrip time for a radar signal required to catch a vehicle traveling at 55 mph and 65 mph.

Since we are interested in the time it takes to traverse the distance from the antenna to the car twice (round trip), we would measure a time difference of 2.034 ns/ft of car travel.

A speed radar measures the positional change of an oncoming or outgoing car. Since 60 mph equals 88 ft/s, we know that 55 mph comes to (80+2/3) ft/s. If the interval between transmitted radar pulses were one pulse per second, a distance of (80+2/3) feet would correspond to an ABS(T1-T2) time difference of 164.0761 ns. A difference in time intervals of more than that many nanoseconds would then be indicative of a driver exceeding a speed limit of 55 mph.

For example, a speed of 65 mph would yield 193.9081 ns, and on most Long Island roadways, it ought to yield a speeding ticket.

John Dunn is an electronics consultant, and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

Related Content

• Mattel makes a real radar gun, on the cheap
• Simple Optical Speed Trap
• Whistler’s DE-7188: Radar (And Laser) Detection Works Great
• Accidental engineering: 10 mistakes turned into innovation

The post Car speed and radar guns appeared first on EDN.

For its fiscal third-quarter 2025 (ended 27 June), Skyworks Solutions Inc of Irvine, CA, USA (which manufactures analog and mixed-signal semiconductors) has reported revenue of $965m, up 5% on $953.2m last quarter and 7% on $905.5m a year ago. This exceeds the $920–960 guidance, fueled by an upside in the Mobile segment and sustained strength across the Broad Markets segment...

submitted by /u/Victor464543 [link] [comments]

The term ‘machine learning’ is used to describe the process of turning the machines smarter day by day in today’s technologically advanced environment. Machine learning serves as the foundation for the creation of voice assistants, tailored recommendations, and other intelligent applications.

The core of this intelligence is the machine learning algorithm, through which a computer learns from data and then makes decisions to some lower or higher extent without human intervention.

This article will explore what these algorithms are, the types, and their common daily life application, in addition to the top 10 machine learning algorithms.

Machine learning algorithms are sequences of instructions or models that allow computers to learn patterns from data and make decisions or prediction under conditions of uncertainty without explicit programming. Such an algorithm helps machines improve their performance in some task over time by processing data and observing trends.

In simple words, these enable computers to learn from data, just as humans learn from experience.

Types of Machine Learning Algorithms:

Machine learning algorithms fall into three main types-

1. Supervised learning

These are systems of algorithms that work on data feeding from a system or set of systems and help form a conclusion from the data. In supervised learning, algorithms learn from labeled data, which means the dataset contains both input variables and their corresponding output. The goal is to train the model to make predictions or decisions. Common supervised learning algorithms include:

• Linear Regression
• Logistic Regression
• Decision Trees
• Random Forests
• Support Vector Machines
• Neural Networks

2. Unsupervised learning

In this type of algorithms, the machine learning system studies data for pattern identification. There is no answer key provided and human operator instructing the computer. Instead, the machine learns correlations and relationships by analysing the data available to it. In unsupervised learning, the machine learning algorithm applies its knowledge to large data sets. Common unsupervised learning techniques include:

• Clustering
• Association
• Principal Component Analysis (PCA)
• Autoencoders

3. Reinforcement learning

Reinforcement learning focuses on regimented learning. That is, a machine learning algorithm is given a set of actions, parameters, and an end value. Reinforcement learning is trial and error learning for the machine. It learns from past experiences and begins to modify its approach depending on circumstances.

• Q-learning
• Deep Q-Networks
• Policy Gradient Methods
• MCTS(Monte Carlo Tree Search)

Applications of Machine Learning Algorithm:

Many sectors utilize machine learning algorithms to improve decision-making and tackle complicated challenges.

• In transportation, machine learning enables self-driving cars and smart traffic systems
• In the healthcare sector, the algorithms promote disease diagnosis.
• In the finance industry, it power fraud detection, credit scoring and stock market forecasting.
• Cybersecurity relies on it for threat detection and facial recognition.
• Smart assistants, where NLP—drives voice recognition, language understanding, and contextual responses.

It also plays a vital role in agriculture, education, and smart city infrastructure, making it a cornerstone of modern innovation.

Machine Learning Algorithms Examples:

Machine learning algorithms are models that help computers learn from data and make predictions or decisions without being explicitly programmed. Examples include linear regression, decision trees, random forests, K-means clustering, and Q-learning, used across fields like healthcare, finance, and transportation.

Top 10 Machine Learning Algorithms:

1. Linear Regression

Linear regression is a supervised machine learning technique, used for predicting and forecasting continuous-valued sales or housing prices. It is a technique that has been borrowed from statistics and is applied when one wishes to establish a relationship between one input variable (X) and one output variable (Y) using a straight line.

2. Logistic Regression

Logistic regression is a supervised learning algorithm primarily used for binary classification problems. It allows to classify input data into two classes on the basis of probability estimate and set threshold. Hence, for the need to classify data into distinct classes, logistic regression stands useful in image recognition, spam email detection, or medical diagnosis.

3. Decision Tree

Decision trees are supervised algorithms developed to address problems related to classification and prediction. It also looks very similar to a flow-chart diagram: a root node positioned at the top, which poses the first question on the data; given the answer, the data flows down one of the branches to another internal node with another question leading further down the branches. This continues until the data reach an end node

4. Random Forest

Random forest is an algorithm which offers an ensemble of decision trees for classification and predictive modelling purposes. Unlike a single decision tree, random forest offers better predictive accuracy by combining predictions from many decision trees.

5. Support Vector Machine (SVM)

Support vector machine is a supervised learning algorithm that can be applied for both classification and the prediction of instances. The appeal of SVM lies in the fact that it can build reliable classifiers even when very small samples of data are available. It builds a decision boundary called a hyperplane; a hyperplane in two-dimensional space is simply a line separating two sets of labeled data.

6. K-Nearest Neighbors (KNN)

K-nearest neighbor (KNN) is a supervised learning model enhanced for classification and predictive modelling. K-nearest neighbour gives a clue about how the algorithm approaches classification: it will decide output classes based on how near they are to other data points on a graph.

7. Naive Bayes

Naive Bayes describes a family of supervised learning algorithms used in predictive modelling for the binary or multi-class classification problems. It assumes independence between the features and uses Bayes’ Theorem and conditional probabilities to give an estimate of the likelihood of classification given all the feature values.

8. K-Means Clustering

K-means is an unsupervised clustering technique for pattern recognition purposes. The objective of clustering algorithms is to partition a given data set into clusters such that the objects in one cluster are very similar to one another. Similar to the KNN (Supervised) algorithm, K-means clustering also utilizes the concept of proximity to find patterns in data.

9. Principal Component Analysis (PCA)

Principal Component Analysis (PCA) is a statistical technique used to summarize information contained in a large data set by projecting it onto a lower-dimensional subspace. Sometimes, it is also regarded as a dimensionality reduction technique that tries to retain the vital aspects of the data in terms of its information content.

10. Gradient Boosting (XGBoost/LightGBM)

The gradient boosting methods belong to an ensemble technique in which weak learners are iteratively added, with each one improving over the previous ones to form a strong predictive model. In the iterative process, each new learner is added to correct the errors made by the previous models, gradually improving the overall performance and resulting in a highly accurate final model

Conclusion:

Machine learning algorithms are used in a variety of intelligent systems: from spam filters and recommendation engines to fraud detection and even autonomous vehicles. Knowledge of the most popular algorithms, such linear regression, decision trees, and gradient boosting, explains how machines learn, adapt, and assist in smarter decision-making across industries. As data grows without bounds, the mastery of these algorithms becomes ever so vital in the effort toward innovation and problem solving in this digital age.

The post Top 10 Machine Learning Algorithms appeared first on ELE Times.

In telecommunication applications, target impedance serves as a crucial benchmark for power distribution network (PDN) design. It ensures that the die operates within an acceptable level of rail voltage noise, even under the worst-case transient current scenarios, by defining the maximum allowable PDN impedance for the power rail on the die.

This article will focus on the optimization techniques to meet the target impedance using a point-of-load (PoL) device, while providing valuable insights and practical guidance for designers seeking to optimize their PDNs for reliable and efficient power delivery.

Defining target impedance

With the rise of high-frequency signals and escalating power demands on boards, power designers are prioritizing noise-free power distribution that can efficiently supply power to the IC. Controlling the power delivery network’s impedance across a certain frequency range is one approach to guarantee proper operation of high-speed systems and meet performance demands.

This impedance can generally be estimated by dividing the maximum allowed ripple voltage by the maximum expected current step load. The power delivery network’s target impedance (ZTARGET) can be calculated with below equation:

Achieving ZTARGET across a wide frequency spectrum requires a power supply at lower frequencies, combined with strategically placed decoupling capacitors at middle and higher frequencies. Figure 1 shows the impedance frequency characteristics of multi-layer ceramic capacitors (MLCCs).

Figure 1 The impedance frequency characteristics of MLCCs are shown across a wide frequency spectrum. Source: Monolithic Power Systems

Maintaining the impedance below the calculated threshold ensures that even the most severe transient currents generated by the IC, as well as induced voltage noise, remain within acceptable operational boundaries.

Figure 2 shows the varying target impedance across different frequency ranges, based on data from Qualcomm website. This means every element in the power distribution must be optimized at different frequencies.

Figure 2 Here is a target impedance example for different frequency ranges. Source: Qualcomm

Understanding PDN impedance

In theory, a power rail aims for the lowest possible PDN impedance. However, it’s unrealistic to achieve an ideal zero-impedance state. A widely adopted strategy to minimize PDN impedance is placing various decoupling capacitors beneath the system-on-chip (SoC), which flattens the PDN impedance across all frequencies. This prevents voltage fluctuations and signal jitter on output signals, but it’s not necessarily the most effective method to optimize power rail design.

Three-stage low-pass filter approach

To further explore optimizing power rail design, the fundamentals of PDN design must be re-examined in addition to considering new approaches to achieve optimal performance. Figure 3 shows the PDN conceptualized as a three-stage low-pass filter, where each stage of this network plays a specific role in filtering and stabilizing the current drawn from the SoC die.

Figure 3 The PDN is conceptualized as a three-stage low-pass filter. Source: Monolithic Power Systems

The three-stage low-pass filter is described below:

1. Current drawn from the SoC die: The process begins with current being drawn from the SoC die. Any current drawn is filtered by the package, which interacts with die-side capacitors (DSCs). This initial filtering stage reduces the current’s slew rate before it reaches the PCB socket.
2. PCB layout considerations and MLCCs: Once the current passes through the PCB ball grid arrays (BGAs), the second stage of filtering occurs as the current flows through the power planes on the PCB and encounters the MLCCs. During this stage, it’s crucial to focus on selecting capacitors that effectively operate at specific frequencies. High-frequency capacitors placed beneath the SoC do not significantly influence lower frequency regulation.
3. Voltage regulator (VR) with power planes and bulk capacitors: The final stage involves the VR and bulk capacitors, which work together to stabilize the power supply by addressing lower-frequency noise.

The PDN’s three-stage approach ensures that each component contributes to minimizing impedance across different frequency bands. This structured methodology is vital for achieving reliable and efficient power delivery in modern electronic systems.

Case study: Telecom evaluation board analysis

This in-depth examination uses a telecommunications-specific evaluation board from MPS, which demonstrates the capabilities of the MPQ8785, a high-frequency, synchronous buck converter, in a real-world setting. Moreover, this case study underlines the importance of capacitor selection and placement to meet the target impedance.

To initiate the process, PCB parasitic extraction is performed on the MPS evaluation board. Figure 4 shows a top view of the MPQ8785 evaluation board layout, where two ports are selected for analysis. Port 1 is positioned after the inductor, while Port 2 is connected to the SoC BGA.

Figure 4 PCB parasitic extraction is performed on the telecom evaluation board. Source: Monolithic Power Systems

Capacitor models from vendor websites are also included in this layout, including the equivalent series inductance (ESL) and equivalent series resistance (ESR) parasitics. As many capacitor models as possible are allocated beneath the SoC in the bottom of the PCB to maintain a flat impedance profile.

Table 1 Here is the initial capacitor selection for different quantities of capacitors targeting different frequencies. Source: Monolithic Power Systems

Figure 5 shows a comparison of the target impedance profile defined by the PDN mask for the core rails to the actual initial impedance measured on the MPQ8785 evaluation board using the initially selected capacitors. This graphical comparison enables a direct assessment of the impedance characteristics, facilitating the evaluation of the PDN performance.

Figure 5 Here is a comparison between the target impedance profile and initial impedance using the initially selected capacitors. Source: Monolithic Power Systems

Based on the data from Figure 5, the impedance exceeds the specified limit within the 300-kHz to 600-kHz frequency range, indicating that additional capacitance is required to mitigate this issue. Introducing additional capacitors effectively reduces the impedance in this frequency band, ensuring compliance with the specification.

Notably, high-frequency capacitors are also observed to have a negligible impact on the impedance at higher frequencies, suggesting that their contribution is limited to specific frequency ranges. This insight informs optimizing capacitor selection to achieve the desired impedance profile.

Through an extensive series of simulations that systematically evaluate various capacitor configurations, the optimal combination of capacitors required to satisfy the impedance mask requirements was successfully identified.

Table 2 The results of this iterative process outline the optimal quantity of capacitors and total capacitance. Source: Monolithic Power Systems

The final capacitor selection ensures that the PDN impedance profile meets the specified mask, thereby ensuring reliable power delivery and performance. Figure 6 shows the final impedance with optimized capacitance.

Figure 6 The final impedance with optimized capacitance meets the specified mask. Source: Monolithic Power Systems

With a sufficient margin at frequencies above 10 MHz, capacitors that primarily affect higher frequencies can be eliminated. This strategic reduction minimizes the occupied area and decreases costs while maintaining compliance with all specifications. Performance, cost, and space considerations are effectively balanced by using the optimal combination of capacitors required to satisfy the impedance mask requirements, enabling robust PDN functionality across the operational frequency range.

To facilitate the case study, the impedance mask was modified within the 10-MHz to 40-MHz frequency range, decreasing its overall value to 10 mΩ. Implementing 10 additional 0.1-µF capacitors was beneficial to reduce impedance in the evaluation board, which then effectively reduced the impedance in the frequency range of interest.

Figure 7 shows the decreased impedance mask as well as the evaluation board’s impedance response. The added capacitance successfully reduces the impedance within the specified frequency range.

Figure 7 The decreased PDN mask with optimized capacitance reduces impedance within the specified frequency range. Source: Monolithic Power Systems

Compliance with impedance mask

This article used the MPQ8785 evaluation board to optimize PDN performance, ensuring compliance with the specified impedance mask. Through this optimization process, models were developed to predict the impact of various capacitor types on impedance across different frequencies, which facilitates the selection of suitable components.

Capacitor selection for optimized power rail design depends on the specific impedance mask and frequency range of interest. A random selection of capacitors for a wide variety of frequencies is insufficient for optimizing PDN performance. Furthermore, the physical layout must minimize parasitic effects that influence overall impedance characteristics, where special attention must be given to optimizing the layout of capacitors to mitigate these effects.

Marisol Cabrera is application engineer manger at Monolithic Power Systems (MPS).

Albert Arnau is application engineer at Monolithic Power Systems (MPS).

Robert Torrent is application engineer at Monolithic Power Systems (MPS).

Related Content

• SoC PDN challenges and solutions
• Power 107: Power Delivery Networks
• Debugging approach for resolving noise issues in a PDN
• Optimizing capacitance in power delivery network (PDN) for 5G
• Power delivery network design requires chip-package-system co-design approach

The post Impedance mask in power delivery network (PDN) optimization appeared first on EDN.

Vishay Intertechnology, Inc. introduced two new IHDM Automotive Grade edge-wound, through-hole inductors in the 1107 case size with soft saturation current to 422 A. Featuring a powdered iron alloy core technology, the Vishay Inductors Division’s IHDM-1107BBEV-2A and IHDM-1107BBEV-3A provide stable inductance and saturation over a demanding operating temperature range from -40 °C to +180 °C with low power losses and excellent heat dissipation.

The edge-wound coil of the devices released provides low DCR down to 0.22 mΩ, which minimizes losses and improves rated current performance for increased efficiency. Compared to competing ferrite-based solutions, the IHDM-1107BBEV-2A and IHDM-1107BBEV-3A offer 30 % higher rated current and 30 % higher saturation current levels at +125 °C. The inductors’ soft saturation provides a predictable inductance decrease with increasing current, independent of temperature.

With a high isolation voltage rating up to 350 V, the AEC-Q200 qualified devices are ideal for high current, high temperature power applications, including DC/DC converters, inverters, on-board chargers (OBC), domain control units (DCU), and filters for motor and switching noise suppression in internal combustion (ICE), hybrid (HEV), and full-electric (EV) vehicles. The inductors are available with a selection of two core materials for optimized performance depending on the application.

Standard terminals for the IHDM-1107BBEV-2A and IHDM-1107BBEV-3A are stripped and tinned for through-hole mounting. Vishay can customize the devices’ performance — including inductance, DCR, rated current, and voltage rating — upon request. Customizable mounting options include bare copper, surface-mount, and press fit. To reduce the risk of whisker growth, the inductors feature a hot-dipped tin plating. The devices are RoHS-compliant, halogen-free, and Vishay Green.

The post Vishay Intertechnology Automotive Grade IHDM Inductors Offer Stable Inductance and Saturation at Temps to +180 °C appeared first on ELE Times.

What does a wireless standard look like when shaped by edge cases? Qualcomm has a reliability-focused vision for Wi-Fi 8, slated for 2028.

For second-quarter 2025, gallium nitride (GaN) power IC and silicon carbide (SiC) technology firm Navitas Semiconductor Corp of Torrance, CA, USA has reported revenue of $14.49m, down on $20.47m a year ago but up slightly on $14m last quarter...

Materials, networking and laser technology firm Coherent Corp of Saxonburg, PA, USA has inaugurated its new $127m manufacturing facility in Nhon Trach Industrial Park, Dong Nai province, southern Vietnam, which will produce precision-engineered materials and photonics components used in applications spanning smartphones and electric vehicles to advanced medical devices...

Unreliable data is a serious problem for smart meters. This industry article explains why, and presents a solution in the form of embedded software.

I posted V1.0 here a few months ago and a couple people pointed out some problems. I also found some of my own. I need to change the design, so I've made V1.1. I've made a lot of improvements to the board and my documentation. All of my progress can be tracked in the v1.1 branch on my github. I am planning on ordering new boards soon. Any feedback would be appreciated. submitted by /u/SuperCookieGaming [link] [comments]

We’ve seen lots of interesting conversations and Design Idea (DI) collaboration devising circuits for power switching using inexpensive (and cute!) momentary-contact SPST pushbuttons. A recent and interesting extension of this theme by frequent contributor R Jayapal addresses control of relatively high DC voltages: 48 volts in his chosen case.

Wow the engineering world with your unique design: Design Ideas Submission Guide

In the course of implementing its high voltage feature, Jayapal’s design switches the negative (Vss a.k.a. “ground”) rail of the incoming supply instead of the (more conventional) positive (Vdd) rail. Of course, there’s absolutely nothing physically wrong with this choice (certainly the electrons don’t know the difference!). But because it’s a bit unconventional, I worry that it might create possibilities for the unwary to make accidental, and potentially destructive, misconnections.

Figure 1’s circuit takes a different tack to avoid that.

Figure 1 Flip ON/Flop OFF referenced to the V+ rail. If V+ < 15v, then set R4 = 0 and omit C2 and Z1. Ensure that C2’s voltage rating is > (V+ – 15v) and if V+ > 80v, R4 > 4V+2

Figure 1 returns to an earlier theme of using a PFET to switch the positive rail for power control, and a pair of unbuffered CMOS inverters to create a toggling latch to control the FET. The basic circuit is described in “Flip ON Flop OFF without a Flip/Flop.”

What’s different here is that all circuit nodes are referenced to V+ instead of ground, and Zener Z1 is used to synthesize a local bias reference. Consequently, any V+ rail up to the limit of Q1’s Vds rating can be accommodated. Of course, if even that’s not good enough, higher rated FETs are available.

Be sure to tie the inputs of any unused U1 gates to V+.

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

Related Content

• Flip ON flop OFF
• Flip ON Flop OFF for 48-VDC systems
• Flip ON Flop OFF without a Flip/Flop
• Elaborations of yet another Flip-On Flop-Off circuit
• Latching D-type CMOS power switch: A “Flip ON Flop OFF” alternative

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