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In a move that cements India’s transition from a consumer to a producer in the global silicon race, Prime Minister Narendra Modi officially inaugurated the Kaynes Semicon OSAT (Outsourced Semiconductor Assembly and Test) facility on March 31, 2026.

The ₹3,300 crore plant, located in the industrial heart of Sanand, marks the second major semiconductor unit to go operational in Gujarat within 900 days, following the earlier launch of the Micron facility. This rapid execution underscores the momentum of the India Semiconductor Mission (ISM) 2.0, as the country aggressively pursues a slice of the $110 billion global chip market.

A Global Export Hub

While domestic self-reliance is a key driver, the Kaynes plant is looking outward. During the ceremony, the first batch of Intelligent Power Modules (IPMs), sophisticated components that integrate 17 individual chips, was presented to Stephen Chang, CEO of Alpha & Omega Semiconductor, a California-based anchor customer.

“Today, a new bridge has been formed between Sanand and Silicon Valley,” the Prime Minister stated during his address. “The modules made here will reach American companies and, from there, power the world.”

Key Specifications of the Sanand Plant

The facility is designed for high-volume, high-precision manufacturing, focusing on sectors that are currently seeing explosive growth:

Feature	Details
Investment	₹3,300 Crore
Production Capacity	Approx. 6.3 Million chips per day
Primary Products	Intelligent Power Modules (IPMs), Multi-chip modules
Target Industries	Electric Vehicles (EVs), Industrial Automation, 5G Infrastructure
Timeline	From Cabinet approval to production in 14 months

The “Techade” Vision

The inauguration is more than just a corporate milestone; it is a strategic piece of the “India Techade” vision. Unlike traditional manufacturing, the Kaynes plant focuses on the back-end of the semiconductor value chain, like assembly, testing, and packaging, which has historically been a bottleneck for Indian electronics.

Union IT Minister Ashwini Vaishnaw highlighted the speed of the project, noting that the plant moved from foundation-laying to commercial production in record time. He also pointed to the growing “Sanand-Dholera” cluster, which is being modelled after global hubs like Hsinchu in Taiwan and Gyeonggi in South Korea.

Building the Talent Pipeline

To sustain this growth, Kaynes Semicon announced a memorandum of understanding with SVNIT Surat to develop a specialised workforce. This partnership aims to bridge the gap between academic theory and the rigorous standards of semiconductor cleanrooms, ensuring a steady stream of engineers for the 10 major chip projects currently approved across six Indian states.

As the ribbon was cut in Sanand, the message to the global tech community was clear: India is no longer just waiting for the future of hardware; it is assembling it.

The facility has already reported early execution success, having shipped approximately 900 multi-chip modules (IPM5) just days before the formal inauguration, signalling high operational readiness for its export commitments.

By: Shreya Bansal, Sub-Editor

The post Why Every EV & 5G Phone Could Soon Be Powered by Gujarat appeared first on ELE Times.

Intelligent power and sensing technology firm onsemi of Scottsdale, AZ, USA says that its hybrid power integrated modules (PIMs) will be featured in Sineng Electric’s next-generation 430kW liquid-cooled string energy storage systems (ESS) and 320kW utility-scale solar inverter. The design win builds upon the long-standing collaboration between onsemi and Sineng to deliver high-performance, future-ready solutions in the growing renewable energy and AI infrastructure markets...

Студенти ФСП відвідали місто Славутич Інформація КП чт, 04/02/2026 - 10:54

Alligator Automations India Pvt. Ltd., a manufacturer of end-of-line packaging automation systems, has reduced engineering effort in electrical design by around 50% by implementing WSCAD’s E-CAD solution.

The company’s ten-person electrical engineering team now uses WSCAD for creating electrical schematics, control cabinet design, and project documentation. Previously, tasks such as wire numbering, device grouping, and bill-of-materials generation had to be performed manually, resulting in project delays and an increased risk of errors. After switching to WSCAD, many of these steps are now automated, significantly improving both efficiency and design accuracy.

“Tasks that previously required manual work are now automated,” says Sagar Bhavsar, Control Engineering Manager at Alligator Automations. “Wire numbering alone now takes roughly half the time, allowing our team to focus more on complex design and optimisation tasks.”

Alligator Automations develops customised automation solutions, including robotic palletising systems, packaging automation, automatic loading systems, and intralogistics conveyor technology. Projects cover the entire value chain – from design and development to manufacturing, installation, commissioning, and long-term support for customers in industries such as food & beverage, paint & cement, fertiliser & petrochemicals, as well as tyre and agro industries.

“Automation projects are becoming increasingly complex while engineering timelines continue to shrink,” says Dr Axel Zein, CEO of WSCAD. “At the same time, AI is fundamentally changing how electrical engineering is performed. By automating documentation, verification, and knowledge retrieval, engineers can focus more on system design and optimisation instead of repetitive tasks. The Alligator Automations example demonstrates how standardising the E-CAD environment can significantly increase engineering efficiency.”

Beyond schematic creation, WSCAD supports precise 2D and 3D control cabinet layouts, automatic wire routing, and direct data transfer to cabinet manufacturing systems. This eliminates media discontinuities and reduces sources of error. AI-supported design, documentation, and multilingual translation capabilities further accelerate project delivery while ensuring compliance and data quality.

The post WSCAD ELECTRIX AI Cuts 50% Engineering Effort For Alligator Automations appeared first on ELE Times.

Vishay Intertechnology has introduced a new Automotive Grade photovoltaic MOSFET driver that is the first such device in the compact SMD-4 package to provide a creepage distance of 8 mm and mould compound with a comparative tracking index (CTI) of 600. Designed to increase safety and reliability in high voltage automotive applications — while simplifying designs and reducing costs — the Vishay Semiconductors VODA1275 features the industry’s fastest turn-on times and the highest open circuit voltage and short circuit current in its class.

Classified as providing reinforced isolation, the device delivers an open circuit voltage of 20 V typical, short circuit current of 20 μA, and turn-on time of 80 μs, which is three times faster than competing devices. These characteristics enable quicker and more reliable driving of MOSFETs and IGBTs in high-voltage systems. In addition, the device’s working isolation voltage of 1260 Vpeak and isolation test voltage of 5300 VRMS make it ideal for 800 V+ battery systems.

AEC-Q102 qualified, the VODA1275 is intended for use in pre-charge circuits, wall chargers, and battery management systems (BMS) for electric (EV) and hybrid electric (HEV) vehicles. While designers previously had to use two MOSFET drivers in series to generate the higher voltages required in these applications, the device’s high open-circuit output voltage allows them to use just one, saving space and lowering costs. In addition, the driver enables the creation of custom solid-state relays to replace legacy electromechanical relays in next-generation vehicles.

The optically isolated VODA1275 draws all the current required to drive its internal circuitry from an infrared emitter on the low-voltage side of the isolation barrier. This construction simplifies designs and lowers costs by eliminating the need for an external power supply. The MOSFET driver is RoHS-compliant, halogen-free, and Vishay Green.

The post Vishay Intertechnology Automotive Grade Photovoltaic MOSFET Driver Boosts Reliability and Lowers Costs in High Voltage Systems appeared first on ELE Times.

Two TVS diode series from Littelfuse provide DO-160 Waveform 5A Level 5 lightning protection for avionics, military, and other mission-critical systems. The SM15KPA-HR/HRA and SM30KPA-HR/HRA offer peak pulse power ratings of 15 kW and 30 kW (10/1000 µs), respectively, protecting I/O lines, power buses, and sensitive electronics from lightning-induced transients and high-energy surges.

Both families offer fast response times—typically less than 1 ps from 0 V to VBR minimum—30-kV ESD protection per IEC 61000-4-2 on data lines, and low incremental surge resistance. The devices remain stable across a junction temperature range of –55°C to +150°C. While all diodes undergo high-reliability 100% screening tests, the HR versions additionally pass MIL-STD-750 Group B tests for extra test rigor and extended reliability margins.

The TVS diodes come in compact SPD4-1 surface-mount packages compatible with automated assembly. These packages reduce weight and board space while eliminating the through-hole mounting typically required for high-energy TVS components.

The SM15KPA-HR, SM15KPA-HRA, SM30KPA-HR, and SM30KPA-HRA series are available in tape-and-reel format in quantities of 500. Samples can be requested through authorized Littelfuse distributors worldwide.

Littelfuse

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Infineon’s TDM24745T quad-phase power module with trans-inductor voltage regulator (TLVR) magnetics provides high current density for AI workloads. Integrating four power stages, proprietary magnetics, and decoupling capacitors in a compact 9×10×5-mm package, the module achieves 2 A/mm² and delivers up to 320 A peak.

The device optimizes transient response and supports the high-current core rails required by advanced GPU and AI processors in both lateral and vertical power delivery configurations. Powered by OptiMOS-6 MOSFETs, it offers enhanced efficiency and thermal performance in dense AI server designs. The TLVR architecture further improves transient performance while reducing required output capacitance by up to 50%.

The TDM24745T power module integrates with Infineon’s end-to-end AI server power delivery ecosystem. Availability was not disclosed at the time of this announcement. For more information about Infineon’s voltage regulation solutions for AI and data centers, click here.

Infineon Technologies 

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Diodes has added a 100-V MOSFET to its lineup of 40-V to 80-V devices, all in 8×8-mm gullwing-leaded packages for automotive systems. With a maximum on-resistance of 1.5 mΩ, the DMTH10H1M7SPGWQ is well suited for 48-V BLDC motor drives used in power steering and braking systems. Like other family members, it minimizes conduction losses, reducing heat generation and maximizing overall efficiency.

The MOSFET’s PowerDI8080-5 package occupies a footprint of just 64 mm², approximately 40% less than the legacy TO-263 (D2PAK). It also offers a slim off-board profile of 1.7 mm. Copper clip die bonding reduces thermal resistance to as low as 0.3°C/W, enabling drain currents as high as 847 A without risk of damage. The gull-wing lead configuration supports automated optical inspection and enhances temperature-cycling reliability.

AEC-Q101 qualified, the DMTH10H1M7SPGWQ is rated to +175°C for high-ambient-temperature operation. One-hundred-percent unclamped inductive switching (UIS) testing during production ensures reliable, robust end applications.

The DMTH10H1M7SPGWQ is priced at $1.71 each in quantities of 5000. Contact sales via the product page for availability and purchase details.

Diodes

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The 40 LHE linear position sensor from Vishay measures strokes from 0 to 40 mm with ±1% full-stroke accuracy. Using Hall effect technology, it delivers 12-µm resolution and a lifespan exceeding 10 million cycles, making it well-suited for servo loop motion control systems that monitor small displacements. Typical applications include infrastructure integrity monitoring (crackmeters), in-line process measurement, industrial and medical robotic gripping, and throttle/pedal sensing in e-bikes and motorcycles.

Built for harsh environments, the 40 LHE operates from -40°C to +85°C and features IP67 sealing. It withstands high-frequency vibration up to 20 g and shock up to 50 g, with integrated input protections against reverse voltage (-10 VDC) and overvoltage (+20 VDC).

Its compact 35×14.5×28-mm design includes two face-mounting holes for horizontal or vertical installation. The sensor is available with or without a spring return and offers analog ratiometric or PWM output, with a recommended load resistance of 1 kΩ. It operates from a 5-VDC ±10% supply and draws less than 16 mA typically.

Samples and production quantities of the 40 LHE are available now, with 12-week lead times.

40 LHE product page 

Vishay Intertechnology 

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Leveraging IsoShield multichip packaging, TI’s isolated power modules deliver up to 3× the power density of discrete devices. The UCC34141-Q1 and UCC33420 reduce solution size by as much as 70% in isolated power designs for applications ranging from data centers to EVs.

IsoShield co-packages a planar transformer and isolated power stage to provide functional, basic, and reinforced isolation. This architecture supports distributed power and helps meet functional safety requirements by avoiding single-point failures.

The UCC34141-Q1 is an automotive-qualified 5-kVRMS DC/DC module for SiC and IGBT isolated gate drivers. It provides 1.5 W typical output at 85°C ambient, with dual outputs set by resistor dividers. A 5.5-V to 20-V input range and adjustable UVLO support EV battery voltages and regulated rails, while VIN transients up to 28 V are tolerated. 

The UCC33420 is an industrial 3-kVRMS DC/DC module offering up to 1.5 W of isolated output. It supports a 4.5-V to 5.5-V input and regulates a 5.0-V output with selectable 5.5-V headroom. Multiple protection features are integrated in its 4×5×1-mm package.

The UCC34141-Q1 and UCC33420 are available in preproduction and production quantities, respectively. Evaluation modules are available for both.

Texas Instruments  

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some time ago I bought this clock for few dollars at flew market. display was run out, so I decided to create new internals - based on ESP, WIFI and dot -matrix LED display. easiest way was to use bread board and some wires. I like to make some things with ESP modules - it helps to prolong life for unexpected things. My old fridge is next 😁 submitted by /u/Regular-Host-7738 [link] [comments]

EPC Space LLC of Andover, MA, USA (which provides high-reliability radiation-hardened enhancement-mode gallium nitride-on-silicon discrete transistors, ICs and modular devices for power management in space and other harsh environments) has announced two new additions to its family of demonstration and evaluation boards supporting applications including half-bridge connected point-of-load (POL) converter power stages, single- and multi-phase motor drivers, and Class-D single- and full-bridge stages...

NUBURU Inc of Centennial, CO, USA (a dual-use defense & security platform company focused on non-kinetic effects, directed-energy technologies, and software-orchestrated defense systems) says that its subsidiary Lyocon S.r.l. (an Italian laser-technology company specializing in the design, manufacturing and integration of high-power blue laser systems for industrial applications) has secured an initial deployment order for its portable directed-energy laser dazzler system for counter-drone (C-UAV) defense applications from a tier-one government-owned defense electronics organization operating within a centralized government procurement framework in a major Asia–Pacific defense market...

Silvaco Group Inc of Santa Clara, CA, USA — which provides AI-enabled technology computer-aided design (TCAD), electronic design automation (EDA) software and semiconductor intellectual property (SIP) for process and device development — has announced an expanded strategic partnership with Taiwan-based silicon and silicon carbide power device developer and and manufacturer Advanced Power Electronics Corp (APEC)...

If your favorite tool is a hammer, every problem will look like a nail. Abraham Maslow

Given how often I tinker with the LM555 and LMC555 analog timers, Maslow might have written that famous aphorism specifically for me. And it. Well, here I go again. Bang bang.

Figure 1’s circuit morphs the versatile 555 into a circuit that’s quite different from its usual role as an analog oscillator or timer. Here it’s combined with an NTC (negative tempco) thermistor, and one (or optionally two) resistors to make a resistor-programmed ON/OFF thermostat. It’s easily configured for heating or cooling.

Here’s how it works.

Figure 1 Basic bang bang heating configuration. Setpoint thermistor resistance = Rb/2. Optional Rh sets desired temperature hysteresis. Output rated at up to 15 volts and 300 mA = 4.5 W

Wow the engineering world with your unique design: Design Ideas Submission Guide

One of the secrets (or at least scantily documented) features of the 555 is what happens if you tie Threshold (pin 6) to Vdd as shown in Figure 1. What happens is Trigger (pin 7) then becomes an inverting analog comparator input that drives Output (3) and Discharge (7) high if Trigger < Vdd/3, and low if Trigger > Vdd/3.

When you combine that action with an NTC thermistor and bias resistor Rb as shown, presto! You get a simple but practical thermostat. It turns power (and a substantial amount of it: up to 15 V and 300 mA) ON to the load (e.g., a resistive heater) if the thermistor’s temperature is cooler than the setpoint (thermistor resistance > Rb/2). Power goes OFF when the temperature is warmer (thermistor < Rb/2). 

But wait, there’s more. Because accurate thermostatic action depends only on resistor ratios rather than absolute voltages, V+ needn’t be regulated. In fact, if the load isn’t bothered by ripple (e.g., a resistor heater certainly won’t care), it doesn’t even need to be filtered!

Furthermore, if you swap the positions of the thermistor and resistor as shown in Figure 2, and connect a cooling fan (or perhaps a thermoelectric cooler), the temperature regulation inverts. It will now maintain a constant maximum instead of a minimum temperature. If the output load is inductive (e.g., a fan motor), don’t worry about possible inductive transients. The LM555 output pin includes its own kickback protection.

Figure 2 Cooling configuration: Setpoint thermistor resistance = 2Rb.

If hysteresis (dT) is required, for typical NTC tempcos (~4 %/oC), an easy (if approximate) rule of thumb value for Rh = 680k/dToC.

Figure 3 Typical configurations for 50oC setpoint.  Heating (left), Cooling (right) with ~1o hysteresis.

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

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• 555 Temperature Controller Circuit
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The post LM555 begets basic bang bang thermostat appeared first on EDN.

💥 Конкурс «Передова фундаментальна наука в Україні 2027-2029» kpi ср, 04/01/2026 - 14:14

​​📢 Національним фондом досліджень України оголошено конкурс «Індивідуальні наукові проєкти 2027-2028» kpi ср, 04/01/2026 - 14:00

Deepak Shankar, founder of Mirabilis Design and developer of VisualSim Architect platform for chip and system designs, has created this cartoon for electronics design engineers.

The post The system architect’s sketchbook: The football has main character energy appeared first on EDN.

Semiconductor production test and reliability qualification equipment supplier Aehr Test Systems of Fremont, CA, USA has received an initial order from a major new customer that is “a global leader in networking products and solutions” and a “major supplier to the data-center optical transceiver market”. The customer is developing advanced silicon photonics-based transceivers for data-center networking and optical I/O applications to address the rapidly accelerating demand for high-speed fiber-optic communication links in hyperscale AI and cloud data centers...

AI has become EDA’s favorite buzzword, but behind the keynotes and product names the reality is far messier. Cadence, Synopsys, and Siemens EDA are racing to brand incremental heuristics as “platform AI,” while agentic startups promise copilots that mostly smooth over the pain of using legacy tools.

At the same time, giants in the chip design industry—the users of EDA—like Samsung and Nvidia are quietly assembling their own internal AI stacks, universities are sidelined from real industrial data, and foundation model labs like OpenAI and DeepMind are treated as sophisticated pattern-matching systems rather than creators of true intelligence.

This article argues that all four camps are, in different ways, missing the real opportunity: using AI to change what kinds of hardware–software systems we can verify at all, rather than just speeding up what we already do.

It traces how business incentives, closed ecosystems, and data hoarding are holding the field back—and outlines what a genuinely transformative, open, and collaborative AI-for-chips ecosystem would need to look like.

The current AI content in EDA

For the first time in decades, chip design feels like it’s on the verge of a genuine reset. AI isn’t just a new knob on a timing engine or another heuristic in the regression farm; it’s a chance to rethink how we understand, verify, and evolve insanely complex hardware–software systems.

The question is no longer whether AI will touch chip development, but how deep it will go—and whether we’ll use it merely to polish old workflows or to expand what’s possible to design and prove correct at all.

But are we currently progressing into a direction that is worthy of problem solving? It’s not difficult to imagine how such a future would look like: specialized LLMs, APIs to connect EDA tools, serious research, and exchange of representative user data to optimize flows.

But is the industry currently set up this way?

The big 3 vendor perspective(s)

The EDA industry is loudly declaring that AI has arrived. Cadence, Siemens EDA, and Synopsys (the big three) all showcase “AI-driven” platforms, “agentic” workflows, and “generative” capabilities in their keynotes. Agentic startups promise AI copilots for chip design.

Samsung, Nvidia, and other mega-customers are quietly building their own internal AI stacks. And in the background, universities and foundation model labs like OpenAI and DeepMind are doing their own thing, mostly disconnected from this industrial theater.

Look past the branding and see something much less coherent: four camps, each optimizing for its own incentives, and none addressing the hardest verification and design problems in a serious, integrated way.

The first camp is the big three. One has a narrative that is aggressively polished: AI as a unifying fabric across architecture, implementation, verification, and signoff. On paper, it’s exactly the right idea. In practice, most of what’s publicly visible is a scattering of ML and LLM features bolted onto existing products, wrapped in a platform story that is much stronger in marketing than in reproducible methodology.

There are claims about AI-guided coverage closure and scenario generation, but far fewer detailed case studies that a skeptical verification lead could take apart and rely on. Technically, this company narrative shows it’s doing useful work; strategically, it’s primarily about defending revenue and establishing itself as the “AI platform” customers must buy into.

A second narrative takes a different tone: more pragmatic, less breathless. Their AI pitch is 10–30% improvements in regression time, PPA closure, and debug efficiency. They emphasize that ML is built into the solvers and optimizers rather than exposed as a gimmicky chatbot layer.

For organizations taping out serious silicon, this is credible and attractive: keep existing flows and get incremental wins. But that’s also the problem. It’s AI as advanced heuristics, not AI as a rethinking of verification for trillion-cycle, software-heavy, multi-die systems. The message is “do the same thing, just a bit faster,” which is business-rational and intellectually timid.

And the third narrative, for its part, grounds its AI story in hardware-assisted verification and DFT. They are at least honest about where the real pain is: emulation farms straining under 40‑billion‑gate chiplet designs; massive software stacks; and DFT and power analysis workflows that choke traditional environments. Their use of AI is mostly about better resource utilization, faster compiles, accelerated DFT workloads on emulators, and automated generation of reports and transactors.

This is important, and some of it is genuinely innovative on the infrastructure side. However, it mostly skirts the core question of correctness. There is very little about AI for deep semantic understanding of designs, for test synthesis, for inferring invariants, or for blending learning with formal reasoning at scale. This narrative is focusing on shoveling the verification mountain more efficiently, not on changing the shape of the mountain.

Across all three incumbents, the pattern is consistent. They are not leading on foundational AI for verification. They are inserting ML/LLM features into their products in ways that strengthen their moats and justify platform lock-in. Their AI is largely proprietary, closed, and bound to a single vendor ecosystem. It’s technically competent and strategically defensive.

AI startups—new “Tabula Rasa” approaches

The second camp—agentic AI vendors like ChipAgents, Moore’s Lab, and Bronco AI—looks more disruptive at a glance. They don’t try to build the solvers; instead, they target the workflow of the engineer. These systems ingest RTL, testbenches, logs, coverage reports, specifications, bug trackers, and wikis.

They use large language models plus tool APIs to answer questions like “Why did this regression fail?” or “What should I do next?” They can orchestrate multi-step flows: launch regressions, analyze results, file tickets, update documentation, and propose follow-up tests.

This is a genuine improvement over the current state of affairs where engineers burn countless hours on log archaeology and context switching between silos of information. But being critical, agentic AI today is far better at smoothing human pain points than at addressing the core technical difficulty of verification. These systems sit on top of the incumbents’ tools and rely on whatever APIs those tools expose.

If those APIs are thin, unstable, or intentionally limiting, the “agent” degrades into a clever log parser. And because current LLMs are still brittle on precise semantics, concurrency, and strict correctness, most agentic systems are pattern matchers and orchestrators, not genuine reasoning engines about hardware behaviour. They can triage, guide, and accelerate, but they rarely change what you can prove about a design.

The giant users

The third camp consists of the giant end users like Samsung and Nvidia, who look at all of this and decide to build their own AI ecosystems. They have reasons the vendors can only envy: vast proprietary design portfolios, massive software workloads, custom verification flows, and decades of institutional memory about failures and workarounds. They do something closer to what should have existed from the beginning.

They build internal copilots and agents that understand their architectures, coding styles, constraints, safety regimes, and business priorities. They integrate across the big three vendors’ tools, and a forest of in-house tools. They treat the vendors’ products as engines behind the scenes and construct a domain-specific AI layer on top.

From their point of view, this is the only rational approach. For the ecosystem, it has a downside. Each large customer ends up recreating similar internal stacks in private: similar integrations, similar prompt engineering, similar hacks to get around tool limitations. None of this is published or generalized. The most advanced “AI for chips” work is happening inside the firewalls of a few giants, and the lessons do not propagate.

It is effective and myopic at the same time.

The academic perspective

Meanwhile, the fourth camp being university research occupies an awkward and increasingly marginal position. Historically, academia has been where the big conceptual leaps in verification and synthesis occurred: SAT/SMT-based reasoning, CEGAR, IC3/PDR, and many other ideas that quietly underpin modern tools.

Today, universities explore promising combinations of learning and formal reasoning, program synthesis, and new abstractions for system behavior. But they generally lack access to full-scale industrial designs, closed commercial tools, and realistic data. Tool vendors are hesitant to open their ecosystems; customers are understandably cautious about sharing real designs. Funding pressures drive many projects toward small, benchmark-driven demonstrations rather than risky, large-scale collaborations.

The result is that some of the most interesting ideas—how to fuse symbolic reasoning with learned models, how to automatically infer specifications, and how to reason about software and hardware jointly—are explored on toy problems with no clear path into mainstream flows.

The industry, for its part, is busy shipping incremental ML wrappers, and hardly anyone is building serious bridges between the two worlds. It’s not that universities lack relevance; it is that the industry has structured itself such that the most radical research is almost guaranteed to remain peripheral.

The model foundations

Overlaying all of this are the foundation model labs: OpenAI, Anthropic, Google DeepMind, Meta, and others. These organizations are building the most capable general reasoning systems currently available, and they are rapidly evolving techniques for program synthesis, tool use, and formal-ish reasoning in natural language environments. Yet, in the EDA world, they are mostly treated as commodity model providers: grab GPT or Claude, fine-tune a narrow layer, wire up a chat interface to data logs, and call it an AI feature.

What is largely missing is serious, domain-driven co-design: injecting the structure of hardware, formal semantics, type systems, property languages, and symbolic engines into the models themselves, and conversely exposing the models’ strengths back into the verification stack.

Foundation models will never be optimal for RTL and concurrency out of the box, but the EDA incumbents have done very little to create the conditions under which such specialization could happen in a principled way. If and when one of the big model labs decides that “programs that compile to silicon” is a strategic domain, the current generation of vendor platforms will likely look quaint.

Outlook: Is the industry solving the right problem(s) and what’s the problem worth solving?

Taken together, these four camps are all underperforming relative to what is technically possible. The big three are shipping incremental heuristics and calling them platforms. Agentic vendors are improving workflows but are constrained to shallow semantics.

Samsung, Nvidia, and their peers are building powerful but private stacks that do not lift the state of the art for anyone else. Universities are generating genuinely new ideas without real channels for impact. Foundation model labs are shaping the AI substrate, but the interface with hardware design is thin and unimaginative.

The future that would move the needle is not mysterious. It would involve foundation models explicitly specialized and constrained by rich formal and domain structures; EDA tools exposing deep, stable APIs so that both research systems and agentic orchestrators can drive real flows; serious industrial–academic collaborations around real designs, software workloads, and verification obligations; and end users like Samsung and Nvidia contributing abstractions, interfaces, and benchmark problems instead of quietly hoarding bespoke solutions.

Instead, the industry is drifting toward a patchwork of proprietary “AI experiences” bound to each vendor, plus a small number of sophisticated but opaque internal efforts at a handful of giants. The risk is that we declare victory far too early—that “AI in EDA” hardens into a set of shallow, walled-garden add-ons while the central challenge of scalable correctness for software-heavy, multi-die systems remains largely unsolved.

The real question is not who can generate the flashiest AI marketing or the neatest chatbot demo inside an integrated design environment (IDE). It’s who is willing to open enough of their stack, share enough structure and data, and collaborate deeply enough that AI can change what we are capable of verifying at all, not just shave a few percent off the run time of regressions we already know how to run. Right now, no one in this ecosystem can honestly claim that mantle.

“A new hope”

Despite the current mess of walled gardens, shallow copilots, and private AI stacks, the ingredients for something far better are finally on the table. We have foundation models that can reason over code, decades of formal methods waiting to be supercharged rather than sidelined, and a new generation of engineers who are comfortable treating tools as collaborators, not black boxes.

If vendors open real APIs, if giants like Samsung and Nvidia share abstractions instead of just artifacts, and if universities and model labs are invited into serious, data-rich collaborations, AI can do more than accelerate today’s flows—it can change what we dare to design.

The hopeful view is simple: the next great leap in chips won’t come from any one camp winning the landgrab, but from all of them finally deciding that solving the hard problems together is more valuable than owning the buzzword alone.

Will we get there? Only time will tell.

Simon Davidmann is an EDA industry pioneer and serial technology entrepreneur with over 40 years of experience in simulation and verification. His career has been instrumental in shaping the foundational languages and methodologies used in modern chip design, particularly those now critical for AI/ML hardware. Davidmann was the co-creator of Superlog that became SystemVerilog. After selling Imperas to Synopsys in 2023 and being Synopsys VP for Processor Modeling & Simulation, he left Synopsys and is now an AI + EDA researcher at Southampton University, UK.

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