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I low key don't know shit about electronics. I found a old Samsung camera of my parents but the charger was missing. I had this charging module over because I wanted to power an esp32 with a battery (never did something with it). And I looked at the battery and it said 3,8v (4,2v) on the outside and this module was for 3,7v batteries which also charge up to 4,2v, so I thought close enough. I needed a metal that was easy to bend and wouldn't scratch the shit out of the contacts and that I could push a little so it would make contact. Solder was my first thought so all the wiring is solder. It's quite annoying to solder solder but in the end it worked and charged the battery and the camera works. submitted by /u/Tee-Der-Schwarz-Ist [link] [comments]

Found this place after my regular closed. submitted by /u/BlownUpCapacitor [link] [comments]

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I came across a problem today where I'm ordering lots of parts to prototype my product I'm building. I got a lot of the basic dimensions of some of the PCBs, but I needed to know spacing of components as well! I made this website that lets you paste any image of a part. You just draw the outline of the PCB with your mouse (it snaps to the axes to make it easy). Then you can find out the relative distances of the components on the PCB by drawing your own lines. The program automatically finds the distance relative to the boundary of the PCB using a pixels ratio. Check it out here. Absolutely free of charge, no ads or anything like that, just thought it might be a neat tool for the community! submitted by /u/Legitimate-Pea3605 [link] [comments]

It has some pixel errors for some reason, but it works otherwise. It has 2 lines with 40 characters each. Each character has a 5x12 dot matrix. I really like VFDs. submitted by /u/PPEytDaCookie [link] [comments]

I love old Tektronix test gear, it's all beautifully designed and made. submitted by /u/TheMightyMadman [link] [comments]

I wanted to learn more about CPU architecture, so designed a small one. Importantly, this design has an integrated boot-loader (so that we can load programs to be run) and integrated IO (We can use UART to load programs onto the board, and observe the program trace) The whole project is open-source, and can be seen here: https://github.com/matchahack/tcpu. It includes a simulation and FPGA emulation guide. It is a small architecture, since buying space on the tiny-tapeout shuttle is expensive, but it is on the sky26a! See here: https://app.tinytapeout.com/projects/4119 submitted by /u/AlienFlip [link] [comments]

Step-down buck converters used in 48V-to-5V power supply designs are becoming increasingly common in automotive and industrial applications, especially in advanced driver assistance systems, in-vehicle infotainment, and robotics. While synchronous buck topologies achieve high efficiency, they sometimes fall short of expected performance. In some cases, switching behavior, controller bias, power, and thermal performance can create limiting losses, resulting in a decrease in efficiency.

Figure 1 shows the efficiency of Texas Instruments’ 48 VIN, 960 W four-phase buck converter with integrated GaN reference design (PMP23595), with the output voltage set to 5 V using forced pulse-width modulation operation without cooling.

Figure 1 Efficiency of 48 VIN to 5 VOUT at a 400 kHz switching frequency. Source: Texas Instruments

The efficiency curve in Figure 1 can meet the specifications of most 48V-to-5V power supply designs, but could fall just below the intended target for others. Rather than changing topology or adding complexity, it’s possible to make some practical adjustments within a standard buck converter to boost efficiency further.

Figure 2 shows the efficiency curve for of the 48V-5V buck converter under several test configurations, including added thermal management, switching frequency adjustment and external bias operation. These configurations were selected to isolate the effects of each adjustment and indicate that different loss mechanisms dominate depending on the operating point. Let’s look at each adjustment in greater detail.

Figure 2 Efficiency of 48VIN to 5VOUT with multiple adjustments. Source: Texas Instruments

Adjustment No. 1: Thermal performance

Adding a cooling system, in this case a heat sink, produced a negligible improvement at a low output current but resulted in a clear improvement above 30 A.

At a low output current, the total power dissipation remains relatively small, and device temperatures remain closer to ambient. Thus, reducing thermal resistance provides little effect.

At higher output current, conduction losses increase with IOUT2, causing the field-effect transistor (FET) junction temperature and inductor temperature to rise. As temperature increases, the FET drain-to-source on-resistance (RDS(on)) and inductor copper resistance increase, further increasing conduction losses. Incorporating a heat sink or some form of cooling reduces this rise in junction temperature, directly lowering temperature-dependent resistances. Another result is a measurable reduction in conduction losses, which appear as improved efficiency at high currents. At a high current – 80 A in this scenario – the improvement reached 0.8%.

Adjustment No. 2: Switching frequency

Reducing the switching frequency from 400 kHz to 250 kHz while ensuring that the inductance value was still suitable improved efficiency approximately 0.5% through the mid-current range and 1% in the high-current range. However, decreasing the switching frequency too much with the same inductor value can result in higher core losses if you don’t manage the ripple current correctly.

Reduced switching-related losses cause this behavior, such as field-effect transistor turn-on and turn-off losses, gate-drive losses, and internal controller switching losses. At a 48-V input, these losses scale quickly with both current and switching frequency.

At light loads, reducing the switching frequency produces smaller efficiency improvements, suggesting that fixed losses such as quiescent current or inductor core loss dominate in this region and limit the overall impact of this adjustment.

Adjustment No. 3: Controller bias power

In a forced pulse-width modulation configuration, supplying the controller bias from an external 5-V source improves efficiency by approximately 0.5% in the light- to mid-current range.

Deriving bias from VOUT remains a viable option if the output voltage is not a much higher voltage (such as 24 V and above) or much lower (such as 3V and below).

When deriving bias power internally from the output rail, a small portion of the converter’s output power operates the controller. At light loads, this overhead represents a slightly larger fraction of the total output power.

At higher output currents, the conduction losses in the FETs and inductor begin to dominate. In this region, the controller bias power becomes such a small fraction of total losses that it no longer produces a measurable efficiency benefit. As a result, the externally biased efficiency curve converges with the internally biased efficiency curve.

Adjustment No. 4: Inductor optimization

The inductor can play a larger role in efficiency than its direct current resistance (DCR) alone suggests. While copper losses depend on DCR and scale with the output current, core losses depend strongly on ripple current and switching frequency.

If the ripple current is high, core losses can become significant. This is especially common with powdered iron core material, which can have high core losses if you don’t account for the ripple current.

Increasing the inductance reduces ripple current and core losses but may increase DCR. Conversely, using a very low DCR inductor while having excessive ripple current can increase core losses to the point where it offsets the efficiency boost. The inductor choice balances DCR and ripple current such that neither copper nor core losses dominate.

When looking to improve converter efficiency, identify which loss mechanism dominates the operating region of interest as a useful first step. For what we have seen here on this synchronous buck converter, you can evaluate it quickly:

• If light-load efficiency is low, examine the switching frequency and internal bias losses.
• If efficiency is low at high current, focus on conduction losses and thermal management.
• If the losses appear higher than expected across the full current range, review the inductor ripple current and core material.

Once you identify the dominant loss mechanism, minor design adjustments can often lead to measurable efficiency gains.

The high-efficiency system in this exercise used the TI reference design that I mentioned earlier, which includes the LMG708B0 synchronous step-down converter with integrated GaN configured to a 5-V output with a reduced inductance of 2.5µH.

References

1. Jacob, Mathew. “Select inductors for buck converters to get optimum efficiency and reliability.” Texas Instruments Analog Design Journal article, literature No. SLYT775, 3Q2019.

Matthew Bowers is a systems engineer in TI’s Power Design Services team, focused on developing power solutions for automotive applications. Matthew received his bachelor’s degree in electrical engineering from Texas Tech University in 2023.

 

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The post Power Tips #151: Improving efficiency in 48V-input multiphase buck converters with GaN appeared first on EDN.

Arm is now a chip vendor—what does it mean for the semiconductor industry? EE Times’ Nitin Dahad was at the event in San Francisco, California, where the British IP giant unveiled its first chip, an AGI CPU for data centers. He reports on what it means for the company, now increasingly dubbed Arm 2.0, and how this launch will impact its standing in the semiconductor industry. He also explains the delicate balancing act that Arm will have to play moving forward.

Read the full article at EDN’s sister publication, EE Times.

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The post What does Arm’s own chip stand for? appeared first on EDN.

У КПІ відбулася відкрита лекція Посла Республіки Корея Пака Кічанга kpi пт, 03/27/2026 - 12:41

КПІ ім. Ігоря Сікорського відвідала делегація Королівства Данія kpi пт, 03/27/2026 - 12:38

📰 Газета "Київський політехнік" № 11-12 за 2026 (.pdf) Інформація КП пт, 03/27/2026 - 12:10

Wolfspeed Inc of Durham, NC, USA — which makes silicon carbide (SiC) materials and power semiconductor devices — has completed its private placements (announced on 19 March) of...

Over the last few years, there has been growing interest across the global semiconductor packaging industry with a new approach. Co-packaged optics (CPO) involves integrating optical fibers, used for data transmission, directly onto the same package or photonic IC die as semiconductor chips. Traditionally, semiconductor packaging has used copper interconnects, but these can consume large amounts of power and lead to signal weakening at high frequencies when the distance is further than a couple of meters.

With CPO, the optical components are integrated directly into a package, and the long copper trace between the switch and the optical module is replaced with short, high-integrity connections. Optical signaling uses far less power at high data rates than electrical signaling. As CPO reduces the distance between optical components and the semiconductor dice, this lowers latency, improves high-speed signal integrity, and accelerates data transfer.

All of which are fundamental for the next generation of AI devices for high performance computing (HPC) inside the data center systems. Nevertheless, there are obstacles that need to be overcome with CPO and when designing photonic packages, especially for integrated photonic circuits or photonic chips. This is why advances in photonic package design are coming to the forefront.

 

Overcoming CPO obstacles

When co-packaging photonics with electronics, there can be signal integrity issues. Electrical crosstalk must be reduced to improve signal quality. Using short interconnects and low-parasitic layouts are the most appropriate tactics when used alongside co-design tools for optical optimization. Signal integrity can be ensured without requiring complex routing or more space, as optical interconnects can support multi-terabit-per-second data rates over long distances with only minor signal loss.

Mounting a large photonic IC die onto a laminate or organic substrate can be problematic. Due to the coefficient of thermal expansion (CTE) mismatch between the substrate and the photonic IC die, non-negligible die warpage may occur. This warpage can significantly degrade optical signal performance in the photonic IC waveguides during data transmission, leading to substantial reductions in optical signal power and quality.

In addition, excessive warpage may introduce mechanical stress in the photonic IC die, altering its material properties and further impacting optical performance. While using a ceramic substrate could mitigate these issues, it’s more costly and is not widely adopted today.

Dealing with temperature variations can be a concern with photonic devices, but efficient thermal management and thorough thermal design can help to improve performance and reliability. Integrating photonics with electronics may require thermoelectric coolers (TECs) and heat sinks along with smart thermal simulations throughout the design process.

Sub-micron alignment is also a complex technical task. Optical misalignment can lead to significant insertion losses, as well as disrupting device performance. Leveraging passive alignment techniques with etched features or alignment markers may mean lower levels of accuracy, but this is the lowest cost. Active alignment, using real-time optical feedback, results in better performance and efficiency, though it’s far more complex and costly.

Addressing challenges when testing optical components involves using built-in test waveguides, automated optical probing systems, and standardized test procedures during and after packaging. Integrating optical and electrical components into a single package not only makes the manufacturing process more complicated, the associated risks and costs are also greater due to the different assembly phases. It’s possible to cut through the complexity and improve yields by using standardized processes for CPO assembly.

The future of CPO and photonic package design

As a result of the growing interest in CPO and photonic packaging, there have been advances in photonic package design. CPO enables faster data transmission and improved power-efficiency when compared to the conventional copper-based interconnects approach. It has many advantages, including high-speed communication and lower power consumption, but there are also concerns related to signal integrity, thermal management, optical alignment, and costs.

Advances in photonic package design can overcome these obstacles and help electronic design engineers create new architectures that would not be viable with traditional semiconductor packaging. As the semiconductor industry continues to rapidly evolve, with more complex devices requiring high-performance, compact and power-efficient chips, CPO with advanced photonic package design will become increasingly important.

Dr Larry Zu is CEO of Sarcina Technology.

Special Section: Chiplets Design

• What the special section on chiplets design has to offer
• Chiplet innovation isn’t waiting for perfect standards
• Scoping out the chiplet-based design flow
• Demystifying 3D ICs: A practical framework for heterogeneous integration
• Chiplets: 8 best practices for engineering multi-die designs

The post Overcoming interconnect obstacles with co-packaged optics (CPO) appeared first on EDN.

Leading semiconductor manufacturer, Nuvoton, has partnered with pioneering cybersecurity business, Trustonic, to strengthen the capability of its advanced NuMicro® MA35 series MPU.

Established in 2008, Nuvoton was founded to bring innovative semiconductors to market and has since evolved into a leading name in the provision of microcontroller application integrated circuits (ICs), audio application ICs and cloud & computing ICs.

To strengthen the security of the solution, the Trusted Secure Island (TSI) of Nuvoton’s NuMicro MA35 series integrates Trustonic’s Trusted Execution Environment (TEE), Kinibi.

Having obtained the World’s first comprehensive EAL5+ certification in 2022, ‘Kinibi’ is now deployed to nearly 3 billion smart devices and 20 million vehicles globally, with zero safety violations. Its integration in the NuMicro MA35 series creates a secure environment that drives Protection, Detection, and Recovery for IoT products, including EV chargers.

Walter Tseng, Vice President of the Microcontroller Business Group at Nuvoton, explained: “Our partnership with Trustonic represents a significant milestone in Nuvoton’s commitment to providing industry-leading security for the industrial IoT market. By integrating the EAL5+ certified Kinibi TEE into our NuMicro MA35 series, we are providing our customers with a robust, hardware-backed security foundation. This collaboration ensures that critical industrial applications—from edge gateways to smart factory automation—are protected against evolving cyber threats through a dedicated ‘Protection, Detection, and Recovery’ framework, all while maintaining the high performance our users expect.”

Andrew Till, General Manager of Secure Platform for Trustonic, added: “Nuvoton’s MA35 platform is designed for high-performance edge applications, and security is critical to its success. Integrating Kinibi provides a proven Trusted Execution Environment that protects sensitive operations and enables manufacturers to build secure, scalable industrial IoT solutions with confidence.”

The post Nuvoton and Trustonic Collaborate to Strengthen Security of NuMicro MA35 Series MPU appeared first on ELE Times.

This two images i took a long time ago are from a smd led, its curious to se the two little wires connecting the led!. submitted by /u/aguilavoladora36 [link] [comments]

КПІшниці — у плей-офф Клубно-зальної волейбольної ліги kpi чт, 03/26/2026 - 20:19

Lumentum Holdings Inc of San Jose, CA, USA (which designs and makes photonics products for optical networks and lasers for industrial and consumer markets) plans to establish a new US manufacturing facility in Greensboro, North Carolina. The 240,000ft2 facility will produce indium phosphide (InP)-based optical devices that serve as critical components in the world’s largest AI data centers...

💡 Оголошено набір на інтенсивні курси з англійської мови до ЄВІ kpi чт, 03/26/2026 - 15:01