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MacDermid Alpha Electronics displays its latest attachment materials, which help power electronics manufacturers to improve reliability, process variation, and scale production more effectively. As automotive, industrial, and AI-driven data center applications demand higher power density and faster-switching devices, manufacturers are facing tighter thermal limits and increasing pressure to maintain stable, repeatable production. Bond line control, void reduction, and manufacturing consistency are becoming more critical to long-term power module performance.

MacDermid Alpha highlights its expansion of the ALPHA Argomax sintering portfolio and the ALPHA TrueHeight solder preforms, designed to help customers improve thermal and electrical performance while supporting more stable, high-volume manufacturing.

MacDermid Alpha will also contribute to the PCIM Europe technical program, sharing insights on electronics assembly solutions for emerging applications. On the AI stage, John Hynek, Global Product Manager, will examine how attach materials can support the uptime and reliability demands of AI and data center infrastructure. In addition, Andreas Socarras, Senior Application Engineer, will present a poster session titled “Investigation of Large Area Soldering Using High Stress Assembly and Challenging Surface Coatings”.

“Power electronics manufacturers need to attach solutions that can deliver tighter process control and higher reliability without adding unnecessary complexity,” said Gustavo Greca, Line of Business Director for Power Electronics at MacDermid Alpha Electronics Solutions.

MacDermid Alpha Electronics Solutions

MacDermid Alpha Electronics Solutions, a business unit of Element Solutions Inc, is a global leader in high-performance specialty chemicals, materials, and process technologies for every stage of the electronics manufacturing process. With expertise spanning circuitry formation, wafer-level packaging, circuit board assembly, semiconductor assembly, and film and smart surfaces, MacDermid Alpha delivers advanced, sustainable, and integrated solutions that drive innovation and reliability across the electronics supply chain. Operating worldwide and backed by more than a century of innovation, the organization supports a broad range of industries, including automotive, consumer electronics, data infrastructure, high-performance computing, and telecommunications, enabling next-generation electronics.

The post MacDermid Alpha Tackles Power Module Reliability appeared first on ELE Times.

Power Integrations Inc of San Jose, CA, USA (which provides high-voltage integrated circuits for energy-efficient power conversion) has introduced two new ultra-slim, compact auxiliary power supply reference designs for 800VDC AI data centers. The single-output, 15W design is only 30mm by 30mm with a 7mm profile, while the isolated, six-rail, 35W design is only 80mm by 60mm with an 8mm profile...

Design-time closure is no longer the end of system convergence.

In modern AI silicon—encompassing chiplet-based platforms, high-bandwidth memory systems, and advanced heterogeneous packages—the realized system continues to change after release. Workloads shift. Voltage and thermal conditions move dynamically. Network-on-chip (NoC) traffic patterns vary. Memory pressure changes. SerDes links retrain. Aging accumulates. Package and board environments influence behavior over time.

A system may pass design signoff, validation, and qualification, yet still encounter runtime states that were not fully represented during design-time closure. This does not mean the original design was wrong. It means the operating system has entered a lifecycle regime where hardware state, firmware response, and evidence maturity must remain synchronized.

This is where the firmware–hardware handshake becomes important. Hardware senses the condition; firmware executes bounded actions; and governed evidence determines whether the action is valid.

The handshake is not an uncontrolled autonomous loop. It’s a disciplined runtime structure that connects hardware telemetry, firmware policy, causality interpretation, bounded action envelopes, rollback limits, and lifecycle evidence.

In this viewpoint, firmware is not the intelligence. Firmware is the bounded execution layer. The intelligence is in the governed interpretation of evidence: whether a signal is mature enough, synchronized enough, causally grounded enough, and safe enough to support action.

From observability to action

In complex AI silicon, observability is expanding rapidly. NoC counters, voltage monitors, thermal sensors, ECC logs, accelerator stall indicators, memory-controller events, SerDes retraining records, clock-domain telemetry, firmware traces, and package-level sensors can all provide valuable runtime information.

Here is how the firmware–hardware handshake layer works in governed runtime convergence. Source: Author

Hardware telemetry is captured, normalized into evidence, checked for admissibility, evaluated for causality, and passed through bounded firmware policy before any runtime action is executed and recorded as lifecycle evidence. But telemetry alone does not create authority.

An NoC latency spike may correlate with workload congestion, but it may also reflect a localized thermal hotspot, voltage droop, memory backpressure, firmware scheduling behavior, or package-level power delivery instability. A SerDes retraining event may indicate channel degradation, but it may also be triggered by temperature drift, reference-clock behavior, board-level noise, connector variation, or power integrity disturbance.

The runtime system therefore faces a difficult question: When should firmware act?

If firmware acts too slowly, the system may lose performance, reliability, or availability. If firmware acts too aggressively, it may create instability, hide root cause, or trigger unnecessary throttling, rollback, or degraded operation. If firmware acts on weak evidence, it may correct the wrong problem.

This is why runtime telemetry must mature into governed evidence before it’s used to drive consequential action.

Hardware as sensing layer

Hardware provides the first layer of runtime awareness.

Examples include NoC latency, congestion, retry, and utilization counters; voltage droop sensors and current monitors; thermal sensors and hotspot indicators; memory-controller stalls and ECC events; SerDes equalization, retraining, and link-margin information; accelerator utilization and stall counters; clock, reset, and power-state telemetry; and package, board, and system-level sensor data.

These signals provide visibility into how the system behaves under real workload and environmental conditions.

However, hardware signals are not self-explanatory. They must be interpreted in context. A voltage droop event means something different during peak AI workload than during idle transition. A thermal hotspot means something different if it is stable, spreading, oscillating, or correlated with a specific workload pattern. An NoC stall means something different if it aligns with memory saturation, power throttling, package temperature, or firmware scheduling.

The key point is simple: Hardware can sense state, but it does not automatically explain state. And that explanatory layer requires causality, evidence maturity, synchronization, and decision context.

Firmware as bounded execution layer

Firmware is the natural runtime bridge between hardware state and system response. Depending on the platform, firmware may be able to adjust voltage and frequency states, throttle selected regions, retrain high-speed links, reduce lane rate or link width, isolate a tile or accelerator block, migrate workload away from a stressed region, change scheduling policy, request diagnostic capture, enter deterministic degraded mode, or trigger service and validation escalation.

These actions are powerful because they allow the system to respond before a condition becomes a failure. But that power also creates risk.

Firmware should not become an unconstrained autonomous agent. A firmware action can affect performance, lifetime, reliability, customer experience, safety margin, and debug visibility. If firmware changes the operating state without traceable evidence, the system may appear to recover while the underlying cause remains unresolved.

One of the risks of adaptive firmware is that it can unintentionally hide the physical root cause. A system may appear stable because a link retrained, a frequency state changed, a workload migrated, or a region was throttled. But if the intervention is not tied to a normalized evidence record, the original cause may disappear from view. In advanced systems, repeated compensation can become a failure mode of its own.

The purpose of the firmware–hardware handshake is therefore not only to act, but to preserve the evidence trail behind the action. In other words, the correct role of firmware is not unlimited control. The correct role is bounded execution.

Firmware should execute only within approved policy limits, with clear evidence requirements, confidence thresholds, rollback rules, and auditability.

The handshake model

The firmware–hardware handshake can be described as a governed runtime sequence:

Hardware state → contextual capture → normalized evidence → admissibility check → causality assessment → firmware policy → bounded action → updated evidence → lifecycle record

Each step prevents runtime telemetry from becoming uncontrolled action.

First, the hardware signal must be captured with context: timestamp, workload class, physical location, power state, thermal state, firmware version, configuration state, and system region. Second, the signal must be normalized into an evidence object. A raw sensor reading or counter value is not enough. It must be linked to the specific system condition it describes.

Third, the evidence must be checked for admissibility. Is the timestamp valid? Is the firmware version known? Is the sensor calibrated? Is the workload context synchronized? Is the signal consistent with voltage, thermal, memory, package, and board evidence? Is the proposed cause physically plausible?

Fourth, firmware action must remain inside a bounded envelope. The system may allow a defined frequency reduction, limited link retraining, controlled workload migration, or temporary degraded mode. But if evidence confidence is low or the action exceeds policy authority, escalation is required.

Finally, the outcome must be recorded. Did the action stabilize the system? Did the same condition recur? Did the event indicate a one-time workload excursion, a design margin issue, a package-related sensitivity, or an aging trend?

This is how runtime action becomes lifecycle evidence.

Bounded action envelopes

The bounded action envelope is the core safety mechanism. It defines what firmware may do, under what evidence conditions, and with what limits. For example, a firmware policy may allow temporary throttling if thermal evidence is mature, localized, and correlated with workload.

It may allow link retraining if signal-margin evidence crosses a defined threshold. It may allow workload migration if a tile shows repeated voltage-droop sensitivity under known conditions. It may allow deterministic degraded mode if full performance cannot be preserved without violating reliability boundaries.

But the same policy may block action when evidence is incomplete. If an NoC latency spike occurs without synchronized voltage, thermal, workload, and memory context, firmware should not automatically classify the NoC as the root cause.

If a link repeatedly retrains after thermal cycling, firmware should not hide the event indefinitely by retraining silently. If a voltage-droop event becomes recurrent under a specific package lot, board lot, workload class, or thermal condition, the system should escalate the event instead of silently compensating through repeated firmware action.

Bounded action does not mean passive behavior; it means disciplined behavior. The system can respond, but it must respond within governed limits.

Extending convergence into runtime

The handshake extends governed convergence beyond design-time. At design-time, engineers close the system against modeled requirements, simulated margins, validation data, and qualification evidence. At runtime, the system encounters real workload, real aging, real environment, and real variation.

The firmware–hardware handshake allows convergence to continue operationally. Several runtime concepts become useful here.

• A boot-time realization baseline can capture the initial measured system state at startup. This provides a reference for later drift.
• A corridor stability index can summarize the health of a specific governed path, such as an NoC region, power domain, HBM interface, SerDes path, or package-to-board corridor.
• A global convergence epoch can ensure that telemetry from multiple runtime sources is compared within a valid synchronization window.
• Realization fatigue tracking can monitor accumulated stress, repeated throttling, retraining frequency, thermal exposure, voltage events, or degradation patterns.
• A deterministic degraded mode can preserve safe operation when full performance is no longer evidence-supported.

These concepts are not meant to add vocabulary for its own sake. They define how runtime signals can be organized into a governed system state rather than scattered logs.

Why this matters for AI silicon

AI workloads are especially relevant because they stress systems dynamically and unevenly.

A training or inference workload may create localized NoC congestion, memory pressure, power spikes, or thermal concentration. The system may remain within global specifications while a local region experiences repeated stress. A package or board condition may interact with workload behavior in ways that were not fully visible during nominal validation.

In such systems, the firmware–hardware handshake becomes a reliability and performance tool. It allows the platform to distinguish between transient workload variation, recurring physical sensitivity, firmware scheduling artifacts, marginal power delivery behavior, thermal containment issues, aging-related degradation, validation escapes, and package or board interaction.

The goal is not to blame the NoC, firmware, package, power delivery network (PDN), memory, board, or workload too early. The goal is to preserve causality until the evidence is mature enough to support a decision.

Relationship to fleet learning

Runtime evidence becomes even more valuable when it’s aggregated across systems, products, lots, platforms, and field conditions. This is where fleet learning enters the picture.

Fleet learning becomes valuable when repeated runtime patterns appear across systems, lots, boards, packages, workloads, or field environments. A recurring SerDes retraining signature after thermal exposure may indicate a package, board, connector, or policy sensitivity.

A workload-specific droop pattern across a defined power domain may inform future PDN design or validation coverage. A degradation signature that appears after a thermal-cycle threshold may reshape future qualification assumptions.

But these patterns should not automatically rewrite firmware policy. Field data should not autonomously change system behavior, alter operating limits, or modify release criteria. Fleet learning recommends and bounded gate authority approves. This preserves the difference between learning and governing.

Physical state and bounded action handshake

The firmware–hardware handshake is becoming a necessary part of advanced system realization.

As AI silicon, chiplets, HBM platforms, high-speed interconnects, and advanced packages become more dynamic, design-time closure alone cannot cover every runtime state. Hardware must sense. Firmware must respond. But the response must remain bounded by evidence maturity, causality, synchronization, rollback limits, and lifecycle governance.

So, the future system will not be defined only by better telemetry or more autonomous firmware; it will also be defined by a disciplined handshake between physical state and bounded action.

In SEGA-AI terms:

• Observability provides signals
• Admissibility qualifies evidence
• Bounded firmware action preserves convergence
• Fleet learning refines the next lifecycle decision

The system does not remain trustworthy because it can sense everything. It remains trustworthy when it knows which signals are mature enough to act on.

Dr. Moh Kolbehdari is senior director of IC/packaging at Socionext US.

Editor’s Note

This is Part 2 of the article series about silicon governance framework for AI silicon. Part 1 described why data movement alone cannot explain system behavior in modern AI chip designs.

Related Content

• UVM Reactive agents verify with a handshake
• Development tool evolution – hardware/firmware
• Hardware Root of Trust Essential for AI Chip Integrity
• What you need to know about firmware security in chips
• Hardware Verification: What AI Gets Right When It Generates Your Testbench

The post The firmware-hardware handshake in a silicon governance system appeared first on EDN.

Wolfspeed Inc of Durham, NC, USA — which makes silicon carbide (SiC) materials and power semiconductor devices — is expanding into the rapidly growing data-center market with the creation of a dedicated data-center solutions team and regional office in the San Francisco Bay Area. The new data-center solutions team is targeted at enabling closer alignment with leading hyperscalers, ODMs and the entire ecosystem to build differentiated products and solutions for AI and other data-center applications...

A new hardware-in-the-loop (HIL) testing framework claims to make automated, hardware-validated testing accessible to every team by offering engineering resources previously available only at large enterprises. This new testing framework—called BootLoop Test—unifies bench, continuous integration (CI), and end-of-line validation on a single platform.

Though HIL testing is one of the most valuable practices in the hardware world, it’s mostly adopted without any rigorous testing infrastructure. That’s because building a hardened HIL framework requires dedicated test engineers, months of custom development, and specialized skills that most firmware teams don’t have.

Consequently, many companies either forgo testing entirely or rely on ad hoc scripts and manual validation processes. That, in turn, slows development cycles, misses errors, and causes fragile release processes.

BootLoop, a startup that provides an AI platform for firmware and embedded development, addresses this problem by offering a complete HIL platform that spans the entire embedded product lifecycle. As a result, a hardware company can go from zero testing infrastructure to a fully automated pipeline in days.

“Most hardware companies know they need more rigorous firmware testing,” said Noah Pacik-Nelson, CEO of BootLoop. “They just don’t have the time or the tools. We built BootLoop Test, so they don’t have to choose between shipping quickly and shipping robust code.”

The HIL test platform helps teams to create a fully automated pipeline in days. Source: BootLoop

BootLoop’s agent ingests PCB design files and component datasheets to automatically generate tests that validate real hardware behavior down to the register level. The agent connects to serial monitors, debuggers, and test equipment to iterate until the code runs clean. So, test teams can go from zero testing infrastructure to a full CI pipeline on real hardware in hours by using a single command install.

BootLoop—a Y Combinator company founded by SpaceX and MIT Media Lab engineers—covers the entire embedded development lifecycle, including development, testing, and debugging. The company was founded in 2025 and is based in San Francisco.

Related Content

• HIL simulation boosts automotive design efficiency
• Firmware Testing Still Falls Short of What We Need
• Hardware-in-the-loop or digital twin: Use one, both, or neither?
• Accelerate Automotive Dev Time: Fill Hardware-in-the-Loop Gaps
• Hardware-in-the-loop testing for electric vehicle drive applications

The post HIL platform automates tests to validate hardware behavior appeared first on EDN.

Наставниця Ганна Шевлякова: "Вмотивовані учні надихають рухатися вперед" Інформація КП пн, 06/01/2026 - 18:00

Independent power electronics company Quantum Power Transformation (QPT) Ltd of Cambridge, UK — which was founded in 2019 and develops gallium nitride (GaN)-based electric motor controls — has opened customer demonstrations of its MicroDyno test platform, now updated with full field oriented control (FOC) and real-time dynamic cogging correction. The platform is available for in-person demos at QPT’s new R&D facility in Edinburgh, with remote-access demos available for international customers unable to travel...

BluGlass Ltd of Silverwater, Australia — which develops and manufactures gallium nitride (GaN) visible laser diodes based on its proprietary low-temperature, low-hydrogen remote-plasma chemical vapor deposition (RPCVD) technology — has secured a firm commitment of $1m, with the potential to be raised to $1.5m in total, following the execution of a shortall agreement in relation to options with an exercise price of $0.26 which expired on 31 May...

Macro shot taken using Fujifilm XH2 and Laowa 65mm F2.8. submitted by /u/Nightrach [link] [comments]

🎥 Круглий стіл «Механізм безпеки», присвячений механізованому розмінуванню в Україні kpi пн, 06/01/2026 - 15:18

Two devices. Same manufacturer. Similar cosmetics. (Near-)identical dimensions. Different branding. What about the insides?

After taking a month’s break from the TP-Link smart plug family teardown cadence, I’m back for more. This time, we’ll be looking inside the Tapo P105, one member of a four-pack, to be exact.

Back in early December, I’d noted that it was a “seeming Tapo equivalent to the Kasa EP10”, which I’d subsequently dissected for early March publication, and indeed there are many similarities between them:

• The Kasa EP10 has published dimensions of 2.36 x 1.50 x 1.21 in (60 x 38 x 33 mm), while those of the Tapo P105 are near-identical (in imperial units, that is, identical in metric): 2.4 × 1.5 × 1.3 in (60 × 38 × 33 mm)
• They both support switching load currents of up to 15 A
• And they both support Amazon (Alexa), Google (Assistant and Gemini) and Samsung (SmartThings) smart device protocols, in addition to company-proprietary schemes.

A smart plug by any other name…

The last bit of that last bullet, however, is indicative of a minor-at-least deviation between them. The earlier device was the Kasa EP10; this one’s the Tapo P105. Once again requoting my early December piece, appropriately titled “Tapo or Kasa: Which TP-Link ecosystem best suits ya?”:

“Kasa” was TP-Link’s original smart home device brand, predominantly marketed and sold in North America. The company, for reasons that remain unclear to me and others, subsequently, in parallel, rolled out another product line branded as “Tapo” across the rest of the world. Even today, if you visit the “smart plugs” product page on TP-Link’s website, you’ll see a mix of Kasa- and Tapo-branded products. The same goes for wall switches, light bulbs, cameras, and other TP-Link smart home devices. And historically, you needed to have both mobile apps installed to fully control a mixed-brand setup in your home.

Fortunately, TP-Link has made some notable improvements of late, from which I’m reading between the lines and deducing that a full transition to Tapo is the ultimate intended outcome. As I tested and confirmed for myself just a couple of days ago, it’s now possible to manage both legacy Kasa and newer Tapo devices using the same Tapo app; they also leverage a common TP-Link user account…They all remain visible to Alexa, too, and there’s a separate Tapo skill that can also be set up…along with, as with Kasa, support for other services.

A perusal of the outside cosmetics also reveals some differences. The Kasa EP10’s status LED is integrated within the left-side-located multi-function on/off, pairing and reset switch:

whereas the Tapo P105’s status LED is in the top-left corner of the front panel, with the left-side switch now non-illuminated:

…would switch as sweet?

The illumination locational variance between the two devices presumably results in at least some internal-layout deviance between them, but what about the building-block components themselves? Reiterating what I’ve asked before in similar teardown comparison projects, how different (if at all) are these two product generations from a hardware standpoint, versus TP-Link relying solely on software-only differentiation schemes? Let’s find out.

I’ll start with a conceptual internal view to whet your appetite:

As mentioned previously, today’s patient was sourced from a four-pack that I’d acquired during a 2025 Thanksgiving-week Amazon Warehouse-now-Renewed promotion for $18.06 ($25.80 minus 30%). I’ll start with some outer box shots, as usual accompanied by a 0.75″ (19.1 mm) diameter U.S. penny for size comparison purposes.

The “US/1.26” bit in the upper right corner of the product label in the following photo, based on my past experiences with TP-Link gear, is suggestive of hardware v1.26 inside the box. I’ve mentioned before both the company’s tendency for hardware-iteration profusion and the inter-version compatibility problems that can result from it. That said, the Tapo P105 product page on TP-Link’s website lists only hardware versions v1 and v1.2 (but not v1.26) for both the one- and four-pack bundle variants. Dive into the product support page, on the other hand, and four to-date hardware versions are listed there (none of them v1.2, ironically):

• v1
• v1.26 (mine)
• v1.60, and
• v1.80

So…

Onward…

Time to dive inside…

The first things I found were a piece of protective foam, a slip of quick-start literature (PDF), and a small sheet of clear plastic.

What I subsequently realized was that the latter was normally folded in thirds and wrapped around two of the smart plugs. Its sibling was still in place, thereby tipping me off that (at least) one of the two lower devices in the box was removed (and presumably tried out) pre-return by the original purchaser.

Let there (not) be blood

I went with the one in the lower left corner as my dissection victim. Front:

Left side (and upside-down, I subsequently realized):

Back (note the screw head; hold that thought):

Right side (once again upside-down, too):

Top:

And last but not least, the most informative of the lot, the bottom (the penny’s temporarily taped in place from underneath, in case you were wondering):

There’s that US/1.26 notation again, along with the always useful FCC ID (2AXJ4P105):

Remember that screw head I noted earlier? Buh-bye:

I’ve taken apart a few of these devices’ cases by now, so I’ve figured out how to do so without maiming myself like I did the first time (and yes, I realize I’ve just jinxed myself by writing this):

Mission accomplished.

SoC swap motivation: Processing necessity or product availability?

And now for the perspectives you all care about:

The switch, as noted before, is still on the left side:

but whereas with the Kasa EP10, it had been mounted to the same mini-PCB that contained the system SoC:

it’s now standalone, with the mini-PCB lodged in one corner, as already suggested by the earlier-shown conceptual teardown image and presumably to improve wireless connectivity:

The SoC itself is also evolved, from the Realtek RTL87210 to the same dual-core RTL8720 (PDF) found in the Kasa EP25, whose teardown was published in late March.

Note once again the presence of an antenna connector on the module, not used in this particular system implementation.

A relay merry-go-round

Once again on the right side is the blue-colored relay:

this time a Churod A16-V-105DA2F (PDF):

Top and bottom side perspectives follow, for your “edumacation” purposes:

And alas, as with its TP-Link-developed predecessors, I was unable to share with you any perspectives of the PCB backside, although as you might be able to tell from the glimpses in the following shots, there’s not much there to share anyway.

As usual, the FCC certification documentation provides additional visual insights.

And that’s “all” I’ve got for you today! Next up in the TP-Link smart plug dissection series, again as I initially alluded to back in December, I plan to tear down the Tapo P125, which builds on the Tapo P105 foundation with Apple HomeKit (now Apple Home) “smart” support. It’s akin to the earlier Kasa EP10-to-EP25 transition, albeit absent added energy monitoring features this time. Until then, and as always, I welcome your thoughts in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

• Tapo or Kasa: Which TP-Link ecosystem best suits ya?
• TP-Link’s Kasa EP10: If at first it doesn’t connect, buy, buy again
• TP-Link’s Kasa HS103: A smart plug with solid network connectivity
• TP-Link’s Kasa EP25: Energy monitoring for a hoped-for utility bill nose-dive

The post TP-Link’s Tapo P105: A Kasa EP10 clone, or evolutionarily derived? appeared first on EDN.

Microchip’s dsPIC33CK Value Line DSCs offer a streamlined design for cost-sensitive applications and consistent pricing regardless of order size.

Designers of real-time control applications need to balance performance and peripheral integration while keeping system cost and complexity low. To address these challenges, Microchip Technology Inc. introduces the dsPIC33CK Value Line family of Digital Signal Controllers (DSCs) to provide essential real-time control at a competitive price point. By combining up to 100 MHz deterministic processing, high-resolution pulse-width modulation (PWM), and a 12-bit analog-to-digital converter (ADC), Value Line DSCs support motor Field Oriented Control (FOC), touch, and precision sensing applications without the added cost of unnecessary features.

Value Line device dsPIC33CK integrates a balance of peripherals that enable designers to consolidate multiple system functions onto a single device, helping reduce external component count, printed circuit board footprint, and overall Bill-Of-Materials (BoM) cost. With scalable program flash memory options ranging from 32 KB to 256 KB, and compatibility across the broader dsPIC33CK family, Value Line DSCs support scalability while offering migration paths for future needs.

“Not every real-time control design needs a high-end solution; many just need dependable performance at the right cost,” said Joe Thomsen, corporate vice president of Microchip’s digital signal controller business unit.

The dsPIC33CK Value Line delivers the essentials designers rely on most while eliminating complexity and helping provide a straightforward path to building capable, reliable systems without paying for features they don’t need. Offering consistent pricing at any volume makes it easier for customers to plan, scale, and control long-term costs. The dsPIC33CK Value Line family offers consistent and competitive pricing across various purchase volumes, helping simplify device selection during early-stage evaluation and production planning. Automotive-grade reliability, including AEC-Q100 Grade 1 qualification and built-in security features for implementing secure boot and secure firmware updates, helps enable use in industrial, automotive, consumer, and medical applications where dependable real-time operation is required.

Value Line DSCs provide up to 2 ns PWM resolution across eight channels, a 12-bit ADC supporting up to 2 MSPS, on-chip analog comparators with a 12-bit digital-to-analog converter (DAC), and a comprehensive set of communications peripherals including CAN FD, Local Interconnect Network (LIN), Single Edge Nibble Transmission (SENT), Universal Asynchronous Receiver-Transmitter (UART), Serial Peripheral Interface (SPI), and I²C. Together with Microchip’s established dsPIC33CK DSC ecosystem, these capabilities help designers implement precise, reliable real-time control functions within a single device, simplifying system design while supporting use in demanding applications that require long-term dependability and cost efficiency. Visit the website to learn more about Microchip’s full portfolio of digital signal controllers.

Development Tools

To accelerate evaluation and development, Microchip offers a low-cost dsPIC33CK Value Line Curiosity Nano evaluation kit featuring an onboard debugger, eliminating the need for an external programming or debugging tool. The evaluation platform can be used with Microchip’s Curiosity Nano base for Click Boards and the Curiosity Nano touch adapter board for touch-based applications. A Motor Control Dual Inline Module (DIM) is also available to support rapid prototyping of motor control designs. Value Line DSCs are compatible with the MPLAB development ecosystem, including the MPLAB XC-DSC Pro Compiler.

About Microchip Technology

Microchip Technology Inc. is a broadline supplier of semiconductors, and the headquarters is in Chandler, Arizona. It is known for innovative design, easier through total system solutions that address critical challenges at the intersection of emerging technologies and durable end markets. Its easy-to-use development tools and comprehensive product portfolio support customers throughout the design process, from concept to completion. TMicrochip offers outstanding technical support and delivers solutions across the industrial, automotive, consumer, aerospace and defense, communications, and computing markets. For more information, visit the Microchip website at www.microchip.com.

The post Essential Performance Meets Real-time Control in Microchip’s dsPIC33CK appeared first on ELE Times.

Infeneon’s SECORA brings contactless payment to a smart watch and smart ring, which offers fast, convenient, and secure payment technology. With up to 4 billion devices with NFC connectivity by the year 2030, and up to 700 million wearables. The demand for contactless payment is growing rapidly. Infineon Technologies AG introduces SECORA Connect X, a ready-to-integrate solution that enables customers to transform smart wearables into fully functional payment devices. A combination of Infineon’s new SECORA Wallet with SECORA Token Requestor linked to Mastercard (MDES) and Visa (VTS), enabling the digitization of cards and the creation of a custom-brand wallet app. This new SECORA one-stop shop for wearable payment accelerates time-to-market through seamless integration and certification, while offering flexible design, card tokenization, and secured payment functionality for any active wearable.

“SECORA one-stop-shop turns wearables into payment devices certified by Visa and Mastercard with worldwide acceptance at all contactless POS terminals, without the need for a phone or digital wallet,” says Tolgahan Yildiz, Head of the Trusted Mobile Connectivity and Transactions Product Line at Infineon. “Original equipment manufacturers (OEMs) can now launch their own branded payment services across a wide range of smart wearables, leveraging our powerful and secure products.”

Comprehensive Solutions for Secure Payment in Smart Wearables

SECORA Connect X is a highly efficient and secure payment solution for active smart wearables, including smart rings, sports watches, and fitness trackers. The solution features a Secure Element that enables contactless payment with Mastercard, Visa, and many other NFC applications, with payment credentials securely stored on the chip, not in the cloud. As the smallest NFC payment card emulation device on the market, SECORA Connect X provides extremely low power consumption for longer battery life and lower costs thanks to fewer external electronic components. Its compact design fits into any wearable design, regardless of size, shape, or material. Java Card and GlobalPlatform standards support seamless integration through comprehensive development tools, while pre-certified applets and 1 MB of memory allow developers to create custom NFC- and Bluetooth-enabled applications.

In addition, SECORA Wallet and SECORA Token Requestor enable any Secure Element-based smart wearable to support EMVCo payment functionality via card digitization. As a Token Requestor, Infineon can connect directly with payment services such as Mastercard or Visa to request and manage payment tokens, removing Primary Account Numbers (PANs) from the payment chain for added security.

The payment tokenization process stores credit and debit cards directly on the Secure Element, adding an extra layer of security without relying on the cloud. The tokenize wearable is accepted globally at all contactless-enabled POS terminals, without the need for a phone or third-party wallet services. The integrated white-label software development kit (SDK) allows full branding flexibility and frictionless integration into existing OEM apps. SECORA Wallet supports both iOS and Android devices, enabling wide accessibility for end users.

Complementary Solution for IoT

SECORA Connect X and SECORA Connect E are efficient in connecting IoT devices such as AR/VR headsets, laptops/tablets, gaming consoles, and PC accessories. Infineon delivers a full-service offering, from end-to-end design to deployment, and contributes its expertise to a wide range of technical and payment industry bodies, including EMVCo, FiRa, GlobalPlatform, ISO, Java Card Forum, NFC Forum, and Calypso Network Association. As a result, OEMs adopting SECORA solutions benefit from industry-leading security, compliance, and innovation.

Availability

The market launch is planned for Money2020 in Amsterdam from June 2–4, 2026. Demonstrations will take place at the Infineon booth (booth 1C183, entrance F), and Infineon’s experts will be available to provide further information. More information is available at https://www.infineon.com/applications/security-solutions/payment-solutions/one-stop-shop-wearable-payments.

 

The post Infineon’s SECORA Connect X and SECORA Wallet Bring Secure Contactless Payment to Smart Wearables appeared first on ELE Times.

Captured using Fujifilm XH2 and Laowa 65mm F2.8. UV module taken from a Convoy S21A light submitted by /u/Nightrach [link] [comments]

Imagine a component that combines the heavy-duty muscle of a power relay with the surgical precision of a digital signal. That is the essence of a pulse width modulation (PWM) relay. While traditional switches are often strictly binary, the integration of pulse width modulation allows engineers to go beyond simple “on-off” control, enabling significant power savings and reduced heat signatures.

The “PWM relay” myth

While high-speed switching is often associated with the solid-state relay (SSR), the real magic happens when applying these pulses to a standard electromechanical relay (EMR). By modulating the “hold current” of an EMR coil, you can prevent overheating and drastically extend the life of your hardware. Whether you are managing automotive solenoids or optimizing industrial control panels, understanding the synergy between PWM and EMR is the key to transforming a basic mechanical switch into a sophisticated, energy-efficient power management tool.

However, if you head to an electronics distributor, looking for a “PWM relay,” you will likely hit a dead end. You cannot easily buy a dedicated PWM-enabled or PWM-driven EMR off the shelf because PWM is not a physical feature of the relay itself; it’s a control strategy applied by the external circuit.

To achieve this, you typically need a devoted relay driver or a microcontroller to manage the signal. By sending a high-frequency pulse to a standard, inexpensive EMR, you effectively turn a “dumb” mechanical switch into a “smart” energy-saver. While an SSR is natively capable of high-speed switching for load modulation, using PWM with a traditional EMR is specifically about optimizing the coil’s efficiency, allowing you to reap the benefits of mechanical isolation without the drawback of a roasting-hot solenoid.

The “holding current” tweak

Nowadays electromechanical relays are widely used across automation systems because they enable a low-power signal to control a high-power circuit. Yet, the conventional method of relay operation is relatively energy-intensive, often producing excess heat and demanding a sizeable power supply. In practice, energizing a relay requires more power than simply holding it in the active state.

This opens the door to efficiency gains: by applying pulse width modulation to the coil’s holding current, we can reduce the duty cycle and thereby lower the average current. The result is decreased power consumption, less heat generation, and improved thermal management—particularly valuable in applications that employ banks of relays.

As a quick design example, begin by switching the relay driver MOSFET fully on to apply voltage to the coil for at least 100 ms. During this initial energizing phase, set the duty cycle to 100% to ensure the MOSFET is fully on, and the relay pulls in reliably.

Once the relay is engaged, transition to PWM control with a reduced duty cycle—say 50%—to sustain the relay state while cutting power consumption. This approach maintains functionality while significantly lowering average current draw, reducing heat, and improving overall efficiency.

Figure 1 Basic schematic illustrates PWM control for lowering relay coil holding voltage. Source: Author

As an aside, while current is the physical mechanism at play, “holding voltage” is a very common industry term because engineers often think in terms of the voltage applied to the circuit.

Practical switching: EMRs and PWM

On the workbench, additional considerations arise when using PWM to drive EMRs.

In conventional relay designs, the nominal coil voltage must be continuously applied to keep the relay energized, which reduces overall energy efficiency. By contrast, PWM-driven relays can operate with reduced effective coil voltage, significantly lowering power consumption, an advantage in energy-conscious applications.

PWM drivers regulate the effective voltage by adjusting the duty cycle of a DC signal at a fixed frequency. A quick note: Duty cycle is usually given as a percentage, while duty ratio is the same concept expressed as a fraction. Relay coils, being inductive, respond to duty-cycle transitions with current fluctuations. The resulting ripple depends on coil inductance, suppression circuitry, PWM frequency, voltage level, and duty cycle.

Best practice is to begin with a 100% duty cycle until the relay pulls in and stabilizes. The required time varies with relay type and excess voltage but typically falls between 100–500 milliseconds. Afterward, the duty cycle can be reduced to maintain holding current.

Higher PWM frequencies reduce ripple, allowing lower effective coil voltages while keeping other parameters constant. Frequencies in the 20–100 kHz range are generally recommended. Since effective coil voltage equals the product of supply voltage and duty cycle, tight regulation is essential. Even small supply variations demand rapid duty-cycle adjustment—within a few milliseconds—to prevent the effective voltage from dropping below the relay’s minimum requirement.

For reliable performance, coil current must always exceed the holding current plus a margin for shock and vibration. If current falls below this threshold, the armature may release, causing repeated pull-in cycles. Such instability can lead to humming noise, unintended contact opening under load, or even contact welding.

Notably, an increasing range of EMRs now support PWM-regulated holding currents to improve thermal management and efficiency. By modulating the duty cycle once the armature is seated, these relays minimize steady-state power dissipation. The Omron G2RL-1A-E-PW1 exemplifies this trend, featuring a coil architecture optimized for PWM and reduced-voltage holding.

Figure 2 The G2RL-1A-E-PW1 relay utilizes PWM control to minimize coil power consumption and heat. Source: Omron

What is more, dedicated PWM current controllers like DRV110 and DRV120 are specifically engineered to optimize relay and solenoid operation through precise waveform regulation. These ICs rapidly ramp the current to a peak level to ensure the plunger or contactor fully seats.

Once actuation is confirmed, they transition to a significantly lower hold current, which maintains the magnetic field while drastically reducing power dissipation. By managing this peak-to-hold transition automatically, these controllers prevent thermal overhead and extend the operating life of the inductive load.

Figure 3 A prewired DRV120 module empowers makers and experimenters to slash relay power consumption by automatically transitioning from pull-in to hold current. Source: tindie

Clever pulses never stop

Where does this leave us? Whether through basic RC mechanisms, dedicated integrated solutions, or the efficiency gains of PWM applied to electromechanical relays, engineers have a wide range of proven strategies to reduce relay energy consumption.

This is more significant nowadays in the era of EVs and e-mobility, where every watt saved translates into extended range and smarter system design. Yet beyond the established lies the experiment, where unproven methods await bold exploration.

Energy efficiency is not just about saving power; it’s about sparking possibilities, and the next breakthrough may come from your own trial and error. If you have worked with PWM-driven electromechanical relays or discovered alternative approaches, share your insights in the comments and help expand the collective knowledge base for engineers everywhere.

T. K. Hareendran is a self-taught electronics enthusiast with a strong passion for innovative circuit design and hands-on technology. He develops both experimental and practical electronic projects, documenting and sharing his work to support fellow tinkerers and learners. Beyond the workbench, he dedicates time to technical writing and hardware evaluations to contribute meaningfully to the maker community.

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• Relays Are Great, But There’s No Need to Let Them Waste Power
• Relay and solenoid driver circuit doubles supply voltage to conserve sustaining power

The post The pulse of power: Mastering the PWM relay appeared first on EDN.

Qorvo, a leading global provider of connectivity and power solutions, today announces a new family of RF switches that simplifies multi-band radio architectures. Spanning 50 MHz to 10 GHz, the family reduces component count, improves signal integrity, and enables more efficient RF system design across 5G infrastructure, industrial, drone, and test applications.

As 5G radios expand to support wider bandwidths and more frequency bands, including emerging spectrum such as FR3, designers face increasing challenges maintaining isolation and signal integrity without adding size, loss, and complexity. Many current designs rely on cascaded switch architectures or multiple narrowband devices, increasing insertion loss, degrading linearity and signal integrity, and adding board space and design effort.

“Designers no longer have to rely on cascaded switch architectures to achieve high isolation. We’re delivering that performance in a single device across a very wide bandwidth,” said Debbie Gibson, general manager of Qorvo’s infrastructure business. This approach reduces insertion loss, maintains signal linearity, and simplifies design, improving receiver performance in applications such as digital pre-distortion (DPD) feedback.

Qorvo’s new QPC6144 is a SP4T wideband switch that delivers greater than 65 dB isolation in a single device. Complementing this capability, the QPC6122 (SP2T) and QPC6188 (SP4T) provide wideband absorptive switching across 50 MHz to 10 GHz, enabling a single platform approach to RF routing. These devices reduce component count and simplify design while maintaining low insertion loss and strong linearity across wide bandwidths for calibration paths, general signal routing, and multi-band operation.

The new family of devices forms a dual switching platform that supports both high-isolation and general-purpose routing. By consolidating switching functions into fewer components, engineers can reduce BOM complexity, simplify layouts, and accelerate development across multiple applications.

Product	Key Role	Solves	Typical Use
QPC6144	High-isolation switching	Eliminates cascaded switches with >65 dB isolation in a single device	DPD feedback, calibration paths, high-isolation paths in 5G radios, and advanced drone communications
QPC6122	Compact wideband switching	Reduces component count while maintaining low insertion loss and signal linearity across wide bandwidths	Calibration paths, space-constrained RF routing in compact RF modules, and drones
QPC6188	Flexible wideband routing	Simplifies multi-path RF routing while maintaining low loss and signal linearity across multiple bands	Switching networks in infrastructure, industrial, drone, and test system applications

Samples are available through Qorvo. Visit the Qorvo IMS hub for more information.

About Qorvo

Qorvo supplies innovative semiconductor solutions that make a better world possible.  It combines product and technology leadership, systems level expertise, and global manufacturing scale to quickly solve customers’ most complex technical challenges.  Qorvo serves diverse high-growth segments of large global markets, including automotive, consumer, defense & aerospace, industrial & enterprise, and infrastructure. and mobile.  Visit www.qorvo.com to learn how a diverse and innovative team.

The post Qorvo drops Cascaded Switches with New Wideband 5G High-Isolation Family appeared first on ELE Times.

For coverage of all the key business and technology developments in compound semiconductors and advanced silicon materials and devices over the last month...

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I added RGB backlighting to my RAM stick to get +20 fps. submitted by /u/mmSTEA [link] [comments]

This is a heart-shaped LED keychain I made. submitted by /u/Federal_Door_9998 [link] [comments]