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At the Optical Fiber Communication Conference and Exhibition (OFC 2026) in Los Angeles (15–19 March), photonic application-specific integrated circuit (PASIC) chip designer and manufacturer OpenLight of Goleta, Santa Barbara, CA, USA (which launched as an independent company in June 2022, introducing the first open silicon photonics platform with heterogeneously integrated III-V lasers, modulators, amplifiers and detectors) showcased multiple technology breakthroughs, including demonstrating its latest advances in high speed photonic integrated circuits (PICs) with integrated lasers, electro-absorption (EA) modulators, and amplifiers. The demonstrations showed next generation optical architectures designed to meet the performance, efficiency and scalability demands of AI, cloud and hyperscale data-center networks...

Photonic application-specific integrated circuit (PASIC) chip designer and manufacturer OpenLight of Goleta, Santa Barbara, CA, USA (which launched as an independent company in June 2022, introducing the first open silicon photonics platform with heterogeneously integrated III-V lasers, modulators, amplifiers and detectors) has announced continued progress in its ecosystem partnership with Suzhou TFC Optical Communication Co Ltd (a provider of optical sub-assembly integrated solutions and advanced optoelectronic package manufacturing services), building on the collaboration first announced in 2025 to fast track the back-end process for silicon photonics production and optical communication systems...

We’ve come to expect the U.S.-based global positioning system (GPS) to be available and ubiquitous for the countless military, commercial, and consumer applications dependent on it. Its diverse uses represent a huge leap from its original military-centric objective for determining an object’s precise location (positioning), chart its path to a destination (navigation), and manage its movement along that path (guidance)—usually summarized as PNG.

Applications that were not even conceived, let alone doable, are now enabled by tiny GPS ICs and systems that provide amazingly accurate and precise results—you can make your own list here.

If you want some insight into the people who made GPS happen despite severe technical and bureaucratic obstacles, check out Pinpoint: How GPS Is Changing Technology, Culture, and Our Minds by Greg Milner. Though somewhat dated now in its discussion of social implications, this fascinating book from 2016 tells the story of GPS from its conceptual origins as a bomb guidance system to its presence in almost everything we do.

Despite the sense that GPS is everywhere, the reality is that it was never the situation. Underwater, tunnels, indoor sites, and similar RF-blocked locations simply can’t receive enough of the relatively weak satellite signals to provide a viable result.

Now, we’re seeing many more situations where GPS signals are also being “denied” due to deliberate interference or spoofed via false signals by players with various motives. Some of the consequences are modest (lost dogs can’t be found), but others have more serious implications.

One possible solution is to increase the power of the transmitted signals, but that’s technically difficult and won’t happen for years even if and when it does—and doing so will still not help in many of these cases.

Alternatives to GPS

There’s a significant amount of research and product development toward devising ways to provide PNG using non-GPS, non-RF techniques driven by sensors for which jamming or signal access is not an issue. All of them require a considerable amount of computation to make sense of the sensed signals and transform data into results; none of them provide the performance of a GPS-based system—at least not yet. Much of the R&D work is being done by startups and innovators, in addition to traditional sensor vendors.

Among the non-GPS possibilities are:

• Inertial sensing

This is not new, of course, and has been used for decades, beginning with gyroscopes and accelerometers. Both sensors are now reduced to small, low-power MEMS devices that are orders of magnitude smaller, lighter, and lower-power than their electromechanical predecessors of just a few decades ago and even compared to the laser and fiber-optic versions that leverage the Sagnac effect and interferometry. Still, their accuracy is not as good as a high-end GPS system, but it’s improving.

For example, ANELLO Photonics has developed a silicon photonics optical gyroscope—dubbed SiPhOG—that uses an on-chip waveguide manufacturing process, integrated with a patented silicon photonic integrated circuit (Figure 1). Together, they claim these offer fiber-optic gyro performance with a standard silicon manufacturing process.

Figure 1 This silicon photonics optical gyroscope uses an on-chip waveguide manufacturing process that is integrated with a patented silicon photonic IC. Source: ANELLO Photonics

• Magnetic sensors

The Earth’s magnetic field is pervasive, ubiquitous, and unjammable. It’s also uneven, with highly localized variations due to differences in the Earth’s outer-crust and under-crust layers as well as deeper causes (literally) from flows of conducting material within the Earth (Figure 2).

Figure 2 This geomagnetic map of part of the Northern hemisphere is a starting point for more detailed, higher-resolution images and variations, and changes that must be captured for effective magnetic navigation. Source: Geomag

Using supersensitive quantum-based magnetic sensors based on optically pumped, cesium-based, split-beam scalar magnetometers, which have an absolute accuracy between one and three nanoteslas, it’s possible to read that field with high precision. The Earth’s core field has values ranging from 25 to 65 microtesla (that’s 0.25 to 0.65 gauss) at the surface while magnetic anomaly field of interest typically varies by just hundreds of nanotesla.

The readings are then matched to pre-existing maps of Earth’s field. This scheme has the disadvantage of not being very accurate compared to GPS, partially because the Earth’s magnetic field is not static and matching maps need constant updating.

Despite these challenges, companies such as SandboxAQ have developed a navigation technology (AQNav) that leverages proprietary large quantitative models (LQMs) and powerful quantum sensors to make use of the Earth’s crustal magnetic field. By combining high-sensitivity magnetometers with AI algorithms to identify unique magnetic patterns and locate position in real time, it’s possible to determine position in that field. The sensing is entirely passive, so users remain undetected.

• Visual matching

This uses a simple concept of matching what a camera sees to the verified landmarks on a map. Visual terrain-following has been used for decades in cruise missiles which follow a precise terrain-image pattern. Orders-of-magnitude improvements in imaging quality and the associated algorithms needed to process and match the observed image to the map now make this technology even more precise.

One vendor pursuing this approach is Vermeer Corp. Their system uses between one and four electro-optical/infrared camera feeds simultaneously to map real-time video to a locally stored 2.5D or 3D map database to generate an accurate location signal.

• Celestial navigation

This classic approach to navigation now uses modern, automated versions of the transit, celestial charts and precise clocks, aided by computerized calculations. This is a case of “back to the future” but in a new form and implementation.

• E-LORAN

LOng-RAnge Navigation was a hyperbolic radio navigation system developed by the United States during World War II. The third iteration, LORAN-C, was initiated in the late 1960s, but the stations and system were decommissioned in the 1990s due to the availability and performance of GPS.

It uses the differences in timing of received signals from multiple high-power transmitters in the 100-kHz band (yes, that’s kilohertz) to developed positioning information.

Enhanced LORAN is a standard which builds on the now obsolete LORAN system by putting more information into the modulation of the carrier as well as adding a data channel. Like LORAN, E-LORAN offers some benefits such as near-impossibility of jamming and spoofing, but it also requires many high-power transmitters and many of these need to be in inhospitable or remote locations which are difficult to support (Figure 3).

Figure 3 Like its predecessor LORAN, the enhanced LORAN system will require an extensive physical infrastructure located around the world. Source: UrsaNav

While E-LORAN proponents are eternally hopeful, the project has had difficulty getting traction and support due to technical challenges (primarily at the transmitter side), very high up-front infrastructure costs, and best-case accuracy of about 50 to 100 meters (although there are proposed ways to improve that number).

The realities of dealing with a GPS-unavailable world

Many of these alternatives are being enabled by advances in quantum-based sensors. Some may even require supercooled arrangements with all the obvious downsides of that requirement. Each of them offers the virtue of not being jammable or denied.

At the same time, none offers the amazing accuracy and simplicity of GPS for the user. No single technology offers anything close to GPS. A viable alternative, even with reduced accuracy, will require advances in sensors and gigabytes of support data such as maps. Any GPS alternative will also require tight fusion and merging of unrelated sensor technologies and outputs, huge datasets, and extensive use of AI and machine learning to create useful results.

It will be fascinating to see which one of these, if any, takes a dominant role in non-GPS settings, or will it be a balanced fusion? Perhaps some unexpected physical phenomenon will come from behind, as has happened so often in the past. As they say, “predictions are very hard to make, especially about the future.”

Related Content

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• Navigating without GPS requires advanced sensors, intensive analog
• Sophisticated Sensors, Extreme Conditioning, Advanced Algorithms Yield Amazing Geolocation Results

The post GPS-free systems to spur highly advanced sensors, fusion appeared first on EDN.

Took the laser PCB process a bit further and pushed this one to a fully working board. The vias are drilled with a sub-mm bit and stitched manually with wire to tie the planes together. It’s basically sewing the board to keep the return path tight. Main goal here was reducing loop inductance as much as possible since this is driving a SiC switching stage. Not trying to replace fab boards, but for fast iteration this is actually way more capable than I expected. Still experimenting with how far this approach can go in terms of switching performance vs a proper manufactured board. submitted by /u/Intelligent_Raise_40 [link] [comments]

Hey, I built a Bluetooth audio amp based around the TPA3110. The QCC5125 uses differential audio signals for the TPA. I had to cut some ground lanes on the PCB for it to work because those cheap TPA boards use the same ground. USB trigger board for a 12V linear reg to an isolated 5V converter. Works really good; I only hear a quiet noise about 2-3cm in front of the speaker. I have 2x 15W 4-ohm speakers. What do you think? Anything to add, or just finish it with a case? submitted by /u/Busy-Amphibian-4317 [link] [comments]

I wish I had been smart and careful enough not to use a freerouter. submitted by /u/nemo_o_ [link] [comments]

submitted by /u/liamkinne [link] [comments]

I'm honestly so happy I finally got it to work. I'm new to his but I love figuring out the ins and outs. submitted by /u/kittenkween12 [link] [comments]

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Not sure how you all feel about LLMs, but I have been letting Claude get involved in my electronics projects recently. After a great deal of experimentation using Rigol DS1054Z over LAN with Claude Code, I've built a small MCP server that lets Claude fully drive the scope. It exposes things like: configuring channels / trigger / timebase running measurements (Vpp, frequency, etc.) downloading waveform data with basic heuristics for Claude to plan around capturing screenshots that Claude can view It's just SCPI with Python, but wrapping it as MCP tools makes it surprisingly usable for iterative diagnosis! Repo: https://github.com/erebusnz/rigol-mcp Curious if anyone else is using Claude for their electrical engineering. Claude is surprisingly good. Example use: Here's a real example with a frequency generator + LCR connected to Channel 2 but with Channel 1 set up (incorrectly). Claude was able to get the waveform visible and correctly guess what it was seeing. using my rigol scope figure out how to get a clean measurement ● rigol.idn RIGOL TECHNOLOGIES,DS1104Z,... ● rigol.get_scope_state CH1 active, 10x probe, 1V/div, DC Scope STOPped Trigger level: 0V Channel offset: ~1.68V → Trigger mismatch → unstable/dirty capture → Running autoscale... ● rigol.autoscale → Signal detected on CH2 (not CH1) → Trigger locked (TD) on CH2 ~0V ● rigol.measure(CH2, FREQUENCY) 1.298701e+06 Hz ● rigol.measure(CH2, VPP) 5.08 V ● rigol.measure(CH2, VRMS) 0.723 V ● rigol.screenshot [captured] ✓ Clean measurement achieved Results: Frequency: ~1.30 MHz Vpp: ~5.08 V Vrms: ~721 mV Waveform: Step response with damped ringing → square wave exciting an LC resonance submitted by /u/stigm [link] [comments]

Since i'm planning to build a bigger batch of USBpwrMe i actually need to test each unit in a fast and repeatable way. Therefore i have designed a test jig that will measure all functions. There are 2 voltage regulators that will supply the test jig itself with 5V but also a 6V regulator to be able to make a test of an over voltage circuit with a threshold of 5.6-5.7V. INA139 will monitor the current of the DUT thru a shunt of 0.5 ohm or less. This will be optimized depending on what the DUT will actually consume. On the test jig board a PIC Mcu will control and manage the whole test and test instructions and results will be presented on a 2x16lcd display. The test is not high tech but the DUT must be manipulated with external resistors and voltages to be tested. This is mostly handled by 3 relays. Connection to the DUT will be easy using the banana connectors and the USB outputs which has corresponding mating connectors on the test jig. Following steps will be performed 1 It will measure the current consumption of the board to see if there is excessive power consumption 2 It will change polarity on the DUT and measure if there is any voltage on the output. 3 It will will apply resistors on the D+ and D- lines och the USB-A connector and measure so that expected voltage appears. 4 It will apply resistors on the CC1 and CC2 line for the USB-C connector. Vbus1, Vbus2, CC1 and CC2 are measured. If negotiation is correct it will enable Vbus. 5 It will change input voltage from 5V to 6V and test so that the OVP protection works. 6 Finally it will test the OVP mode switch by telling user to turn of OVP. And measures that Vbus goes on. The test will hopefully test a unit under 5s. The Gerber files are already sent to manufacturer and are in production. Now you might wonder why a choose a to small board that won't fit the display. Well at first i did. And when i uploaded the gerbers files it was around 40Usd to get it manufactured and shipped. By reducing the height of the board with 3cm the cost was 12Usd. Since it's only a testjigg and will be put into a casing i rather save some money!!! The PCB has 4 layer stack up. Not really needed but it's much easier to route the signals and takes less time. The schematic and routing took around 5hours. Funny thing is that the test jig is way more advanced than the product it is itended to test :) :) submitted by /u/KS-Elektronikdesign [link] [comments]

Photonic application-specific integrated circuit (PASIC) chip designer and manufacturer OpenLight of Goleta, near Santa Barbara, CA, USA (which launched as an independent company in June 2022, introducing the first open silicon photonics platform with heterogeneously integrated III-V lasers, modulators, amplifiers and detectors) has announced sample availability of its first heterogeneously integrated silicon photonics-based 3.2T DR8 photonic integrated circuit (PIC)...

For fourth-quarter 2025, epitaxial deposition and process equipment maker Veeco Instruments Inc of Plainview, NY, USA has reported revenue of $165m, down 9.4% on $182.1m a year ago but roughly flat on Q3/2025’s $165.9m...

Photonic application-specific integrated circuit (PASIC) chip designer and manufacturer OpenLight of Goleta, near Santa Barbara, CA, USA (which launched as an independent company in June 2022, introducing the first open silicon photonics platform with heterogeneously integrated III-V lasers, modulators, amplifiers and detectors) has announced the first volume production orders by a customer on its PH18DA indium phosphide (InP) on silicon photonic platform, developed in collaboration with specialty analog foundry Tower Semiconductor Ltd of Migdal Haemek, Israel. Based on NewPhotonics 800G and 1.6T laser-integrated photonic integrated circuit (PIC) solution, this marks a step towards bringing highly integrated, laser-enabled photonic ICs into high-volume production for AI and hyperscale data-center networks...

У КПІ ім. Ігоря Сікорського розпочав роботу уповноважений підрозділ з питань запобігання та виявлення корупції kpi пт, 03/20/2026 - 15:19

It was with humble spirit and a good dose of Mea Culpa that a semiconductor company, from whom some very large-scale digital large-scale integration (LSI) chips were purchased, had a problem (later corrected, thank goodness) in that their chips would malfunction when powering up if their +5V rail voltage rose too slowly as the system was being turned on.

The vendor’s recommendation was to apply a 0 V (off) to +5 V (on) rail voltage with a steeper rise time (< 45 ms) than our power supply could deliver. We decided that we needed a switching arrangement that would operate as follows in Figure 1.

Figure 1 Providing a steep +5-V rail voltage rise time. 

One problem with making something like this was that the input voltage could indeed rise very slowly through ½ volt to 1 volt to 2 volts, and so forth, which were voltage levels that were well below specification limits for any voltage monitoring IC we could find.

The resulting operations were erratic and unpredictable at arbitrarily low input voltages. This did not help the LSI situation even one little bit. (Yes, I am aware of the pun.)

Remedy was achieved using the following circuit in Figure 2. 

Figure 2 Rail voltage switch, four loads.

The result obtained was as follows:

Figure 3 Rail voltage delay and rise time speedup.

This worked predictably down to arbitrarily low power supply voltages because there would be no response whatsoever, as long as the TLV431 didn’t see some voltage high enough to get itself conducting.

When the power supply voltage did get high enough to turn on the TLV431 at the time we’re calling “t1”, the power MOSFETs would turn on, and there would be a downward but very short-duration transient voltage drop from the power supply, which would be recovered from very quickly. The rail voltage thus presented to the LSI chips had a sufficiently quick rise time of its own to make those chips happy.

The end result made a bunch of human beings happy, too.

John Dunn is an electronics consultant and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

Related Content

• Silly Simple Supply Sequencing
• Power-Supply Sequencing for Low-Voltage Processors
• Shunt Regulator Eases Power-Supply Start-Up Woes
• Use a TL431 Shunt Regulator to Limit High AC Input Voltage
• Fundamentals of Designing with MOSFET Power Switches

The post Vcc delay appeared first on EDN.

The Electronic Industries Association of India (ELCINA), India’s leading association of electronics manufacturers, welcomes the Government’s announcement of the Bharat Audyogik Vikas Yojana (BHAVYA) scheme, with a Rs. 33,600 crore outlay, aimed at developing India’s industrial manufacturing ecosystem. The BHAVYA scheme would support India’s transformation into a globally competitive, self-reliant electronics, components, and semiconductor ecosystem.

Welcoming the BHAVYA scheme, Rajoo Goel, Secretary General, ELCINA, said: “The Government has announced the BHAVYA scheme at an opportune time and stands to significantly strengthen the ecosystem and the value chain. Through cluster-based promotion, BHAVYA can co-locate OEMs, component suppliers, logistics providers, and service providers within the same industrial park, which is exactly what a deeper ecosystem for electronics and semiconductors requires. At ELCINA, we are excited to see how this scheme will transform the industry over the next few years.”

ELCINA President, Dr Sasikumar Gendham, lauded the scheme as “it would complement the EMC Schemes of MeitY under which several Electronics Manufacturing Clusters had been initiated and industries set up. BHAVYA would catalyse this further and suggested that existing Clusters should also be allowed to benefit from the Scheme and enhance their infrastructure further”.

The plug-and-play industrial ecosystems will help industry players – both existing and new – cut down on the setup phase and move more quickly towards production. Additionally, with streamlined approvals, effective single-window systems, and investor-friendly reforms led by states, the industry would be in a better position to address the critical need to reduce import dependence and position the country as a credible export and supply-chain hub.

ELCINA also lauds the Government’s broader goals of job creation, investment, and economic growth across states. BHAVYA is expected to enhance the supply chain while creating new opportunities for Indians who stand to benefit from the country’s manufacturing growth, particularly in the electronics sector.

The post Government’s Rs. 33,600 crore BHAVYA Scheme Strengthens India’s Electronics, Components, Semiconductor Manufacturing Industries: ELCINA appeared first on ELE Times.

Part 1 of this article series on gallium nitride (GaN) fundamentals described crystal structures and the formation of the two-dimensional electron gas (2DEG), along with material figures of merit and the transition from depletion-mode to enhancement-mode GaN HEMTs.

Part 2 will outline hybrid structures and the RDS(on)  penalty, as well as provide further details on GaN HEMTs and substrate choices for GaN. It will also make the case for the path to monolithic integration while showing how ohmic contacts, metallization, and packaging advantages are facilitating this design roadmap.

Figure 1 Schematic of low-voltage enhancement-mode silicon MOSFET is shown in series with a depletion-mode GaN HEMT: Cascode circuit (a) and enable/direct-drive circuit (b). Source: Efficient Power Conversion (EPC)

An alternative to monolithic enhancement-mode GaN transistors is the hybrid cascode configuration, pairing a low-voltage enhancement-mode silicon MOSFET with a high-voltage depletion-mode GaN HEMT in series. Figure 1 above illustrates two variants.

The cascode configuration, in particular, is highlighted as a pragmatic intermediate solution: a low-voltage enhancement-mode Si MOSFET is connected in series with a high-voltage d-mode GaN HEMT. The MOSFET gate is the external control terminal; when it turns on, the GaN gate-source is pulled close to zero and the HEMT conducts. When the MOSFET turns off, the GaN gate sees a negative bias through the MOSFET, turning off the high electron mobility transistor (HEMT) and providing normally-off behavior at the system level.

A natural question is how much extra RDS(on) the silicon MOSFET adds to the GaN device. Figure 2 shows a useful plot of the percentage contribution of the MOSFET to total RDS(on) versus the rated voltage of the cascode system. At high voltage, the GaN device dominates, and the MOSFET contribution becomes small.

Figure 2 Percentage RDS(on) contribution from the low-voltage MOSFET in a cascode configuration is shown as a function of the rated breakdown voltage of the composite device. Source: Efficient Power Conversion (EPC)

From this chart, a 600-V cascode device adds only around 3% extra RDS(on) due to the low-voltage MOSFET, because the GaN HEMT’s drift resistance dominates at such high voltage. At lower voltages, the GaN device resistance drops rapidly with VBR, so the MOSFET contribution becomes increasingly significant. For this reason, cascode solutions are practical and attractive for higher voltages (above roughly 200 V), whereas for 100–150 V class devices, monolithic e-mode GaN is generally preferable.

The direct-drive (enable) variant exposes the depletion-mode GaN gate directly to the external driver (typically 0 V on, -12 to -14 V off). The silicon MOSFET serves as a safety “enable” switch, connected to the gate driver’s undervoltage lockout (UVLO). During normal operation, the silicon device remains on and experiences no switching; it only blocks the GaN gate if supply fails. This configuration offers precise control of GaN dynamics but requires bipolar drive capability.

Reverse conduction in HEMT transistors

Reverse conduction behavior is a clear advantage of enhancement-mode GaN HEMTs. The source potential increases in relation to the gate when current is forced from the source to drain while the device is nominally off.

This process continues until the threshold condition for the formation of 2DEG is reached beneath the gate region. The channel now reorganizes and conducts in the opposite direction. Unlike the body diode of a silicon MOSFET, which depends on minority-carrier injection and storage, this is a majority-carrier mechanism. So, there is no stored minority charge and consequently no reverse-recovery penalty.

A positive gate voltage establishes the 2DEG channel during forward conduction, enabling current to move from the drain to the source. When reverse conduction occurs, as it does during a synchronous rectifier’s dead time, current moves from the source to the drain when the drain is at least the threshold voltage lower than the gate.

Conduction is then determined by channel resistance, and the device functions similarly to a low-drop diode. In contrast to silicon MOSFETs, which suffer reverse-recovery losses because of charge storage effects, current almost immediately stops once the reverse bias is eliminated.

Vertical GaN and substrate choices

Instead of using lateral 2DEG transport, vertical GaN transistors employ a conduction path perpendicular to the wafer surface. In a typical structure, p-GaN regions linked to the source extend from the surface toward the drain, and the drain contact is positioned at the bottom of a thick n-GaN drift region. When a negative gate voltage is applied, the n-GaN between the p-regions beneath the gate is depleted, preventing current flow.

The depleted region collapses and electrons move vertically from source to drain when the gate is positively biased. This architecture has the potential to compete with high-voltage SiC devices because it can support breakdown voltages above 1000 V while maintaining quick switching. The sub-650 V market is dominated by lateral GaN, mainly because silicon substrates are more affordable and scalable.

The cost of standard 200-mm silicon wafers is only a few tens of dollars per wafer, which enables direct reuse of established CMOS fabs and high-volume manufacturing, including the potential for monolithic integration of sensing circuits and drivers. Bulk GaN substrates for vertical devices, on the other hand, are still restricted to small diameters (usually ≤150 mm) and cost several hundred to over a thousand dollars per wafer, or tens of dollars per cm². This severely limits cost competitiveness at mid voltages.

From a performance perspective, lateral GaN HEMTs benefit from the creation of a high-density 2DEG, which offers exceptionally high electron mobility and low channel resistance. This translates into excellent light-load efficiency and high-frequency operation, which are essential for applications like DC-DC converters, server power supplies, telecom, and consumer fast chargers.

Vertical architectures, currently dominated by SiC MOSFETs, continue to be the preferred solution for voltages above ~900 V because they provide superior robustness at high electric fields and decouple blocking voltage from lateral device dimensions. While SiC and future vertical GaN aim for high-voltage applications, lateral GaN emphasizes cost-performance optimization over voltage scaling in this regime, solidifying its leadership in the mid-voltage range.

Building a GaN HEMT transistor

Fabrication of a GaN HEMT begins with epitaxial growth of the GaN/AlGaN heterostructure on a foreign substrate. Unlike silicon devices, where the active layer matches the substrate, GaN HEMTs require heteroepitaxy, growing a wurtzite crystal on a substrate with mismatched lattice constant and thermal expansion.

Four substrate materials dominate: bulk GaN, sapphire (Al₂O₃), silicon carbide (SiC), and silicon (Si). Each offers trade-offs in lattice mismatch, thermal expansion coefficient, thermal conductivity, and cost. Silicon (111) orientation substrates have emerged as the commercial workhorse due to their low cost ($1–2 per 200 mm wafer) and compatibility with existing CMOS fabrication infrastructure, despite a 17% lattice mismatch (a_GaN = 3.189 Å vs. a_Si = 3.84 Å) and thermal expansion difference of 3 × 10⁻⁶ K⁻¹.

Heteroepitaxy grows one crystal on a dissimilar substrate. Metal-organic chemical vapor deposition (MOCVD) deposits the GaN/AlGaN layers. The process starts with an AlN seed layer on the substrate to initiate nucleation. An AlGaN buffer layer creates the transition to pure GaN crystal structure. A thick GaN layer forms the semi-insulating base. Finally, a thin AlGaN barrier layer induces strain that forms the 2DEG conduction channel.

Figure 3 illustrates the complete epitaxial stack from substrate to 2DEG interface. For enhancement-mode devices, a p-GaN cap layer grows atop the AlGaN barrier, introducing positive charge to deplete the 2DEG at zero gate bias (Figure 4). This stack enables lateral electron transport parallel to the surface, distinguishing GaN HEMTs from vertical silicon MOSFETs.

Figure 3 The illustration highlights basic steps involved in creating a GaN heteroepitaxial structure: Starting silicon substrate (a), aluminum nitride (AlN) seed layer grown (b), various Al GaN layers grown to transition the lattice from AlN to GaN (c), GaN layer grown (d), and AlGaN barrier layer grown (e). Source: Efficient Power Conversion (EPC)

Figure 4 An additional GaN layer, doped with p-type impurities, can be added to the heteroepitaxy process when producing an enhancement-mode device. Source: Efficient Power Conversion (EPC)

Ohmic contacts and metallization

Source and drain electrodes must form low-resistance ohmic contacts to the 2DEG, penetrating the AlGaN barrier. Multiple metal layers and high-temperature annealing create reliable shunts. The gate electrode sits atop the AlGaN (or p-GaN), modulating the channel via electric field.

Back-end processing adds multilevel copper interconnects with tungsten vias, scaling gate width across thousands of parallel cells. Final passivation (SiNₓ) protects the surface and shapes electric fields to prevent premature breakdown.

Chip-scale packages (BGA and LGA) minimize parasitics, supporting megahertz switching with minimal ringing. Recent advances in QFN (Quad, Flad, No-Lead) have brought packaging alternatives that have minimal compromises in parasitic inductance, resistance, and thermal conductivity.

In either chip-scale of QFN packages, lateral conduction enables bottom-side cooling and ultra-low inductance packaging. Ball grid array (BGA) formats use SnAgCu micro-bumps (150 µm pitch) for 100–650 V devices (1.5 × 1.0 mm² footprint). LGA variants (3.9 × 2.6 mm²) handle 100 V half-bridges at 10 A continuous. Package loop inductance drops below 0.2 nH, supporting dI/dt >2000 A/µs without significant ringing—impossible in wire-bonded discrete packages

The path to monolithic integration

The lateral architecture of GaN HEMTs—where current flows parallel to the surface—eliminates the need for deep vertical vias or trenches, enabling unprecedented levels of monolithic integration. Unlike vertical silicon or SiC devices, multiple passive and signal-level transistors and passive components occupy the same epitaxial plane, with interconnects formed in overlying metal layers. This allows fabrication of complete power stages on a single die smaller than a grain of rice.

Figure 5 A typical process creates solder bars on an enhancement-mode GaN HEMT (not to scale). Source: Efficient Power Conversion (EPC)

Monolithic GaN stages eliminate interconnect parasitics that plague discrete implementations:

• No bond wires: Package inductance <0.2 nH vs. 1–5 nH with discrete multi-chip QFN
• Zero common source and gate loop inductance
• Pin count reduction: 99% fewer external connections vs. discrete half-bridge + drivers

Compared to silicon DrMOS (driver + MOSFET), GaN integration yields:

• 10× lower QG → MHz switching without excessive gate losses
• Zero QRR → no reverse recovery in synchronous rectification
• 25× smaller die area → lower cost at equivalent performance

Maurizio Di Paolo Emilio is director of global marketing communications at Efficient Power Conversion (EPC), where he manages worldwide initiatives to showcase the company’s GaN innovations. He is a prolific technical author of books on GaN, SiC, energy harvesting and data acquisition and control systems, and has extensive experience as editor of technical publications for power electronics, wide bandgap semiconductors, and embedded systems.

Editor’s Note:

The content in this article uses references and technical data from the book GaN Power Devices for Efficient Power Conversion (Fourth Edition) authored by Alex Lidow, Michael de Rooij, John Glaser, Alejandro Pozo Arribas, Shengke Zhang, Marco Palma, David Reusch, Johan Strydom.

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• The advantages of Vertical GaN Technology
• A brief history of gallium nitride (GaN) semiconductors
• A new IDM era kickstarts in the gallium nitride (GaN) world
• New GaN Technology Makes Driving GaN-Based HEMTs Easier

The post GaN fundamentals: Hybrid structures, HEMT, and substrate choices appeared first on EDN.

HENSOLDT of Taufkirchen near Munich, Germany (which develops sensor solutions, electronics and software for the air, land, sea, cyber and space domains) has signed a long-term supply agreement with United Monolithic Semiconductors GmbH (UMS, which designs and produces RF and millimeter-wave components and ICs at its facilities in Villebon sur Yvette, France and Ulm, Germany). By 2030, UMS will supply a total of 900,000 gallium nitride components for HENSOLDT radars...

The University of Warwick has secured new funding to boost the UK’s ability to test the reliability of advanced semiconductors used in electric vehicles, renewable energy, and other critical technologies...