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AXT Inc of Fremont, CA, USA — which makes gallium arsenide (GaAs), indium phosphide (InP) and germanium (Ge) substrates and raw materials at plants in China — has appointed Jia-Bin Duh to its board, increasing the number of directors to six...

The aerospace industry is undergoing a profound power architecture shift. For decades, radiation-hardened (rad-hard) silicon MOSFETs were the undisputed workhorses of spaceborne DC-DC converters. However, as modern satellite payloads demand higher efficiency, tighter density, and lower mass, silicon is hitting its physical limits.

Enter gallium nitride (GaN) high electron mobility transistors (HEMTs). Boasting a wider bandgap, superior electron mobility, and inherent robustness against certain radiation mechanisms, GaN is the key to unlocking next-generation space power densities. Yet, translating these raw material advantages into flight-ready, highly reliable hardware requires a deep understanding of its unique driving requirements and its interaction with rad-hard pulse width modulation (PWM) controllers.

The rad-hard landscape: Silicon vs. GaN

Space radiation hazards generally fall into two categories: Total ionizing dose (TID) and single event effects (SEE).

In silicon MOSFETs, TID causes a build-up of trapped holes in the thick gate oxide, leading to a severe negative shift in threshold voltage (Vth) and increased leakage current. On the other hand, GaN HEMTs lack a traditional gate oxide, utilizing a Schottky or p-GaN gate structure instead. Because there is no oxide to trap charges, rad-hard GaN devices exhibit exceptional inherent tolerance to TID, often surviving exposure well past 100 krad(Si) to 1 Mrad(Si) with minimal parameter shifts.

While GaN shines under TID, SEE is where the engineering nuances lie. Silicon MOSFETs are susceptible to single event burnout (SEB) and single event gate rupture (SEGR) due to heavy ion strikes creating parasitic bipolar conduction paths or destroying the gate oxide.

But GaN HEMTs don’t suffer from traditional SEB or SEGR because they are majority-carrier devices without parasitic bipolar structures. However, they are prone to single event transients (SETs) and catastrophic degradation at high drain-to-source voltages (VDS). Under heavy ion bombardment, localized high electric fields near the drain can cause high-current leakage paths. Consequently, a VDS derating of 30% to 50% of the maximum rated voltage is standard practice for spaceflight GaN applications.

Alex Lidow, CEO and co-founder of Efficient Power Conversion (EPC), notes the physical limitations of legacy materials: “Silicon has had a glorious 60-year run, but it has hit its theoretical performance wall. In space applications, where every gram of weight translates directly to launch cost, GaN isn’t just an alternative—it’s an absolute architectural necessity.”

Driving the delicate GaN gate

The primary challenge when designing a flight-ready GaN converter is managing the gate drive. Silicon MOSFETs typically feature a comfortable gate threshold of 2 V to 4 V and can tolerate gate voltages up to ±20 V. GaN HEMTs are far less forgiving:

• Low threshold voltage: GaN devices typically turn on at a mere 1.5 V to 2.0 V.
• Fragile gate rating: The absolute maximum gate-to-source voltage (VDS) is often capped at a tight -5 V to +6 V.
• Ultra-low gate charge (QG): GaN switches an order of magnitude faster than silicon. While this minimizes switching losses, it introduces severe dv/dt and di/dt sensitivities.

If the gate drive circuit experiences even minor parasitic inductance, the rapid dv/dt transition can couple back through the device’s Miller capacitance (CGD), generating a transient voltage spike on the gate. If this spike exceeds 1.5 V, it triggers a catastrophic spurious turn-on (shoot-through), potentially destroying the power stage. Conversely, if the gate driver overshoots beyond 6 V due to ringing, the gate permanently degrades.

Interfacing with heritage PWM controllers

Because dedicated rad-hard GaN-integrated drivers are still emerging, power engineers frequently pair discrete rad-hard GaN FETs with established, flight-proven rad-hard analog PWM controllers.

These heritage controllers were designed to drive the heavy, capacitive gates of silicon MOSFETs, delivering output swings from 0 V to 12 V or higher. Interfacing these high-voltage controllers with a delicate 5-V GaN gate requires a meticulously designed intermediate drive stage and layout discipline.

• Voltage clamping: Direct connection is catastrophic. Engineers must employ a high-speed level shifter or a dedicated, rad-hard gate driver buffer (for example, ISL71020M) that accepts standard PWM logic levels and provides a tightly regulated 5-V drive output.
• Asymmetric gate resistance (RG): The gate resistor network must be split into separate turn-on (Rgon) and turn-off (Rgoff) paths via a diode-resistor network. Rgon is optimized to purposefully slow down the turn-on dv/dt to suppress gate ringing. Rgoff is kept near 0 Ω to provide a low-impedance hold-down path, ensuring the gate remains firmly below the threshold voltage during rapid drain voltage transitions.
• Dead time management: GaN HEMTs lack a native body diode; so, they conduct in reverse through the channel when the gate is off. During this dead time, the reverse voltage drop (VSD) can be quite high (2 V to 3 V). If the PWM controller introduces excessive dead time, efficiency penalties from reverse conduction negate the switching advantages of GaN. Therefore, designers must utilize PWM controllers with highly precise programmable dead-time control or implement an external low-forward-drop Schottky diode in parallel.

In my years managing power electronics design, I have watched countless clean schematics fall apart under the oscilloscope simply because an engineer treated a fast wide-bandgap loop layout like a legacy 100-kHz silicon board.

When marrying a heritage 12-V PWM architecture to a 5-V gate, your layout must be an absolute work of art. Parasitic inductance can easily destroy the gate on the very first pulse if the loop area isn’t locked down.

Packaging innovation and real-world use cases

The unique performance GaN metrics are actively reshaping the size, weight, and power (SWaP) equation across various orbital profiles.

In satellite bus power, utilizing isolated GaN-based flyback or forward topologies allows engineers to push switching frequencies past 500 kHz—up from the standard 100 kHz legacy limit—directly translating to a 60% reduction in magnetics volume. In point-of-load (POL) converters, synchronous buck configurations supply core logic rails for spaceborne FPGAs and deep-space processing computers with near-zero reverse recovery losses. Furthermore, in space robotics and motor control, three-phase GaN inverter stages enable compact, motor-integrated electronics housings that bypass heavy shielded cabling.

To support these high-frequency applications, manufacturers have developed innovative, low-inductance packaging structures specifically engineered to eliminate the internal bond wires that cripple traditional high-reliability packages.

Vendor landscape and flight heritage

Navigating the space-qualified GaN marketplace requires examining components that meet the rigorous screening levels required for aerospace reliability. Below are three design case studies.

1. EPC Space

The EPC Space family of devices commands a long track record in commercial-volume rad-hard discrete GaN deployment. Its enhancement-mode (eGaN) discrete FETs (such as 60-V EPC7014) and integrated power modules have accumulated an impressive lineage, with thousands of devices actively operating in orbit since January 2019. These components are heavily utilized in LEO small-sat constellations and GEO communication platforms, powering intermediate bus converters and high-speed pulsed laser drivers for autonomous LiDAR systems.

Figure 1 EPC Space’s hermetic packaging replaces traditional wire bonds with broad, low-profile bottom contact pads to eliminate loop inductance. Source: EPC

2. Infineon Technologies

Infineon’s CoolGaN family represents the entry of traditional military-standard (MIL-PRF-19500) JANS-grade rigor into the wide-bandgap space ecosystem. Leveraging its heritage in spaceborne silicon MOSFETs, Infineon modernized GaN packaging by removing wire bonds entirely. It PowIR-SMD package delivers a 49% footprint reduction compared to legacy housings and reduces internal parasitic package inductance by 97%—dropping to a mere 0.1 nH. This nearly eliminates internal gate ringing, allowing clean interfacing with fast PWM controllers.

Figure 2 The PowIR-SMD technology minimizes internal parasitic inductance down to 0.1 nH via an advanced die-free construction. Source: Infineon

Regarding the validation of these advanced architectures, a high-reliability engineering expert at Infineon stated: “Removing internal wire bonds was the final frontier for GaN in space. By developing a die-free, surface-mount package like PowIR-SMD, we didn’t just solve thermal management—we completely neutralized the parasitic gate inductance that historically caused engineers to shy away from high-speed wide-bandgap switches in critical flight hardware.”

3. Renesas

Renesas entered the space-qualified GaN arena by executing a brilliant ecosystem play: combining its decades-long legacy of rad-hard analog power management with high-reliability GaN FETs like ISL73024SEH. These devices are frequently designed alongside dedicated multi-phase synchronous PWM controllers—such as the ISL73847SEH—to form the fundamental backbone of spaceborne core power bricks.

Figure 3 The Renesas/Intersil radiation-hardened GaN family is engineered in rugged, space-qualified ceramic flatpacks optimized for severe thermal environments. Source: Renesas

Achieving mission success

While designing deep space profiles, we must ruthlessly enforce gate-clamping rules. Designing radiation-hardened GaN converters for space applications is ultimately an exercise in managing extremes. GaN offers game-changing thermal and volumetric efficiencies, but its unforgiving gate drive margins and extreme switching speeds mandate a departure from legacy silicon layout rules.

The accumulated flight data from the GaN industry pioneers has rewritten the rulebook for space power systems, dispelling early engineering anxiety through years of anomaly-free orbital operation. When carefully controlled by a robust, rad-hard PWM controller, these devices provide a mature, predictable, and remarkably rugged path toward achieving unparalleled power density in the cosmos.

Bharrat Mehta, a senior space scientist, is former deputy project director of Indian Space Research Organization (ISRO).

 

 

Related Content

• GaN Transistor for Space Missions
• Infineon unveils rad-hard GaN transistors
• Deep Space Challenges Rad-Hard IC Development
• Test and Measurement Priorities for GaN-Based Power Electronics
• GaN in Space: Unlocking Efficiency and Performance in Satellite Systems

The post Rad-hard GaN converters: Design insights for space hardware appeared first on EDN.

Here is a look at my daily workshop setup for diagnosing, micro-soldering, and refurbishing batches of returned gaming gear and electronics. ​My main focus is on component-level fixes: replacing double-clicking microswitches, faulty wheel encoders, damaged PCB traces, connectors, and power components. Working with larger volumes requires keeping the workbench organized for fast diagnosis, desoldering, and full functional testing before reassembly. ​Always open to discussing repair techniques, equipment preferences, or diagnostic approaches for small electronics! submitted by /u/Accurate_Specific339 [link] [comments]

For first-half 2026, molecular beam epitaxy (MBE) system maker Riber S.A. of Bezons, France has reported revenue of €12.8m, up 19% on €10.7m in first-half 2025...

The RTC 27 Click board from Mikroe provides ultra-low-power timekeeping with alarm, watchdog, and timestamp functions. Based on the mikroBUS add-on board socket standard, it integrates the NXP PCF8525 nano-power CMOS real-time clock and calendar chip with an I2C interface. The board is the 2000th member of the Click family, enabling developers to quickly build proof-of-concept designs, prototypes, and embedded applications.

Using the PCF8525’s default temperature compensation engine and integrated temperature sensor, the RTC 27 Click corrects crystal frequency drift, achieving typical ±30-ppm accuracy across temperature and up to 5× better timekeeping than an uncompensated RTC design. It provides time and calendar information, including year, month, day, weekday, hour, minute, second, and 1/100 second.

The RTC 27 Click operates with 3.3-V and 5-V logic voltage levels, while the PCF8525 consumes a typical 64 nA in timekeeping mode with a 3.3-V supply. This makes the board well suited for battery-powered and always-on designs, including portable instruments, wearables, industrial systems, and IoT applications.

The RTC 27 Click is available from Mikroe and its distributors with single-unit pricing of $19.

RTC 27 Click product page 

Mikroe

The post Low-power RTC simplifies embedded timekeeping appeared first on EDN.

Voyager Wingman from Axelera AI is an AI-powered assistant that works with the Voyager Toolkit to accelerate AI application development. It enables developers to interact with the Voyager SDK and Axelera’s documentation using natural language to build, debug, and optimize AI inference pipelines. In internal testing, Wingman achieved 20% to 30% higher accuracy than general-purpose AI coding tools such as Claude Code.

Developing AI applications for dedicated hardware involves tasks such as model export and compilation, pipeline configuration, performance tuning, analytics, and output visualization. To streamline these workflows, Voyager Wingman focuses on four key areas:

• Application development. Natural language generation of computer vision pipelines, including AI models, pre-processing and post-processing steps, and multi-stage pipelines.
• Performance optimization. Recommendations for compiler settings and other optimizations to improve application performance on Axelera hardware.
• Debugging. Assistance with identifying and resolving configuration errors, device detection problems, and model compilation failures.
• Documentation assistance. Natural language access to information on supported operators, APIs, runtime behavior, and configuration syntax.

Voyager Wingman is available through the Axelera Developer Community and Customer Portal. The web-based chat service includes a free credit allowance for developers, while the standalone application is free with the developer’s own LLM API key. For more information, visit the Voyager SDK and Wingman page.

Axelera AI

The post AI assistant optimizes inference pipelines appeared first on EDN.

Rapidus and Cadence are collaborating to advance agentic AI for advanced SoC design and accelerate design turnaround time. The effort integrates the Cadence InnoStack AI Super Agent with the Rapidus AI-Agentic Design Solution (Raads), combining Cadence’s agentic AI orchestration technology with Rapidus’ AI-native design and manufacturing ecosystem for advanced-node semiconductors. According to Rapidus, the approach targets up to a 2× reduction in design turnaround time over conventional design flows.

Rapidus is extending its Raads AI-agentic design environment with the introduction of Raads Navigator and Raads Indicator to enhance quality assurance and help designers resolve design issues. Integrated with the InnoStack AI Super Agent, the new capabilities enable agentic design orchestration across key SoC workflows, automating and coordinating tasks from early architectural exploration through implementation and signoff. The integration allows teams to better manage advanced-node complexity and improve design predictability.

The InnoStack AI Super Agent is available from Cadence. Raads is part of Rapidus’ AI-native foundry ecosystem for customers developing advanced-node semiconductor designs.

Cadence

Rapidus

The post Rapidus, Cadence partner on agentic SoC AI appeared first on EDN.

Melexis has expanded its MLX90412 family of single-coil fan drivers with a device that provides smoother motor control for higher-power fans. Optimized for the cooling requirements of data center infrastructure, AI workstation GPUs, industrial power supplies, and home appliances, the MLX90412-D features code-free configuration via integrated I²C-programmable memory.

With a peak drive current of 2.2 A, the device supports fan designs up to approximately 18 W at 12 V and 35 W at 24 V. Its improved motor-control algorithm enables smooth start/stop operation, reduces acoustic noise, and extends fan lifetime. Revised proportional-integral (PI) regulation ensures stable operation even at very low speeds, while multiple start/stop profiles accommodate different application requirements.

By integrating a Hall sensor, motor controller, and driver in a single IC, the MLX90412-D provides an alternative to MCU-based discrete fan and pump control implementations. Configurable parameters include start-up profiles, speed curves, and FG/RD signal output options, allowing designers to fine-tune fan operation without firmware development.

Samples of the MLX90412-D in a 3.3-mm DFN10 package are available now.

MLX90412 product page

Melexis

The post Fan driver delivers smooth motor control appeared first on EDN.

Version 3.0 of Microchip’s VectorBlox Accelerator SDK simplifies FPGA-based AI implementation by supporting sparse neural networks. Available free of charge, the VectorBlox SDK and associated CoreVectorBlox IP form an integrated toolchain that streamlines the optimization, compilation, and deployment of convolutional neural network (CNN) models on PolarFire FPGA and SoC platforms.

Designed to scale across different model sizes and multiple AI workloads, VectorBlox enables customers to consolidate vision and sensor AI functions on a single low-power FPGA. Sparsity-based model compression reduces compute and memory requirements by skipping zero-valued operations, improving inference performance while lowering power consumption.

VectorBlox SDK 3.0 integrates with Microchip’s Libero SoC Design Suite and provides broad AI model support for TensorFlow, TensorFlow Lite, ONNX, and OpenVINO.

VectorBlox SDK product page 

Microchip Technology 

The post FPGA SDK enables sparse AI models appeared first on EDN.

КПІ посилює антикорупційну роботу під час вступної кампанії 2026 kpi ср, 07/22/2026 - 16:40

submitted by /u/t_Lancer [link] [comments]

Молоді науковиці КПІ завершили міжнародну літню інженерну програму у Франції KPI4U-1 ср, 07/22/2026 - 15:01

Convert a 4-20 mA signal to 0-20mA and deliver it to a grounded load with no additional power supply needed.

Recently, EDN kindly published a design of mine for a micropower 4-20 to 0-20mA current loop converter. Shortly thereafter, in the grand tradition of the Design Idea circuit collaboration kitchen, also-frequent contributor Jayapal Ramalingam made a (challenging!) suggestion. He commented that the design might be more useful if, instead of needing an (albeit very small) local power supply, it was revised so as to need no local supply at all.  It was a good point.

Wow the engineering world with your unique design: Design Ideas Submission Guide

The challenging part, of course, was that this meant the converter would have to run solely from power stolen (more or less invisibly, hence “phantom”) from the same 4-20mA signal it was working to convert.  Sneaky.  And tricky. I puzzled over JR’s intriguing suggestion until (eventually) a possible solution emerged from my muddled mental mist.  Figure 1 shows the outcome of my foggy fancy: a “phantom power” converter:

Figure 1 In this circuit, the 4-20mA input current is converted to a 0-20mA output while relying solely and exclusively on the input current for (phantom) power. Power-theft-related error is minimized by recycling the same 100µA that runs the opamps to also bias precision voltage reference Z2.  Asterisk’d resistors are 0.5% or better.

Here’s how it works. Comparisons of Figure 1 to the circuit in the earlier design:

reveal many obvious similarities, but a critical difference (other than no power supply in the “current” case) is how the precision shunt voltage reference is biased.  In the prior circuit, since it runs from a constant local supply voltage, a simple resistor sufficed.  But here, if we assume a 34v range of acceptable loop supply, the 80µA required by the TLV431 at 6v could become 900µA at 40v, creating a cringe-worthy (and likely unacceptable) ~5% conversion error.  Yikes!

Current recycling, however, improves accuracy of the conversion function to Iout = 1.249(Iin – 4mA)  = 0 to 19.9mA as Iin = 7 to 20mA.  The malingering 0.5% of full-scale error is the penalty paid for phantom power.  After all, active devices, by definition, must be fed.  And while 0.5% accuracy isn’t quite phantasmagorical, maybe it’ll do.

Other picky phantom phacts include the IR LED wired in series with Q2’s emitter.  It’s not there to make light, which we couldn’t see anyway, but rather to use its 1v minimum forward voltage to help accommodate A2’s ~200mV minimum output that sits atop Z2’s 1.24v.  Likewise dictated by opamp limitations is the boost of R1 to 249 ohms and its minimum sensed voltage to 1v. This accommodates the 2244’s common mode topping out at 900mv below the positive rail.

In conclusion, thanks JR!

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

Related Content

• 4mA-20mA to 0mA-20mA converter’s current mirror drives grounded load
• Triple-duty current loop calibrator
• Double-duty current loop transmitter
• Full circle current loops: 4mA-20mA to 0mA-20mA

The post Current converter performs purely on paltry phantom power appeared first on EDN.

A cautionary tale in two photos: beeper removal and GF problems I have an AC that's triggered with an IR remote. Each time you do an action: it beeps. I also automated the AC with an IR transmitter and an ESP32. I wanted the AC to turn off at temp, and turn back on when it's over temp. But that would mean beeps at 3AM?? I hate that so I used pliers to rip it off. No more beep, yay! This wasn't an issue until my girlfriend turned on the AC with the remote. She complained that there was no feedback for the button presses. (Ok, she actually said, "I don't like that it doesn't beep!" which is complaining about no feedback.) So I, intrepid hardware modder that I am (I just search a bunch,) I decided to have an artificial beep from speakers (They still aren't installed). So I took apart the split AC again, and soldered to the leads of the buzzer I ripped off. That goes though various resistors and a optocoupler until it gets to an ESP32. That reports a beep was done. Optocoupler was stolen from an old cheap USB power supply. (THIS is why you should horde old PSU's and other PCBs) Except... no voltage from the beeper. Or, really, I was getting a ton of it. Or none? It's been a while, but I was on a goose chase because of the two leads off of the buzzer remains. (Also using the wrong AC ground rather than the DC ground) I hunted around, trying to find what controlled the buzzer, thinking I found it i ripped off the component... that provides 5V to the board. (You can see it re-soldered on there, second photo.) Good news: I DID find the pad that controlled the buzzer. It's on the micro controller that's above the buzzer there. Bad news: too small to solder to when I'm standing on a desk reaching up to the split AC's mainboard that's still screwed in. After an hour I finally realized: The buzzer must be the problem, I pull off the plastic remains... and one of the leads was disconnected from the board from when I snapped it off with pliers. I was trying to trace the leads to find the mosfet that controlled it, and learned some more things about PCBs... but I could have just soldered directly to the pads of the PCB. So, now I have a place in Home Assistant for when I finally DO install the speaker in the room, there will be a chime when my GF turns on the AC manually, and no chime when the AC turns off/on automatically via the IR ESP32. Except it's redundant because none of the code has found a use for the beep function (It just caused more problems,) I'm going to move the IR transmitter to this ESP32 installed inside the AC itself, so I won't need confirmation... and the next project is a custom AC controller for the GF that will make this extra redundant. (I can have a chime still... but it would directly trigger from her pressing the buttons, not from the AC itself.) Also I made this post because someone else asked a question showing off their fail and deleted their post, and I wanted them to know they aren't alone with their hate of beepers and doing dumb things to boards. (Ok but stabbing the beeper with a soldering iron is a step too far! Use pliers like a civilized man.) submitted by /u/EmailLinkLost [link] [comments]

it's open source at https://github.com/darshg321/bench i have a ton of hardware laying around, and didn't want to just use a spreadsheet to organize it so i used this! it has a bunch of hardware pre-catalogued so you can simply use the dropdown, and use ai to get images from web pages or find the specs. hope this is useful! submitted by /u/paulsimpngl [link] [comments]

Bosch is expanding its portfolio for diesel components with the new DCP 800 test bench. The abbreviation DCP stands for Diagnostic Common-Rail Pump and refers to a test bench specially developed for common-rail high-pressure pumps. The system helps workshops meet the increasing demands for efficiency, precision, and economy in diesel service.

High-performance technology for precise test results

The DCP 800 enables the testing of common-rail pumps for passenger cars, commercial vehicles, and off-road applications at pressures of up to 2,700 bar. A powerful 25-kW electric motor is directly connected to the drive mechanism and operates without intermediate systems. This drive concept supports precise and reliable testing, particularly for commercial and heavy-duty vehicle applications. Automated inlet and counter-pressure regulation, as well as electronic flow measurement, further contribute to measurement accuracy.

Efficient workflows in the workshop

A key advantage for workshops is the high efficiency of the test sequences. With test times of around 20 minutes – regardless of the application – service processes can be significantly accelerated. At the same time, a quick setup process combined with predefined, standardized test plans ensures simple and repeatable test execution. Optimized filtration, cooling, and measurement systems support automated maintenance intervals and help reduce operating costs.

The test bench covers a broad spectrum of Bosch common-rail pumps, including the CP1 to CPN6 series. Furthermore, it is compatible with existing generations of Bosch test kits such as CP1, CP3, and CBX8 from EPS 815/708 systems. This allows workshops a gradual and economical transition to the new testing technology.

Flexible integration into different workshop environments

A newly developed drive coupling system, which enables the quick mounting of different pump types, provides additional flexibility in the workshop. An adapter solution ensures that older coupling designs can continue to be used. The ergonomic machine concept with three-sided access supports comfortable and safe operation.

The operating computer with a screen for controlling and monitoring the test sequences can be positioned on either side of the test bench, depending on workshop requirements. This allows the DCP 800 to be easily adapted to different workshop specifications. Workshops benefit from optimized workflows, ergonomic operation, and seamless integration into their existing workspace.

The DCP 800 complements the existing Bosch test benches for common-rail injectors and enables workshops to perform comprehensive testing of pumps and injectors from a single source. The new test bench will make its debut at Automechanika Frankfurt from September 8 to 12, where it will be showcased live for the first time.

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For the past decade, the artificial intelligence landscape followed a remarkably simple recipe: if you wanted better AI, you built larger models, fed them more data, and added more GPUs. The formula worked, and it worked spectacularly.

Every new generation of hardware enabled larger neural networks, and larger neural networks broadened their reach. What began as image recognition evolved into agents capable of writing essays, generating software code, and creating realistic images and videos. The world grew accustomed to a simple equation: more GPUs meant more intelligence.

However, in the past couple of years, something changed. As we enter the fourth generation of AI—enterprise AI—the industry is discovering that the old recipe is no longer sufficient. The problem is not that GPUs have become obsolete. Far from it: GPUs will remain indispensable for training the giant, diverse models that underpin modern AI.

The problem is that enterprise AI asks these machines to solve a fundamentally different problem, and the assumptions that drove the generative AI revolution are starting to break down.

Enterprise AI operates by a different set of rules

Most people still think of AI as a chatbot: ask a question, receive an answer, end of interaction. That model defined the generative AI era. Enterprise AI, however, plays by different rules.

Imagine an AI assistant embedded inside a company. It starts the day by reading emails, analyzing spreadsheets, interpreting charts, reviewing contracts, listening to conference calls, and consulting internal databases. It collaborates with other AI agents, prepares reports for employees, and continuously updates its understanding as new information arrives. This is no longer a sequence of isolated interactions; it is continuous reasoning.

AI never truly stops working. It shifts constantly between tasks, maintains context over long stretches of time, and makes thousands of small decisions throughout the day. That may sound like a subtle difference.

But from a computing perspective, it changes everything.

Why GPU architectures struggle with enterprise AI inference

For years, AI systems were optimized for one metric: floating-point operational throughput, or FLOPS. The goal was straightforward: maximize the computation performed every second. GPUs excel at this because they were originally designed to process thousands of identical operations simultaneously.

Rendering video game graphics demanded enormous parallelism, and that same parallelism proved extraordinarily effective for training neural networks. Training, after all, is a highly parallel problem: huge volumes of data can be processed at once, and GPUs thrive under these conditions.

Inference is a different story. Inference is the stage where AI produces answers for users in real time. Unlike training, every new token generated by a large language model depends on the token that came before it. There is no shortcut around this sequential dependency. No matter how many GPUs are thrown at the problem, the system still generates one token at a time.

This is where a new bottleneck emerges. For decades, engineers focused on increasing computational performance while memory performance advanced at a far slower pace. Processors became extraordinarily fast; memory did not keep up. This imbalance is known as the memory wall.

Today, the memory wall stands as one of AI’s most stubborn obstacles. Large language models contain hundreds of billions of parameters, and some already contain trillions. Those parameters cannot fit inside a processor. Every time the model generates a response, it must continuously retrieve information from memory. Increasingly, AI systems spend more time moving data than performing calculations. In fact, in many deployments, far more energy is consumed transporting information than computing the answer.

This reality exposes a fundamental weakness of the GPU-centric approach. GPUs were built to maximize parallel computation; they were never designed to minimize data movement. During the generative AI era, the limitation could be partially hidden by batching many user requests together. Large batch sizes kept GPUs busy and delivered impressive throughput numbers.

Enterprise AI changes the economics

An AI assistant participating in a meeting cannot wait for hundreds of requests to accumulate before responding. A medical system helping a physician interpret an image cannot afford noticeable delays. An AI agent coordinating supply chains or financial operations cannot pause while batches form. Enterprise AI demands immediate responses. Latency becomes far more important than throughput.

Here lies the trap for GPU-based inference: to meet the latency constraints of the application, the GPU is forced to operate with small batches, and small batches impact the very utilization that made the GPU economical in the first place. The architecture is not broken; it’s simply being asked to run against its own design assumptions, and its performance degrades significantly as a result.

This shift is forcing the industry to ask a different question. Instead of asking how many operations a processor can execute per second, engineers are increasingly asking how quickly information can move through the system. It may sound like a small distinction. It is, in fact, a critical architectural change.

For years, AI hardware was designed around compute: the processor sat at the center of the system, and memory existed primarily to feed it. That philosophy is beginning to reverse. Fast memory access is becoming the center of architecture.

The goal is no longer to build faster arithmetic units. It is to increase data bandwidth and shrink the distance information must travel. Every millimeter matters because every movement consumes energy, introduces latency, and limits scalability.

The memory-centric revolution: From adding FLOPS to moving bytes faster

This realization is driving a remarkable wave of innovation across the semiconductor industry. Some companies are building processors with enormous amounts of on-chip memory to keep data local. Others are developing specialized inference engines optimized for autoregressive token generation.

New architectures activate only the portions of a model required for a given task, avoiding unnecessary computation altogether. At the same time, researchers are exploring near-memory and in-memory computing, two approaches that bring computation physically closer to where the data resides.

Among the many pioneers proposing new architectures, a few stand out. Cerebras has demonstrated that placing an entire processor on a single silicon wafer can dramatically reduce latency and communication bottlenecks. Groq has focused on highly deterministic, low-latency inference rather than peak throughput.

d-Matrix attacks the memory problem directly by bringing memory and computation closer together. SambaNova is exploring reconfigurable dataflow architectures, while Etched has aggressively specialized its hardware for transformer models.

Beyond GPUs: Rewriting the rules of AI inference

Another example is a next-generation inference architecture. It rests on three interconnected and mutually reinforcing innovations: a memory-centric design philosophy; a high-bandwidth, low-latency, deterministic pipelined data flow; and a hybrid compute fabric that fuses large arrays of tensor cores with on-the-fly reprogrammable DSP cores. Together, they address the fundamental bottlenecks that have long constrained the performance, efficiency, and scalability of AI inference hardware.

The first innovation, the memory-centric approach, marks a fundamental departure from conventional inference architectures. Traditional systems lean heavily on multi-level KV (key-value) caches shuttled through external memory, introducing latency and energy overhead each time the compute engines retrieve or update cached values.

The KV cache is not eliminated. Instead, its economics is transformed. Massive arrays of local registers, positioned in extreme physical proximity to their corresponding compute engines, allow the architecture to hold far larger contexts and model parameter sets close to the compute fabric, making every KV cache access dramatically more efficient.

This reduction in data travel distance cuts memory access latency, relieves pressure on the memory bus, and yields gains in power efficiency. The result is an architecture that sustains higher throughput while consuming less energy, an advantage in large-scale deployments where energy costs and thermal management dominate operational concerns.

The second innovation, the high-bandwidth, low-latency pipelined data flow, addresses the inefficiencies inherent in the single instruction, multiple threads (SIMT) execution model that dominates GPU-based inference today. SIMT architectures impose a heavy memory tax: threads must frequently synchronize and stall while waiting for memory operations to complete, burning both time and power.

By replacing SIMT with a deeply pipelined data flow, the chip ensures that data moves continuously and predictably through the compute stages, eliminating synchronization stalls and sharply reducing the latency and power penalties of traditional GPU memory access patterns. The pipelined approach also delivers deterministic, real-time inference performance, an increasingly important requirement as AI systems move into latency-sensitive applications such as enterprise AI, autonomous driving, robotics, and real-time speech.

The third innovation, the hybrid tensor core and DSP compute fabric, adds a new dimension of computational power and flexibility. Tensor cores are highly optimized for the dense matrix and vector operations that dominate transformer inference, but many workloads also require specialized signal processing, custom activation functions, and non-standard numerical transformations that tensor cores handle poorly.

By augmenting the tensor core arrays with reconfigurable DSP cores, reprogrammable on the fly and driven by a rich instruction set in which every instruction executes in a single clock cycle, the hardware can adapt dynamically to the computational demands of each model and each inference task.

This versatility carries weight for agentic AI. Pre- and post-processing tasks that would normally fall to the host CPU can be executed locally on the accelerator, minimizing CPU-accelerator traffic and freeing host compute capacity for other work. It also future-proofs the architecture against a model landscape that refuses to stand still.

Taken together, these three innovations from VSORA offer a purpose-built solution for modern, scalable AI inference in data centers and at the edge. The result is greater efficiency, lower latency, and broader adaptability than conventional GPU-centric approaches that translates into a lower cost structure and higher ROI for cloud service providers.

On the verge of next architectural transition

Computing history teaches that architectural transitions occur whenever a dominant technology encounters the limits of its original design assumptions. For decades, CPUs were the universal solution until graphics workloads grew so demanding that GPUs emerged as a new specialized architecture. Today, GPUs face a similar moment. They are not being replaced; they are being complemented.

The winners of the next AI race will not necessarily be the companies that build the largest clusters of GPUs. They will be the companies that build systems capable of the smartest data access and management, consuming less energy, responding faster, and reasoning more efficiently.

Lauro Rizzatti is a business development executive with VSORA, a technology company offering silicon semiconductor solutions that aim to redefine silicon performance. He is a noted chip design verification consultant and industry expert on hardware emulation.

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Singapore-based fabless silicon photonics company SILITH Technology has announced the first mass-production wafer delivery of photonic ICs from the Singapore fab of foundry United Microelectronics Corp (UMC) of Hsinchu, Taiwan, advancing the partnership between the two companies to scale next-generation silicon photonics manufacturing...

Behold: My first major project that isn't just big electric components or basic relay logic. This is a WiFi servo controller that I'm building to control a homemade automatic power transfer switch for our home's backup generator. Two large main servos are powered by the large buck converter module, and a third auxiliary servo is run off of a 3.3V regulator. A second regulator powers the ESP-01S WiFi control module to avoid voltage fluctuations when the small servo is powered. The ESP-01S handles the signals for controlling the servos, and is connected to my Home Assistant home automation system via Tasmota. It's DEFINITELY not pretty, and I still have a lot to learn about soldering, but it DOES work. ...For about 3 seconds until it sent the full 12V supply voltage into one of the servos and destroyed it... I'm guessing the 3.3v regulator I used to power the small auxiliary servo just isn't up to the job. That means this whole thing has to go back to the drawing board. :( submitted by /u/Cheetawolf [link] [comments]

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