Feed aggregator

 The DSA504RT delivers high-performance timing and integration at a cost-efficient price point

Spacecraft timing systems must provide highly stable, precise signals for navigation, communications, and scientific instruments, even when GNSS signals are weak or unavailable. Designers often rely on multiple oscillators and buffers to supply precise frequencies to various subsystems, adding size, mass, and complexity. Microchip Technology announces the space-grade DSA504RT, a radiation-tolerant, six-output programmable clock generator for addressing the complex timing needs of aerospace and defense applications. 

The DSA504RT streamlines timing architecture by generating multiple clean, phase-aligned frequencies from a single master source. Additionally, this solution reduces the need for multiple discrete oscillators, lowers overall component count, and improves system failure in time (FIT) rate. It also reduces power consumption and mass, as well as simplifies distribution networks to keep all subsystems synchronized even in the harshest environments and during GNSS outages or disruptions.

Analog Phase-Locked Loop (APLL) features spread spectrum capability, two fractional and two integer dividers, and six highly configurable output buffers, each of which can be configured as a differential driver (LVPECL, LVDS, or HCSL) or as a pair of single-ended CMOS outputs. The DSA504RT delivers ultra-low jitter performance as low as  200 femtoseconds (12kHz–20MHz) and is compliant with PCIe Gen 1-7 standards. This level of integration allows engineers to replace multiple crystals, oscillators, and buffers with a single device, improving design reliability, reducing Bill of Materials cost, and design complexity.

“This Microchip clock generation device is a game-changer for space applications. It can offer a comprehensive clock tree solution, producing three different clock families and up to six different frequencies, each buffered on a variety of selectable output drive types,” said Maamoun Abou Seido, appointed vice president of Microchip’s timing communications group. “Replacing numerous oscillators, buffers, and synthesizers, the DSA504RT saves board space and reduces part count to improve the system’s Failures in Time (FIT) rate in these high-reliability applications.”

The DSA504RT, offered in QFN28 and CQFP32 packages, serves as a companion device for complex aerospace and defense systems. It enables high integration of clock architectures within a single chip, distributing precise timing references to subsystems built around radiation-tolerant or radiation-hardened FPGAs and MCUs.

The post Spacecraft Timing Architecture: Microchip’s Radiation-Tolerant, Low-Power, Low-Jitter Six-Output Clock Generator appeared first on ELE Times.

VL53L9 is the first direct Time-of-Flight (dToF) 3D LiDAR all-in-one module in ST’s portfolio, offering a resolution of 2.3K zones, a wide field of view, on-chip processing, 100 frames per second, and a sensing range from 5 centimeters to 9 meters. It meets the evolving needs of customers and partners across diverse industries, including robotics, industrial automation, smart buildings, AR/VR, and healthcare.

The global semiconductor leader serving customers across the spectrum of electronic applications announces the launch of the VL53L9, a compact direct Time-of-Flight 3D LiDAR all-in-one module that sets a new benchmark in high-resolution sensing. The VL53L9 combines state-of-the-art features in a compact and cost-effective package, delivering AI-ready output data for low-compute edge AI systems on small microcontrollers (MCUs) and high-performance sensing across a wide range of applications across robotics, industrial automation, smart buildings, AR/VR, and healthcare.

“VL53L9 demonstrates how far Time-of-Flight sensing has evolved, combining high-resolution depth data, up to 100 frames per second, and a fully integrated architecture in a single compact module. By simplifying integration and reducing system complexity, we enable customers to accelerate the development of applications such as robotics, smart infrastructure, and healthcare monitoring,” said Alexandre Balmefrezol, Executive Vice President and General Manager of the Imaging Sub-Group at STMicroelectronics. “This launch reflects our strategy to move beyond standalone sensors and deliver integrated sensing systems that support real-world edge AI.”

“3D sensing demand accelerates across robotics, industrial automation, XR, and intelligent consumer devices. Time-of-Flight technology is expanding beyond smartphones into applications requiring compact, affordable, and precise depth perception, from navigation and people monitoring to gesture recognition and safety. Higher resolution multizone dToF modules are now emerging as key enablers for this next wave of 3D sensing adoption(1),” said Anas Chalak, Market & Technology Analyst at Yole Group.

 

ST FlightSense VL53L9 is designed for multiple industry use cases:

• Robotics: enhances small-object detection, SLAM (Simultaneous Localization and Mapping), and obstacle avoidance for autonomous navigation.
• Industrial automation: accurate volume measurement in tanks and bins, improving operational efficiency and inventory management.
• Smart buildings and homes: reliable human presence detection and people counting while preserving user privacy.
• AR/VR and consumer electronics: advanced gesture recognition, body tracking, and finger skeleton for immersive user experiences.
• Healthcare: fall detection and monitoring solutions for eldercare and patient safety.

Technical Information

Enhancing 3D sensing with precision and efficiency

The VL53L9 offers the 2,268 resolution zones (54×42) with a wide 54°x42° field of view, enabling detailed 3D depth mapping and precise detection of small objects, contours, and edges. Leveraging ST’s proprietary stacked BSI SPAD sensor technology and innovative metasurface optical elements (MOE), the module delivers fast and accurate ranging from less than 5 cm up to 9 meters with up to 1% accuracy and a frame rate of 100 frames per second.

All-in-one sensing data for edge AI and easy integration

The VL53L9’s dual-scan flood illumination replaces traditional dot scanning, reducing motion artifacts, eliminating dead zones, improving small-object detection, and capturing complementary 2D infrared and 3D depth images. In contrast to competition, this greatly simplifies post-processing and enables a broad range of edge AI use cases to run efficiently on small MCUs with low compute requirements. The all-in-one module further integrates on-chip dToF processing, a dedicated power management IC, and is fully calibration-free, simplifying integration and reducing system cost and complexity.

Compact form factor

Measuring just 12.8 mm x 6.1 mm x 4.6 mm, the VL53L9 is a reflowable, single-component module compatible with a wide range of cover glass materials. It supports dual-power-supply operation (1.2 V and 3.3 V) and outputs data via MIPI or I3C interfaces, ensuring compatibility with diverse CPU architectures. The module is certified as Class 1 laser safe, providing reliable and secure operation for end users.

For more information, visit the VL53L9 product page: https://www.st.com/vl53l9cx

The post STMicroelectronics Unveils New Compact Time-of-Flight 3D LiDAR Module for Compact Edge AI Systems appeared first on ELE Times.

I wanted a "real" quantum random number generator, something where every bit is an actual physical quantum event. First attempt was a 1970s Canon FD 55mm f1.2 with a thoriated rear element. It's pretty radioactive (the Geiger counter make scary noises). But radioactive decay gives you when an atom popped, which is timing-random, not the which-path coin flip I was after. The build that actually worked is optical: attenuate a light source down to single photons, fire them at a 50:50 UV beam splitter, and read which way each photon went with two detectors. Through → bit 0. Bounce → bit 1. The detectors are two Hamamatsu PMT modules a friend gave me, pulled out of a dead lab instrument. I tore it down, yanked the dichroic mirror, and dropped in a UV 50:50 splitter. For a fluorescent source I ended up using 3D-printer filament — it's faintly fluorescent at the right wavelength and doubles as a light-tight cover. All the detection and conditioning runs on a Red Pitaya (FPGA + fast ADCs): Op-amp + transistor LED current sink, reed-relay LED gate, PMT gain via dividers, all driven by the Red Pitaya's slow DACs so I could sweep everything in software instead of hand-twiddling pots. VHDL threshold + edge detection on the 14-bit ADC, a coincidence veto (kills double-fires / cosmic rays), and a symmetric "global blank" after every event — that last one matters, because per-channel dead time secretly biases the stream. A timestamped debug FIFO that was a chunk of fabric to build but caught a bunch of detector-memory artifacts I'd otherwise have shipped. The hard part genuinely wasn't generating random-looking bits, but it was proving they were real random bits from the optical system and not other noise sources. Most of the project ended up being diagnostics... Payoff demo is a Quantum Magic 8-Ball: hit a button, it pulls fresh quantum bits and gives you one answer (and, if you're an Everettian, every other answer somewhere in the multiverse). Full build log with schematics, scope shots, and the FPGA stuff: https://dnhkng.github.io/posts/building-the-beam-universe-splitter/ Happy to answer questions on the analog front end or the FPGA fabric — the analog side is honestly my weakest area, so I'd welcome the critique. TL;DR, and just want to play with the Quantum Magic 8-Ball? -> https://quantumlever.stream/oracle submitted by /u/Reddactor [link] [comments]

Від ідеї до дії: енергоефективність по-данськи Інформація КП чт, 06/25/2026 - 15:50

Hello r/electronics, In this post, I want to share my project that I’ve been working on in the past few months. It’s a custom-built lab bench power supply. Such a project is common in the DIY community, so what makes this one different? The custom-designed SMPS board that I engineered from scratch isn’t your typical “let’s put this power supply module into a case” approach. So let’s dive into the working principles, design decisions, and in-depth test results. The Forwarder 1kW is the SMPS board that I designed and used in this project. It’s based on a hard-switch, half bridge topology. The full features of this power supply are as follow: 1000W maximum continuous output capacity. Configurable from 50V/20A up to 400V/2.5A. CC/CV mode with mode signal and indicator. Tuneable operating frequency and dead-time. Dedicated power stage enable pin. Analog reference interface for output voltage/current control. Analog signal output interface for monitoring voltage/current. Dedicated fan port with optional automatic power-on. Simple construction, less than 130 components on board. Easy to build with mostly THT components. Curated component selection for high accessibility. The working principle of this design is about as simple as it can get for a switched-mode power supply. I talked about the working principle of my design over on r/AskElectronics, so I’m not going to repeat it here. Most of the concepts stay the same, just with some design adjustments and the numbers changed. https://www.reddit.com/r/AskElectronics/comments/1s8ll9g/ Now, I want to go in detail about the design decisions that led into this design that you may find interesting. The lack of active PFC (Power Factor Correction) was determined after I reviewed many existing designs and products in the same power level and after noticing many of them get away without one, I decided to omit this feature. For my first SMPS design, I want to focus solely on the DC to DC conversion power stage. For my next iteration, I’m more likely to resort to a simple boost PFC to achieve tighter regulation. Double-ended hard-switch topology (half-bridge in particular) was chosen due to its suitability and simplicity in this application. Flyback is out of the question due to power requirement, single-ended topologies have poorer core utilisation and the high favour for current mode control, and resonant topologies don’t seem like a good choice for my first SMPS design (duh). An SG3525 with LM324 was chosen to generate the PWM signal and achieve regulation. SG3525 is quite popular for double-ended converters with plenty of documentation online, while the LM324 provides CC+CV regulation with two of its op-amps (because SG3525 only features one error amplifier). This effectively forms a setup based on voltage mode control. Voltage mode control was inherently chosen as the result of using SG3525 and it was favoured due to its “arguably” simpler implementation over current mode control. However, I find the better regulation and inherent cycle-by-cycle overcurrent protection offered in current mode control very enticing. I probably would resort to this approach for my next iteration. My galvanic isolation strategy was to have the entire control circuit on the secondary side and have the PWM signal driven to the primary through a gate drive transformer. This way, I can have simpler and more precise control over the voltage and current regulation without the nonlinearity issues of using optocouplers. ETD49 cores were used for both transformer and output inductor. I like the round bobbin that makes winding easier, and the calculations prove it’s suitable for power of 1kW at 64kHz. The gapped version was used for the output inductor because the high inductance requirement requires high turn number, and that gets complicated real quick with toroidal cores. After I finished the board, I wanted to know how my design performs in real-life. So, I conducted a few tests that are relevant for a power supply. The testing rig was pretty simple: A power meter at the input and four DS18B20 were used to track the energy consumption and component thermal profile over time. An electrolysis tank with electrodes that can be spaced accordingly was used to simulate multiple load profiles at power up to 1kW. A third positive electrode connected through a toggle switch was used to abruptly step the load in the dynamic tests. Hantek DSO2D10 was used to capture the waveforms in various tests. The test conducted, along with their results are as follow: The stress test was conducted for one hour and each component temperatures peaked at the following temperatures: half-bridge N-MOS 75°C / 167°F, main transformer 55°C / 131°F, output rectifier 69°C / 156°F, output inductor 44°C / 111°F. The efficiency characterisation was conducted at 50V and 1, 2, 5, 10, and 20 amps. 89% efficiency was achieved at 5A load or more. Maximum recorded efficiency was 90.3% at 50V 10A load, and efficiency at maximum load was 89.1%. The output ripple test was done with direct on-trace probing with a ground spring, 20M BW limit, 1x probe, and no added capacitor. No load ripple showed at 40mVpp, 1A load at 34mVpp, and maxes out at 94mVpp at full load. The turn-on curve tests showed that under loaded condition, it’s bound to the SG3525 soft start function and takes a second to reach the full 50V. At no load and lower setpoints, the voltage overshoots by a few volts. The load step tests showed about 3% voltage deviation going from no load to 10A and vice-versa. Going from 5A to 10A and vice-versa showed no sign of voltage deviation. CV to CC transition took 3ms to begin responding and a full 7ms until the voltage settled. CC to CV transition began immediately and took 3ms to settle. 50V CV to 10A dead-short showed 10App oscillation at 2.2kHz. The input bulk capacitor showed 24Vpp ripple and the DC blocking capacitor showed 14.2Vpp ripple. The primary side of the transformer showed about 75% overshoot that settled within 2 cycles. The N-MOS at conduction showed 184nS fall time for Vds and 572nS rise time for Vgs. At disconduction, the Vds rise time showed as 56nS and 556nS for Vgs fall time. I’m here not to glaze over my design. After reviewing the results and doing a retrospective, here are my critical opinions about this design. What I like about this design: Good efficiency figure (89.1% at full-load) Excellent ripple even without a second-stage filtration (94mVpp at full load) Good power density for an almost-fully THT build. What I don’t like about this design: The overcurrent protection is too slow, though it somehow works at preventing the half-bridge from exploding on the dead-short test. The compensator design fails in certain conditions (DCM/CCM transitions, output dead short), which results in output oscillation. The output diodes are hard to access or replace. The full schematic, gerber files, KiCAD save files, spreadsheet calculation, and full-res images are available on my Github repository: https://github.com/Luq1308/Forwarder1kW The build process and the in-depth testing are available in my YouTube video: https://youtu.be/MGMqqtXgwRg That’s all I have about this project. I hope this post is informative and can be used as a reference or for benchmarking purposes, in which I had difficulty in researching previously. If you have any unanswered questions, let me know and I’ll try to answer them. Thank you for reading, and I'll see you next time. submitted by /u/Luq1308 [link] [comments]

Just because generational device improvements aren’t in-your-face obvious doesn’t mean they aren’t sooner-or-later still tangibly impactful.

As mentioned last week, one of the perks that accompanied my recent personal-cellular-line transition from AT&T to Google Fi Wireless was a free (after two years’ service, albeit still notably discounted upfront) Pixel 10 smartphone, which I’d needed to press into service immediately in order to qualify for the various promotion discounts (this “stock” photo is of the “Indigo” colorway; as noted last week, mine’s “Obsidian”):

As long-time readers may recall, I’ve been a (mostly) Google Pixel “daily driver” since mid-2017, across multiple product generations. And I’ve been specifically using a pair of Pixel 7s for the past three years. So, I feel a “bit” qualified to offer some observations and comparisons with past device experiences. Without further ado…

I’m not a power user

What I’m referencing by means of this admittedly cryptic initial section header is the fact that although the Pixel 10, which I initially wrote about as part of my coverage of Google’s August 2025 multi-product launch event, has a three-generation-newer Tensor SoC inside it (the G5, versus the earlier G2), the performance differences aren’t strikingly obvious. at least to me. Not that they’re nonexistent, mind you; Google’s increasingly impressive AI “chops” are most evident at the moment in the handset’s computational photography capabilities. That said, I strongly suspect that AI’s effects will be comparatively even more broadly visible (both in their results, responsiveness and fundamental existence) with the passage of time.

To that point, the “bump” in RAM from the Pixel 7 (8 GBytes) to the Pixel 10 (12 GBytes) is likely at least as important as is bolstered inference processing “muscle” in delivering local AI enhancements, as it enables on-device deep learning models to be more comprehensive and otherwise robust than would otherwise be the case, delaying if not completely foregoing a performance- and power-sapping handoff to the “cloud” in the process. And if there’s one upside to today’s semiconductor memory shortages, it’s that it’ll compel Google’s and other organizations’ developers to make their models even more efficient (while retaining sufficiently high results accuracy) than might otherwise be the case.

Pleasantly pocketable and reliably chargeable

Put the two phones side-by-side and you’ll realize that although the active screen dimensions and other high-level display attributes are identical (6.3” diagonal OLED with 1080 x 2400 pixel resolution, though the Pixel 10 variable refresh rate tops out at 120 Hz versus 90 Hz for the Pixel 7, for whatever that’s worth…), the Pixel 10 (at left in the following photos) is actually a smidge shorter and narrower, the result in part of bezel decreases, not to mention rounder:

• Pixel 7: 6.13 x 2.88 x 0.34 inches (155.6 x 73.2 x 8.7 mm)
• Pixel 10: 6.02 x 2.83 x 0.3 inches (152.8 x 72.0 x 8.6 mm)

That aside, the Pixel 10 has a higher internal battery capacity than its Pixel 7 forebear—4,970 mAh vs 4,355 mAh—and the foundry transition from Samsung to TSMC that accompanied the to-Tensor G5 SoC evolution also aspires to improve not only performance (decreasing the energy consumption necessary to complete a given task in the process) but also stored-electron efficiency, with the two factors combining to boost claimed battery life.

Speaking of battery life, a few words on charging. The Pixel 7 supports wired charging at up to a 21W incoming power payload and wireless charging at up to 12W with conventional Qi chargers or 20W with the pricey, seemingly no longer available 2nd-generation official Google Pixel Stand:

For the Pixel 10 family, there’s a new wireless charger, the magnet-augmented Pixelsnap (reflective of the magnet-inclusive and Apple MagSafe-reminiscent QI2 support now within the phones themselves), which supports 15W charging speeds with the baseline Pixel 10 and 25W for the high-end Pixel 10 Pro (both of which also support wired charging at 30W rates):

And even though, as with the Pixel 7, I still need to use a case that’s magnet-inclusive with the Pixel 10 to ensure sufficient “cling” strength to a charger or whatever else I’m striving to stick it to (or, depending on the circumstance, stick to it), MagSafe-tailored chargers now work with it, too. With the Pixel 7, charging reliability with magnet-based chargers such as my Belkin-based desktop:

and in-car setups:

was flaky at best, typically DOA with the magnet-augmented case but magnet-less foundation. Now, for whatever reason, it’s ironclad (I hope I haven’t jinxed myself by writing those words).

Optics upgrades

Speaking of computational photography, while the Pixel 7’s front camera did implement face recognition-based unlock support (for the first time since the Pixel 4), it was both too flaky and insufficiently robust in associated software support to be something I could rely on. Beginning with the Pixel 8 (therefore also including the Pixel 10), the implementation is not only faster but also more accurate and broadly robust, thanks to machine learning algorithm augmentation:

That said, it’s still reliant on the front visible light image sensor, dropping the Pixel 4’s Kinect-reminiscent and IR-derived structured light approach in the process, in an ironic contrast to the conceptually similar IR-based TrueDepth technique that Apple uses to this day with FaceID. As such, it doesn’t work great in dim light, and not at all in the dark; thankfully, Google has also seemingly improved its historically woeful fingerprint ID detection implementation as a backup in such situations. And there’s always also your PIN or other unlock sequence, after all…

One other camera-related note; in the earlier backs-of-phones images you might have noticed what appeared to be a third lens on the Pixel 10’s rear “camera bar”. Or maybe you’ve just noticed the increased prevalence of ultra-closeup pictures in my recent teardowns, ones specifically taken without the bulky multi-piece accessory I had to use previously:

Google refers to it as a 5X telephoto, and it’s admittedly nice for that, but its Macro Focus capabilities are what I’m lovin’ the most, right now at least.

Tying up loose ends

I mentioned earlier in this piece, and have also mentioned previously, how much I appreciated the fact that Google extended support (not only security patches but also full O/S updates) for the Pixel 6 and 7 series from 3 to 5 years at the end of 2024. As such, they’ll remain reliable backup-at-least options in my smartphone arsenal for at least the next year-plus. That said, beginning with the Pixel 8 series, therefore also including both my Pixel 10 and Pixel 9a, support was further extended to seven years from initial release date. Nice.

One (very) minor downside, for which I have nobody but myself to “blame” since I knew about it before I pressed “purchase”, involves ultrawideband (UWB) support. Apple’s latest-generation AirTag trackers leverage not only integrated Bluetooth and Wi-Fi subsystems but also UWB capabilities to enable more precise location discernment. So too do advanced Android-friendly trackers such as Motorola’s Moto Tags, one of which currently resides on my teardown shelf:

This is all well and good, but there’s one key qualifier: tracker-based UWB is only meaningful if the connected device that’s doing the tracking also supports UWB. That gives a green light to the Pixel 10 Pro, but not my UBW-deficient Pixel 10. Oh well…First World problems strike again.

And speaking of Android friendliness, I’m ironically writing this piece one day ahead of Google I/O 2026, with my special-project coverage of it scheduled to be published weeks ahead of this piece. Google has already talked some about Android-centric stuff at least week’s (again, as I write this) Android Show I/O Edition, replicating a cadence tradition it did for the first time a year ago. I’ll be curious to see what else Android- and Pixel-related is unveiled tomorrow. And I hope it doesn’t obsolete what I’ve just written today in the process! I’ll see you all “on the other side”, where I as-always also welcome your thoughts in the comments.

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

• Try Google Fi (Wireless)? The perks-for-the-price are why
• From T-Mobile To AT&T: It Couldn’t Have Been More Easy
• Playin’ with Google’s Pixel 7
• If you made it through the schtick, Google’s latest products were pretty fantastic
• The 2025 Google I/O conference: A deft AI pivot sustains the company’s relevance
• Google I/O 2026: Agentic AI gets serious

The post Google’s Pixel 10: Upgrading smartphones again appeared first on EDN.

Ceva’s RealSpace Elevate is a Microsoft-certified Windows Audio Processing Object (APO) that enables spatial audio for PC gaming headsets. Unlike OS-level solutions that offer limited differentiation or branded third-party applications that restrict customization, the production-ready APO gives OEMs full control over performance and product identity. This includes customizable tuning and presets optimized for gaming and entertainment use cases such as music, movies, and podcasts.

Leveraging Ceva’s RealSpace spatial audio technology, the APO integrates precise sound localization and natural externalization within the Windows APO framework for seamless deployment on Windows PCs. It is optimized for gaming headset use cases, combining rich entertainment audio with competitive gameplay enhancements.

RealSpace Elevate supports 7.1 multichannel rendering with pinpoint accuracy and a realistic soundstage. Gaming-focused enhancements include controls to highlight critical in-game sounds such as footsteps or gunshots.

The licensable APO is available now. 

RealSpace Elevate product page  

Ceva

The post Windows APO delivers customizable spatial audio appeared first on EDN.

A 3D direct ToF LiDAR module, the VL53L9CX from STMicroelectronics offers 2.3k-zone resolution for low-compute edge AI systems. This compact all-in-one module integrates a SPAD array, post-processing SoC, two VCSELs, a BCD VCSEL driver, infrared filters, metasurface optical elements (MOEs), and PMIC. It enables high-resolution spatial awareness in robotics, industrial automation, smart buildings, and healthcare.

The VL53L9CX provides 2,268 ranging zones (54×42) across a wide 55°×42° field of view, allowing detailed 3D depth mapping and precise detection of small objects, contours, and edges. With stacked BSI SPAD sensors and MOEs, the module delivers fast, accurate ranging from less than 5 cm to 8.8 m with up to 1% accuracy and frame rates up to 100 fps.

Dual-scan flood illumination reduces motion artifacts and eliminates dead zones while enhancing small-object detection. It also combines 2D infrared and 3D depth imaging, simplifying post-processing and enabling edge AI applications to run on small MCUs.

The VL53L9CX is supplied in a miniature reflowable package. Mass production is scheduled for July 2026.

VL53L9CX product page 

STMicroelectronics

The post LiDAR module generates high-resolution depth maps appeared first on EDN.

NUBURU Inc of Centennial, CO, USA (a dual-use defense & security integrated platform company focused on non-kinetic effects and directed-energy technologies, electronic warfare and defense mobility programs, software-orchestrated defense systems and advanced manufacturing) has provided an update on the commercial pipeline of its photonics and laser activities, centered on Lyocon S.r.l. and supported by the firm’s strategic collaboration with SunCubes S.r.l., i.e. the LaserTech Business Line. Management believes that the commercial activity reflected in the current tracker demonstrates growing market adoption of NUBURU’s blue-laser technologies and supports continued execution of the firm’s Defense & Security platform strategy...

The R&S PR300 portable monitoring receiver provides 125 MHz of real-time bandwidth and a scanning speed of more than 500 GHz/s. It is designed for field-based spectrum monitoring, interference hunting, high-speed signal detection, and direction finding (DF) with a directional antenna in complex RF environments.

Covering 8 kHz to 8 GHz, the PR300 supports segmented panorama scanning, embedded spectrum analysis, and time-gated direction finding. The frequency range extends to 20 GHz or 33 GHz when used with the HE400DC or HE800-DC30 handheld directional antennas, respectively. With the ADDx07 series compact DF antenna, the system achieves direction-finding accuracy better than 1° from 9 MHz to 20 GHz.

Gapless capture and analysis of wideband communication signals support applications such as radio monitoring in accordance with ITU recommendations, QoS verification, and interference hunting in 5G and LTE networks. The PR300-ZS time-domain measurement option provides simultaneous time-domain data and a corresponding time-gated frequency spectrum, useful for analyzing burst, intermittent, and transient signals.

For more information, visit the PR300 product page.

Rohde & Schwarz  

The post Handheld receiver captures wideband RF signals appeared first on EDN.

D-Wave Quantum has announced a gate-model quantum computing simulator for error-aware programming and algorithm development. The cloud-based simulator provides tools for modeling quantum processor behavior, error detection, and real-time control. It supports up to 21 qubits, ideal and hardware emulation modes, and integration with D-Wave’s Ocean SDK.

Built around D-Wave’s dual-rail technology, the simulator gives developers greater visibility into errors so they can design applications and workflows that reflect real processor behavior. It also enables Monte Carlo simulation of real-time quantum system dynamics, development of error-correction routines, and evaluation of advanced error-correction approaches based on dual-rail qubits.

D-Wave plans to offer quantum development bundles that provide access to its forthcoming gate-model quantum simulator and quantum computing systems. Available in Starter and Premium tiers, the bundles include monthly usage allocations and technical guidance from D-Wave. Pricing is available upon request.

The simulator is scheduled to be available through D-Wave’s Leap cloud platform in September 2026. Learn more and request future access here.

D-Wave Quantum 

The post Simulator emulates quantum hardware behavior appeared first on EDN.

Qualcomm’s Snapdragon Reality Elite spatial computing processor delivers 48 TOPS of AI performance for video-see-through (VST) headsets and tethered optical-see-through (OST) glasses. The processor can run large vision models (LVMs) and large language models (LLMs) locally, reducing dependence on cloud-based processing for XR applications.

Snapdragon Reality Elite supports photorealistic avatars using Gaussian Splatting, LLM-based agents, and real-time, LVM-driven object generation. These AI capabilities enable more context-aware XR experiences with natural interaction while improving head and hand tracking in see-through devices.

According to Qualcomm, the Snapdragon Reality Elite provides 60% higher GPU performance, up to 30% better CPU performance, and up to 160% greater NPU performance than the Snapdragon XR2+ Gen 2. It also enables up to 20% longer battery life at the same workload and reduces chipset temperature by up to 12°C under load. The increased power efficiency allows the design of lighter, cooler headsets and glasses that can be worn comfortably for extended periods.

Support for visuals up to 4.4K per eye at 90 fps enables sharper detail, smoother motion, and improved color fidelity. VST enhancements enabled by IP hardening, including the EVA block, reduce latency and improve image quality.

For more information, visit the Snapdragon Reality Elite product page.

Qualcomm Technologies 

The post Qualcomm powers next-gen XR with Reality Elite appeared first on EDN.

Київський політехнічний інститут поділився експертними висновками у глобальному дослідженні щодо конкурентоспроможності 6G kpi чт, 06/25/2026 - 12:42

Як гостьові лекції розширюють освітні горизонти факультету лінгвістики Інформація КП чт, 06/25/2026 - 12:00

Eggtronic of Modena, Italy (which provides mixed-signal IC controllers for power electronics) has released a jointly developed 500W solar microinverter reference platform with Renesas Electronics Corp of Tokyo, Japan...

I'm designing a DIY remote intended as a soldering kit. My design requirements were: Use a few parts as possible Make easy to assemble (so THT parts only) Make it modular so that main parts can be taken out and used in other projects. First I had to think about power management, microcontroller and RF module. I'll start with the RF module first... I chose the popular nRF24L01, although the version I am using has a can on it and has FCC/IC. I prefer this version over the generic one that is everywhere. Works well and has a ton of support! The range it can achieve is also more than sufficient for the intended applications. Since this RF module does not officially support 5V (Yes, I contacted the manufacturer .. there are some versions of the nRF24L01 that *do* support 5V, but this module does not), I had to stick with 3.3V. As my first design goal was to use as few parts as possible, I did not want to use a logic level shifter (LLS). So I needed a microcontroller that operates on 3.3V. Like the Pro Mini, but in my case a Nano form factor running on 3.3V (I had to drop the clock frequency a bit to remain within manufacturer suggested conditions). Even at reduced clock speed, the ATmega328 running at 8MHz and the nRF2401 module combined are still quite fast... at least for the human mind. (more on that below) Both the RF module and the microcontroller can operate well at 3V, so I figured I just use two AA batteries. Then I only need some filters but no other real power management components like a linear regulator. Perfect for what I was trying to design. Also, I wanted to pick batteries that are super common, cheap enough and can be recharged. I made a 3D printed base for this remote as well and it now hold very well. I used the remote as a general HID controller for a couple custom games I made and it works great. Response time is super (no lag or delay that is noticeable) and the battery lasts more than a day. All the parts are THT (through-hole) and therefore easy to solder together (second design goal). I mounted the RF module and the microcontroller using female headers. They are secure enough but this allows them to be removed easily and used in other projects. This was my third design goal. I am working on a remote car and drone (under 250g), both of which can also be controlled with this remote. So there are quite some applications. submitted by /u/PTSolns [link] [comments]

Artificial intelligence (AI) is accelerating semiconductor innovation at a pace that is forcing a rethinking of conventional production test strategies. The rapid scaling of graphics processing units (GPUs), AI accelerators, and heterogeneous compute architectures is increasing not only device complexity, but also the amount of test content required to validate performance, reliability, and quality across the manufacturing flow.

As AI infrastructure investments continue to expand, semiconductor manufacturers are building increasingly sophisticated devices that combine massive transistor counts, advanced packaging, high-bandwidth memory (HBM), chiplet architectures, and emerging co-packaged optical (CPO) interfaces. These devices are redefining the relationship between design, validation, and production test.

The result is a new test paradigm in which test content, infrastructure, and analytics are distributed dynamically across multiple insertions—from wafer sort through system-level test (SLT)—to balance cost-of-test, defective-parts-per-million (DPPM), and time-to-market objectives.

 

AI devices driving a step change in test requirements

The transition from monolithic devices to heterogeneous multi-die systems has substantially increased the burden on automated test equipment (ATE). AI processors now incorporate far more compute engines, memory bandwidth, and power-delivery complexity than previous generations of high-performance devices.

At the same time, traditional transistor scaling no longer delivers the same gains once associated with Moore’s Law. To continue improving system performance, designers are adopting More-than-Moore integration strategies that combine chiplets, 3D packaging, integrated voltage regulation, and advanced interconnect technologies within increasingly dense package architectures. These changes are producing several cascading effects on tests.

First, scan and functional test workloads are growing dramatically as transistor counts increase. Modern AI devices require extremely large volumes of scan vectors that must be delivered at gigabit-per-second speeds through either massively parallel digital channels or high-speed serial interfaces such as PCIe and USB.

Second, power requirements are rising rapidly. Device power supplies must now support kiloamp-class current delivery while maintaining tight regulation and accuracy under highly dynamic loading conditions. Flexible power architectures capable of extensive channel ganging are becoming increasingly important as final-test power envelopes continue to climb.

Thermal management is becoming equally critical. AI devices entering production are expected to push package-level power dissipation into multi-kilowatt ranges, making active thermal control essential throughout the test flow. In advanced environments, thermal systems are increasingly paired with predictive analytics capable of anticipating thermal excursions before they occur, enabling proactive cooling and tighter junction-temperature management.

Advanced packaging complicates multisite test

Migration toward larger 2.5D and 3D packages is also changing the physical realities of production test. As package sizes expand to accommodate more chiplets, HBM stacks and photonic components, device handling and multisite efficiency become more difficult to optimize. Larger sockets consume increasing amounts of device-under-test (DUT) board real estate, constraining routing resources and limiting tester scalability.

In parallel, manufacturers are moving toward larger tray formats carrying fewer devices per tray because of package dimensions and handling constraints. These shifts reduce some of the traditional efficiencies associated with high-parallelism production environments.

The addition of photonic and CPO technologies introduces another layer of complexity. Optical interfaces require integrated electro-optical validation across multiple stages of manufacturing, extending test coverage well beyond conventional electrical characterization. As a result, optical instrumentation is increasingly being introduced at wafer probe, optical-engine test, final package test, and SLT insertions.

Test engineering becoming more software- and data-centric

The growing complexity of AI devices is changing not only hardware requirements, but also the nature of test engineering itself. In other words, engineering organizations are under pressure to accelerate bring-up, reduce debug cycles, and maintain quality targets despite rapidly increasing test content volumes. This is driving tighter integration between design, silicon validation, and manufacturing teams.

As a result, AI-assisted software tools are beginning to play a larger role in test-program generation, debug optimization, and adaptive workflow management. Real-time analytics platforms can now aggregate data across multiple insertions, enabling faster correlation of failures and more intelligent allocation of test coverage throughout the production flow.

In these environments, test content is no longer statically assigned to a single insertion. Instead, coverage increasingly shifts throughout the flow depending on where defects can be detected most efficiently and economically. This distributed approach to test is becoming essential as AI devices scale toward trillion-transistor complexity.

Shifting test left reduces packaging risk

One major trend is the movement of more test content earlier in the manufacturing flow. For advanced AI devices, packaging costs now represent a substantial portion of total product cost because of technologies such as HBM and chip-on-wafer-on-substrate (CoWoS) integration. Packaging defective die into expensive multi-die assemblies can significantly increase material waste and reduce yield.

To mitigate this risk, manufacturers are pushing more coverage to wafer-level and die-level test insertions to improve known-good-die confidence before assembly. Figure 1 illustrates how test distribution increasingly spans the entire workflow, with tighter interaction between design, validation, and production environments.

Figure 1 Test distribution has expanded to accommodate growing need for test across the manufacturing ecosystem—beginning with silicon validation and extending through system-level test. Source: Advantest

This shift-left strategy (Figure 2) includes broader scan coverage and expanded fault modeling at speed testing, and increasingly system-aware functional validation at the die level. Some workflows also incorporate calibration, trimming, and memory repair operations prior to package assembly.

Figure 2 Shifting test content left enables more coverage at wafer and die test stages to improve known-good-die screening before package assembly. Source: Advantest

In more advanced implementations, active thermal control capabilities are also migrating closer to singulated-die test stages. The objective is straightforward: identify marginal or defective components before they enter expensive advanced-packaging flows.

System-level test expanding

At the same time, other forms of coverage are shifting later in the process. As devices become more heterogeneous and application-specific, certain failure mechanisms emerge only under realistic operating conditions involving software execution, thermal loading, timing interactions, or high-bandwidth traffic patterns.

These conditions are often difficult—or impossible—to replicate during traditional structural or functional test insertions. Consequently, SLT is becoming increasingly important for AI and HPC devices. System-level environments can expose defects associated with workload execution, protocol interactions, and real-world operating states that are not observable during earlier production stages.

New approaches, including scan-over-PCIe methodologies and highly parallel SLT architectures, are helping manufacturers improve coverage while attempting to control the significant test times associated with these environments. Figure 3 illustrates the corresponding shift-right strategy.

Figure 3 Shifting test content right enables additional test coverage to be executed after packaging to further reduce DPPM before shipment. Source: Advantest

Real-time analytics enabling adaptive test distribution

The increasing fragmentation of test insertions is creating demand for tighter orchestration across the production floor. Modern test infrastructures are evolving toward highly connected environments in which data streams continuously between validation, wafer sort, final test, and SLT operations. Real-time analytics platforms can then use this data to optimize insertion decisions, adapt test limits, and improve yield-learning cycles.

GPU-accelerated edge inferencing and AI-based decision engines are also enabling faster adaptive responses during production. In some cases, computation can be offloaded from the tester itself to remote compute infrastructure, allowing more sophisticated analytics without compromising throughput.

This level of coordination requires consistent software frameworks and portable test content capable of moving seamlessly between insertions and platforms. So, shared execution environments and unified debug tools are becoming increasingly important as manufacturers attempt to reduce engineering overhead while accelerating deployment.

Optical test adds new workflow stages

CPO and photonic integration introduce additional challenges because optical functionality must be validated alongside traditional electronic behavior. Unlike conventional semiconductor devices, photonic systems often require multiple dedicated insertion points throughout manufacturing. These may include photonic wafer test, dual-sided probing of electronic and photonic die, optical-engine characterization, and additional packaged-module validation after integration with ASICs.

As with electrical tests, much of this optical validation is shifting earlier in the flow to ensure known-good optical engines prior to final assembly. However, full electro-optical verification often still requires additional socketed final-test and SLT insertions after system integration.

Figure 4 highlights how optical test introduces additional insertion points spanning photonic wafer test, optical-engine validation, final package test, and SLT.

Figure 4 For testing CPO devices, test content shifts left for three insertions and right for final socketed device test. Source: Advantest

Test distribution is becoming a strategic optimization problem

AI is transforming semiconductor tests from a relatively linear production step into a highly distributed optimization challenge involving power, thermal management, data analytics, packaging economics, and workflow orchestration. Meeting future quality and throughput requirements will require closer collaboration across the semiconductor ecosystem, including design teams, ATE suppliers, packaging providers, and system integrators.

As AI devices continue scaling in complexity, test infrastructure must evolve from traditional defect screening toward intelligent, adaptive validation environments capable of making real-time decisions across the manufacturing flow. In that sense, the future of semiconductor test may depend as much on data movement and workflow intelligence as on the tester hardware itself.

Fabio Pizza is business segment manager at Advantest Europe.

Related Content

• Will AI come to the test industry?
• Optimizing Automated Test Equipment for Quality and Complexity
• Advanced verification: unlocking the door to a new era of AI chips
• AI test chip offers proof of concept for digital in-memory compute design
• From Defect Images to Die Prediction: How Intel Is Scaling AI in Advanced Manufacturing

The post How AI is driving a new paradigm in test distribution appeared first on EDN.

У КПІ відкрили оновлену навчально-наукову лабораторію технології та модифікування біополімерів kpi ср, 06/24/2026 - 16:58