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Ceva’s RealSpace Elevate is a Microsoft-certified Windows Audio Processing Object (APO) that enables spatial audio for PC gaming headsets. Unlike OS-level solutions that offer limited differentiation or branded third-party applications that restrict customization, the production-ready APO gives OEMs full control over performance and product identity. This includes customizable tuning and presets optimized for gaming and entertainment use cases such as music, movies, and podcasts.

Leveraging Ceva’s RealSpace spatial audio technology, the APO integrates precise sound localization and natural externalization within the Windows APO framework for seamless deployment on Windows PCs. It is optimized for gaming headset use cases, combining rich entertainment audio with competitive gameplay enhancements.

RealSpace Elevate supports 7.1 multichannel rendering with pinpoint accuracy and a realistic soundstage. Gaming-focused enhancements include controls to highlight critical in-game sounds such as footsteps or gunshots.

The licensable APO is available now. 

RealSpace Elevate product page  

Ceva

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A 3D direct ToF LiDAR module, the VL53L9CX from STMicroelectronics offers 2.3k-zone resolution for low-compute edge AI systems. This compact all-in-one module integrates a SPAD array, post-processing SoC, two VCSELs, a BCD VCSEL driver, infrared filters, metasurface optical elements (MOEs), and PMIC. It enables high-resolution spatial awareness in robotics, industrial automation, smart buildings, and healthcare.

The VL53L9CX provides 2,268 ranging zones (54×42) across a wide 55°×42° field of view, allowing detailed 3D depth mapping and precise detection of small objects, contours, and edges. With stacked BSI SPAD sensors and MOEs, the module delivers fast, accurate ranging from less than 5 cm to 8.8 m with up to 1% accuracy and frame rates up to 100 fps.

Dual-scan flood illumination reduces motion artifacts and eliminates dead zones while enhancing small-object detection. It also combines 2D infrared and 3D depth imaging, simplifying post-processing and enabling edge AI applications to run on small MCUs.

The VL53L9CX is supplied in a miniature reflowable package. Mass production is scheduled for July 2026.

VL53L9CX product page 

STMicroelectronics

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NUBURU Inc of Centennial, CO, USA (a dual-use defense & security integrated platform company focused on non-kinetic effects and directed-energy technologies, electronic warfare and defense mobility programs, software-orchestrated defense systems and advanced manufacturing) has provided an update on the commercial pipeline of its photonics and laser activities, centered on Lyocon S.r.l. and supported by the firm’s strategic collaboration with SunCubes S.r.l., i.e. the LaserTech Business Line. Management believes that the commercial activity reflected in the current tracker demonstrates growing market adoption of NUBURU’s blue-laser technologies and supports continued execution of the firm’s Defense & Security platform strategy...

The R&S PR300 portable monitoring receiver provides 125 MHz of real-time bandwidth and a scanning speed of more than 500 GHz/s. It is designed for field-based spectrum monitoring, interference hunting, high-speed signal detection, and direction finding (DF) with a directional antenna in complex RF environments.

Covering 8 kHz to 8 GHz, the PR300 supports segmented panorama scanning, embedded spectrum analysis, and time-gated direction finding. The frequency range extends to 20 GHz or 33 GHz when used with the HE400DC or HE800-DC30 handheld directional antennas, respectively. With the ADDx07 series compact DF antenna, the system achieves direction-finding accuracy better than 1° from 9 MHz to 20 GHz.

Gapless capture and analysis of wideband communication signals support applications such as radio monitoring in accordance with ITU recommendations, QoS verification, and interference hunting in 5G and LTE networks. The PR300-ZS time-domain measurement option provides simultaneous time-domain data and a corresponding time-gated frequency spectrum, useful for analyzing burst, intermittent, and transient signals.

For more information, visit the PR300 product page.

Rohde & Schwarz  

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D-Wave Quantum has announced a gate-model quantum computing simulator for error-aware programming and algorithm development. The cloud-based simulator provides tools for modeling quantum processor behavior, error detection, and real-time control. It supports up to 21 qubits, ideal and hardware emulation modes, and integration with D-Wave’s Ocean SDK.

Built around D-Wave’s dual-rail technology, the simulator gives developers greater visibility into errors so they can design applications and workflows that reflect real processor behavior. It also enables Monte Carlo simulation of real-time quantum system dynamics, development of error-correction routines, and evaluation of advanced error-correction approaches based on dual-rail qubits.

D-Wave plans to offer quantum development bundles that provide access to its forthcoming gate-model quantum simulator and quantum computing systems. Available in Starter and Premium tiers, the bundles include monthly usage allocations and technical guidance from D-Wave. Pricing is available upon request.

The simulator is scheduled to be available through D-Wave’s Leap cloud platform in September 2026. Learn more and request future access here.

D-Wave Quantum 

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Qualcomm’s Snapdragon Reality Elite spatial computing processor delivers 48 TOPS of AI performance for video-see-through (VST) headsets and tethered optical-see-through (OST) glasses. The processor can run large vision models (LVMs) and large language models (LLMs) locally, reducing dependence on cloud-based processing for XR applications.

Snapdragon Reality Elite supports photorealistic avatars using Gaussian Splatting, LLM-based agents, and real-time, LVM-driven object generation. These AI capabilities enable more context-aware XR experiences with natural interaction while improving head and hand tracking in see-through devices.

According to Qualcomm, the Snapdragon Reality Elite provides 60% higher GPU performance, up to 30% better CPU performance, and up to 160% greater NPU performance than the Snapdragon XR2+ Gen 2. It also enables up to 20% longer battery life at the same workload and reduces chipset temperature by up to 12°C under load. The increased power efficiency allows the design of lighter, cooler headsets and glasses that can be worn comfortably for extended periods.

Support for visuals up to 4.4K per eye at 90 fps enables sharper detail, smoother motion, and improved color fidelity. VST enhancements enabled by IP hardening, including the EVA block, reduce latency and improve image quality.

For more information, visit the Snapdragon Reality Elite product page.

Qualcomm Technologies 

The post Qualcomm powers next-gen XR with Reality Elite appeared first on EDN.

Київський політехнічний інститут поділився експертними висновками у глобальному дослідженні щодо конкурентоспроможності 6G kpi чт, 06/25/2026 - 12:42

Як гостьові лекції розширюють освітні горизонти факультету лінгвістики Інформація КП чт, 06/25/2026 - 12:00

Eggtronic of Modena, Italy (which provides mixed-signal IC controllers for power electronics) has released a jointly developed 500W solar microinverter reference platform with Renesas Electronics Corp of Tokyo, Japan...

I'm designing a DIY remote intended as a soldering kit. My design requirements were: Use a few parts as possible Make easy to assemble (so THT parts only) Make it modular so that main parts can be taken out and used in other projects. First I had to think about power management, microcontroller and RF module. I'll start with the RF module first... I chose the popular nRF24L01, although the version I am using has a can on it and has FCC/IC. I prefer this version over the generic one that is everywhere. Works well and has a ton of support! The range it can achieve is also more than sufficient for the intended applications. Since this RF module does not officially support 5V (Yes, I contacted the manufacturer .. there are some versions of the nRF24L01 that *do* support 5V, but this module does not), I had to stick with 3.3V. As my first design goal was to use as few parts as possible, I did not want to use a logic level shifter (LLS). So I needed a microcontroller that operates on 3.3V. Like the Pro Mini, but in my case a Nano form factor running on 3.3V (I had to drop the clock frequency a bit to remain within manufacturer suggested conditions). Even at reduced clock speed, the ATmega328 running at 8MHz and the nRF2401 module combined are still quite fast... at least for the human mind. (more on that below) Both the RF module and the microcontroller can operate well at 3V, so I figured I just use two AA batteries. Then I only need some filters but no other real power management components like a linear regulator. Perfect for what I was trying to design. Also, I wanted to pick batteries that are super common, cheap enough and can be recharged. I made a 3D printed base for this remote as well and it now hold very well. I used the remote as a general HID controller for a couple custom games I made and it works great. Response time is super (no lag or delay that is noticeable) and the battery lasts more than a day. All the parts are THT (through-hole) and therefore easy to solder together (second design goal). I mounted the RF module and the microcontroller using female headers. They are secure enough but this allows them to be removed easily and used in other projects. This was my third design goal. I am working on a remote car and drone (under 250g), both of which can also be controlled with this remote. So there are quite some applications. submitted by /u/PTSolns [link] [comments]

Artificial intelligence (AI) is accelerating semiconductor innovation at a pace that is forcing a rethinking of conventional production test strategies. The rapid scaling of graphics processing units (GPUs), AI accelerators, and heterogeneous compute architectures is increasing not only device complexity, but also the amount of test content required to validate performance, reliability, and quality across the manufacturing flow.

As AI infrastructure investments continue to expand, semiconductor manufacturers are building increasingly sophisticated devices that combine massive transistor counts, advanced packaging, high-bandwidth memory (HBM), chiplet architectures, and emerging co-packaged optical (CPO) interfaces. These devices are redefining the relationship between design, validation, and production test.

The result is a new test paradigm in which test content, infrastructure, and analytics are distributed dynamically across multiple insertions—from wafer sort through system-level test (SLT)—to balance cost-of-test, defective-parts-per-million (DPPM), and time-to-market objectives.

 

AI devices driving a step change in test requirements

The transition from monolithic devices to heterogeneous multi-die systems has substantially increased the burden on automated test equipment (ATE). AI processors now incorporate far more compute engines, memory bandwidth, and power-delivery complexity than previous generations of high-performance devices.

At the same time, traditional transistor scaling no longer delivers the same gains once associated with Moore’s Law. To continue improving system performance, designers are adopting More-than-Moore integration strategies that combine chiplets, 3D packaging, integrated voltage regulation, and advanced interconnect technologies within increasingly dense package architectures. These changes are producing several cascading effects on tests.

First, scan and functional test workloads are growing dramatically as transistor counts increase. Modern AI devices require extremely large volumes of scan vectors that must be delivered at gigabit-per-second speeds through either massively parallel digital channels or high-speed serial interfaces such as PCIe and USB.

Second, power requirements are rising rapidly. Device power supplies must now support kiloamp-class current delivery while maintaining tight regulation and accuracy under highly dynamic loading conditions. Flexible power architectures capable of extensive channel ganging are becoming increasingly important as final-test power envelopes continue to climb.

Thermal management is becoming equally critical. AI devices entering production are expected to push package-level power dissipation into multi-kilowatt ranges, making active thermal control essential throughout the test flow. In advanced environments, thermal systems are increasingly paired with predictive analytics capable of anticipating thermal excursions before they occur, enabling proactive cooling and tighter junction-temperature management.

Advanced packaging complicates multisite test

Migration toward larger 2.5D and 3D packages is also changing the physical realities of production test. As package sizes expand to accommodate more chiplets, HBM stacks and photonic components, device handling and multisite efficiency become more difficult to optimize. Larger sockets consume increasing amounts of device-under-test (DUT) board real estate, constraining routing resources and limiting tester scalability.

In parallel, manufacturers are moving toward larger tray formats carrying fewer devices per tray because of package dimensions and handling constraints. These shifts reduce some of the traditional efficiencies associated with high-parallelism production environments.

The addition of photonic and CPO technologies introduces another layer of complexity. Optical interfaces require integrated electro-optical validation across multiple stages of manufacturing, extending test coverage well beyond conventional electrical characterization. As a result, optical instrumentation is increasingly being introduced at wafer probe, optical-engine test, final package test, and SLT insertions.

Test engineering becoming more software- and data-centric

The growing complexity of AI devices is changing not only hardware requirements, but also the nature of test engineering itself. In other words, engineering organizations are under pressure to accelerate bring-up, reduce debug cycles, and maintain quality targets despite rapidly increasing test content volumes. This is driving tighter integration between design, silicon validation, and manufacturing teams.

As a result, AI-assisted software tools are beginning to play a larger role in test-program generation, debug optimization, and adaptive workflow management. Real-time analytics platforms can now aggregate data across multiple insertions, enabling faster correlation of failures and more intelligent allocation of test coverage throughout the production flow.

In these environments, test content is no longer statically assigned to a single insertion. Instead, coverage increasingly shifts throughout the flow depending on where defects can be detected most efficiently and economically. This distributed approach to test is becoming essential as AI devices scale toward trillion-transistor complexity.

Shifting test left reduces packaging risk

One major trend is the movement of more test content earlier in the manufacturing flow. For advanced AI devices, packaging costs now represent a substantial portion of total product cost because of technologies such as HBM and chip-on-wafer-on-substrate (CoWoS) integration. Packaging defective die into expensive multi-die assemblies can significantly increase material waste and reduce yield.

To mitigate this risk, manufacturers are pushing more coverage to wafer-level and die-level test insertions to improve known-good-die confidence before assembly. Figure 1 illustrates how test distribution increasingly spans the entire workflow, with tighter interaction between design, validation, and production environments.

Figure 1 Test distribution has expanded to accommodate growing need for test across the manufacturing ecosystem—beginning with silicon validation and extending through system-level test. Source: Advantest

This shift-left strategy (Figure 2) includes broader scan coverage and expanded fault modeling at speed testing, and increasingly system-aware functional validation at the die level. Some workflows also incorporate calibration, trimming, and memory repair operations prior to package assembly.

Figure 2 Shifting test content left enables more coverage at wafer and die test stages to improve known-good-die screening before package assembly. Source: Advantest

In more advanced implementations, active thermal control capabilities are also migrating closer to singulated-die test stages. The objective is straightforward: identify marginal or defective components before they enter expensive advanced-packaging flows.

System-level test expanding

At the same time, other forms of coverage are shifting later in the process. As devices become more heterogeneous and application-specific, certain failure mechanisms emerge only under realistic operating conditions involving software execution, thermal loading, timing interactions, or high-bandwidth traffic patterns.

These conditions are often difficult—or impossible—to replicate during traditional structural or functional test insertions. Consequently, SLT is becoming increasingly important for AI and HPC devices. System-level environments can expose defects associated with workload execution, protocol interactions, and real-world operating states that are not observable during earlier production stages.

New approaches, including scan-over-PCIe methodologies and highly parallel SLT architectures, are helping manufacturers improve coverage while attempting to control the significant test times associated with these environments. Figure 3 illustrates the corresponding shift-right strategy.

Figure 3 Shifting test content right enables additional test coverage to be executed after packaging to further reduce DPPM before shipment. Source: Advantest

Real-time analytics enabling adaptive test distribution

The increasing fragmentation of test insertions is creating demand for tighter orchestration across the production floor. Modern test infrastructures are evolving toward highly connected environments in which data streams continuously between validation, wafer sort, final test, and SLT operations. Real-time analytics platforms can then use this data to optimize insertion decisions, adapt test limits, and improve yield-learning cycles.

GPU-accelerated edge inferencing and AI-based decision engines are also enabling faster adaptive responses during production. In some cases, computation can be offloaded from the tester itself to remote compute infrastructure, allowing more sophisticated analytics without compromising throughput.

This level of coordination requires consistent software frameworks and portable test content capable of moving seamlessly between insertions and platforms. So, shared execution environments and unified debug tools are becoming increasingly important as manufacturers attempt to reduce engineering overhead while accelerating deployment.

Optical test adds new workflow stages

CPO and photonic integration introduce additional challenges because optical functionality must be validated alongside traditional electronic behavior. Unlike conventional semiconductor devices, photonic systems often require multiple dedicated insertion points throughout manufacturing. These may include photonic wafer test, dual-sided probing of electronic and photonic die, optical-engine characterization, and additional packaged-module validation after integration with ASICs.

As with electrical tests, much of this optical validation is shifting earlier in the flow to ensure known-good optical engines prior to final assembly. However, full electro-optical verification often still requires additional socketed final-test and SLT insertions after system integration.

Figure 4 highlights how optical test introduces additional insertion points spanning photonic wafer test, optical-engine validation, final package test, and SLT.

Figure 4 For testing CPO devices, test content shifts left for three insertions and right for final socketed device test. Source: Advantest

Test distribution is becoming a strategic optimization problem

AI is transforming semiconductor tests from a relatively linear production step into a highly distributed optimization challenge involving power, thermal management, data analytics, packaging economics, and workflow orchestration. Meeting future quality and throughput requirements will require closer collaboration across the semiconductor ecosystem, including design teams, ATE suppliers, packaging providers, and system integrators.

As AI devices continue scaling in complexity, test infrastructure must evolve from traditional defect screening toward intelligent, adaptive validation environments capable of making real-time decisions across the manufacturing flow. In that sense, the future of semiconductor test may depend as much on data movement and workflow intelligence as on the tester hardware itself.

Fabio Pizza is business segment manager at Advantest Europe.

Related Content

• Will AI come to the test industry?
• Optimizing Automated Test Equipment for Quality and Complexity
• Advanced verification: unlocking the door to a new era of AI chips
• AI test chip offers proof of concept for digital in-memory compute design
• From Defect Images to Die Prediction: How Intel Is Scaling AI in Advanced Manufacturing

The post How AI is driving a new paradigm in test distribution appeared first on EDN.

У КПІ відкрили оновлену навчально-наукову лабораторію технології та модифікування біополімерів kpi ср, 06/24/2026 - 16:58

Hey guys I just made my first ever PCB at college. I designed it online and then cut it out with a PCB-CNC machine. We didn’t have time for the teachers to show me the masking process so we just did it without. \\ The red wire is because I made a mistake with the design but it worked out in the end. \\ It’s a traffic light if you couldn’t tell with an AtMega submitted by /u/EDC_powerlifter [link] [comments]

An only slightly less simple followup circuit also ratios sensor capacitance to a reference capacitor to measure micrometers…this time linearly.

A few weeks ago, Design Ideas published a simple circuit of mine that provides an analog interface to capacitive position sensors. Figure 1 shows that basic design with its separate complementary outputs: Out and –Out.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Figure 1 The U1a and U1b cross-coupled Schmidt trigger timers form a ~1MHz RC multivibrator. The Tsense pulse width is inversely proportional to sensor displacement (Tref/Tsen= Cref/Csen = d).

Figure 2 shows the “Simple Simon” method it offered for acquisition of the sensor position signal: passive RC averaging of the Tsense pulse train.

Figure 2 Passive RC averaging of the Tsense output yields the analog position output.

The resulting analog output, as shown in figure 3, provides good range and resolution but is nonlinear.

Figure 3 This graph shows the sensor performance when Out is connected to a 12bit ADC using +5V for its reference. The black curve (left axis) equals the plate separation (d) in millimeters. The red curve (right axis) equals the ADC lsb resolution in micrometers.

So, I got to thinking about linearization and the advantages it would provide, and wondering how tough it would be.  It turned out to be not that difficult. 

Figure 4 shows the resulting interface with added linearization circuitry.  Just an added opamp, three resistors, and two non-critical caps did the trick.  Here’s how it works.

Figure 4 Averaging integrator A1 linearizes the displacement sensing response.  R5 is shown as a precision type, albeit just out of force of habit.  It, like the ON resistances of U2’s switches, actually cancels out.

Each capacitance measurement cycle, the 500ns Tref pulse causes 4066 switch U2d to deposit a quantum of charge on integrator A1’s summing node of Qref = Tref/R5.  Meanwhile the sensor-capacitance proportional Tsen pulse subtracts Qsen = Tsen(Vout – 1)/R5.  The charge balance is forced by A1 to maintain Qsen = Qref, therefore Tsen(Vout – 1)/R5 = Tref/R5, and Vout – 1 = Tref/Tsen = Cref/Csen = d. Note that R5 magically (?) disappears from the math.

Figure 5 shows the straight-as-an-arrow-in-zero-gravity result.

Figure 5 In this graph of the enhanced circuit results, the black curve equates to the sensor readout d in mm, with red at a constant 1 mV per micron resolution.

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

Related Content

• ~0.1% resolution capacitive position sensor
• Capacitor matchmaker
• CMOS flip-flop used “off label” implements precision capacitance sensor
• From gap to signal: Non-contact capacitive displacement sensors
• Simple circuit interfaces differential capacitance sensor

The post Capacitive position sensor with linearized output appeared first on EDN.

The research institute TNO (the Netherlands Organization for Applied Scientific Research in Delft) and equipment provider Advanced Semiconductor Materials Lithography (ASML) of Veldhoven, The Netherlands have announced a new partnership that aims to strengthen the European semiconductor ecosystem through the development and industrialization of photonic chips. The collaboration focuses on the utilization of TNO’s new Photonic Chip Pilot Line currently under construction at the High Tech Campus in Eindhoven...

This is my version of qron0b. Meet takku:b, a BCD wristwatch which uses CR2032. It uses 0.6uA during sleep and when awake uses around 4mA - 4.5mA depending on the amount of LED is turned on. It is made using STM32L010C6 It currently displays following info on each cyclic display: Time in Hours and Minutes Weekday and Date Month and Year Will be adding alarm soon. submitted by /u/Independent_Limit_44 [link] [comments]

Infineon Technologies AG of Munich, Germany says that its CoolGaN Transistor 100V devices have been selected by BRC Solar GmbH of Ettlingen, Germany (which provides module-level power electronics for photovoltaic systems) as the core switching technology for its Power Optimizer...

Міжнародна конференція "Прикладна геометрія, інженерна графіка та об'єкти інтелектуальної власності" 2026 Інформація КП ср, 06/24/2026 - 12:00

ClassOne Technology of Kalispell, MT, USA (which manufactures electroplating and wet-chemical process systems for ≤200mm wafers) has announced record follow-on orders from Applied Optoelectronics Inc (AOI) of Sugar Land, TX, USA (a designer and manufacturer of optical and hybrid fibre-coaxial networking products for AI data centers, cable TV and broadband fiber access networks) for multiple Solstice S8 single-wafer wet processing systems to support AOI’s expanding production of optical devices in Houston...