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The UNO Media Carrier is a carrier board that brings two MIPI-CSI camera inputs, one MIPI-DSI display output and three 3.5 mm audio jacks to compatible host boards. The connection runs through the high-speed JMEDIA and JMISC connectors, so the board stays in the UNO form factor. That way the multimedia capabilities of the UNO Q and VENTUNO Q are extended without touching the host board’s headers directly.

The strong point lies in the standard connectors. Two 22-pin MIPI-CSI ports accept IMX219 cameras, for example the Camera Module 2, and open the way to computer vision applications with dual cameras. A 22-pin MIPI-DSI port, meanwhile, supports Waveshare displays, so you add an interactive visual output without any special soldering.

On the audio side the carrier offers three separate 3.5 mm jacks: a combined microphone input and headphone output, a line out for amplifiers or powered speakers, and an ear out for connecting earphones directly. In addition, the JMEDIA and JMISC connectors have a passthrough design, so all the host board signals remain accessible for stacking additional modules or carriers.

The exposed signals: I2C, PSSI and two-voltage GPIO

Besides the multimedia connectors, the board exposes several interfaces useful to anyone who wants to integrate sensors and peripherals. There is I2C (CCI and MCU I2C4), an 8-bit PSSI parallel camera interface, the SoC GPIOs at 1.8 V and the MCU GPIOs at 3.3 V. This dual voltage reflects the architecture of the UNO Q, which pairs an STM32U585 microcontroller with an application processor.

For those who want to get started right away, the 8-megapixel camera module with a Sony IMX219 sensor is the right component to pair with the two MIPI-CSI inputs. The module with the IMX219 sensor for Raspberry Pi 5 covers exactly that kind of application, from surveillance to embedded computer vision.

Power, dimensions and operating temperature

The VIN (DC_IN) supply accepts 7 to 24 V DC through the 4-pin J13 header. The VCOIN input, on the other hand, is 3.0 V DC for the host board’s RTC, with a maximum of 3.6 V, and goes through the 4-pin J10 header. The dimensions are 68.58 x 53.34 mm, so the form factor stays UNO, and the temperature range goes from -10 to 60 degrees. The board also has room for 4 RGB LEDs.

• Two 22-pin MIPI-CSI connectors for IMX219 cameras
• One 22-pin MIPI-DSI connector for Waveshare displays
• Three 3.5 mm audio jacks: mic/headphones, line out, ear out
• JMEDIA and JMISC connectors, 60-pin female, in passthrough
• I2C (CCI and MCU I2C4) and 8-bit PSSI
• SoC GPIOs at 1.8 V and MCU GPIOs at 3.3 V

The list price is 19.25 dollars, or 19.89 euros including VAT, on the Arduino store. For those who want to start from scratch with the host board, the complete kit with accessories for the UNO Q 4GB covers the starting point. The complete kit with accessories for the UNO Q 4GB combines the STM32U585 microcontroller with the application processor, that is, the same combination that the Media Carrier sets out to extend.

On the software side Arduino provides a User Manual and a Kiosk Mode tutorial, which explains how to connect and configure the UNO Q and Media Carrier with a Waveshare touch display. Those who want to dig deeper will find everything on the Arduino maker site, where the manual and tutorial are collected.

Source: https://docs.arduino.cc/hardware/uno-media-carrier/

Related products

• 8MP Camera Module with Sony IMX219 for Raspberry Pi 5
• Arduino UNO Q 4GB – Complete kit with accessories

The post UNO Media Carrier: cameras, displays and audio for the UNO Q appeared first on Open Electronics.

KnowMade’s latest Lateral Power GaN Patent Monitor update on inventions, patent grants and emerging players across the power gallium nitride (GaN) supply chain shows that second-quarter 2026 was led by industrial patent assignees, while several Chinese universities maintained a strong presence in GaN power device innovation...

Materials technology company Mivium Inc of Fremont, CA, USA has achieved the production of high-purity submicron gallium nitride (GaN) particles using its proprietary technology platform (which extends to additional wide-bandgap and advanced semiconductor materials including gallium oxide and boron nitride)...

Renesas Electronics Corporation, a premier supplier of advanced semiconductor solutions, has expanded its GaN portfolio into low-voltage applications with its first family of 100V enhancement mode (E-mode) GaN-based discrete power transistors. The RTP100E005G1FL, RTP100E2P6G1FL, RTP100E1P8G1FL-DSC and RTP100E1P2G1FL-DSC low-voltage GaN FETs deliver ultra-fast switching speeds and enhanced thermal performance in efficiency-critical, high power density applications, including AI data centers, humanoid robotics, factory automation and industrial motor drives, power tools and solar microinverters.

The new GaN FETs achieve industry-leading hard- and soft-switching figure-of-merit (FOM) performance, delivering up to 35% lower hard-switching FOM and up to 63% lower soft-switching FOM than comparable GaN devices. The low-voltage GaN devices also maintain a silicon-compatible footprint that allows for easy adoption into existing designs.

Power converters in today’s data centers generally operate at switching frequencies of a few hundred kilohertz. But as AI servers and industrial infrastructure transition to 800 VDC power distribution and 48V bus architectures, many converter stages are moving toward megahertz-class switching to shrink magnetics, increase power density and improve overall efficiency.

Using low-voltage GaN in 800V high-voltage direct current (HVDC) power architectures simplifies power conversion design, significantly reducing passive component size, switching losses and cooling requirements. At the system level, this translates to better efficiency, fewer thermal management requirements and lower energy and BOM costs.

Broad GaN Portfolio Yields Greater Efficiency, Power Density and Design Flexibility

Built on Renesas’ recently expanded low-voltage E-mode GaN technology platform, this new transistor portfolio features ultra fast GaN switching with low total gate charge (Qg) and output charge (Qoss) to minimize the overlap between voltage and current. It reduces energy lost in each conversion cycle across AI power supply units, motor drives and DC-DC power stages. The devices also offer zero reverse recovery (Qrr = 0), which eliminates energy losses for immediate switching efficiency gains.

Fast switching increases power density and yields higher frequency operation by shrinking PCB footprint and reducing the size of magnetic and passive components, while low RDS(on) improves operating efficiency by curtailing conduction losses. Available bottom- and dual-side cooling configurations provide added heat dissipation and design flexibility. Depending on application requirements and power-conversion architecture, the low-voltage GaN devices can achieve up to 40–70% lower switching losses and up to twice the power density at the system level.

The new GaN transistors are offered in multiple standard MOSFET-compatible packages, allowing customers to quickly migrate from silicon MOSFET layouts for faster design implementation without significant PCB rework. The package options, combined with a wide RDS(on) range (5 mΩ-1.2 mΩ), enable designers to scale across power levels and applications, including synchronous rectification, multiphase buck conversion and motor drives.

“Customers adopting next-generation GaN technology for AI servers, robotics, industrial motor drives and renewable energy systems are looking for ways to deliver more efficient power conversion performance from increasingly compact systems,” said Akhil Nair, Senior Director, Low-Voltage GaN at Renesas. “Our low-voltage GaN family delivers the efficiency, switching performance and power density designers expect from GaN while making it significantly easier to transition from existing silicon MOSFET designs.”

High GaN Performance in Silicon-Compatible Footprints

The new GaN family is built on E-mode (normally off) GaN technology, which offers the performance advantages of GaN in a convenient silicon-compatible footprint. This helps designers capture the efficiency and power benefits of GaN and simplifies migration from existing silicon-based designs.

Key features of the new low-voltage GaN family

• 1 to 3% higher efficiency over silicon-based designs, eliminating Qrr loss
• Drastic 40 to 70% reduction in switching losses
• Doubled power density by reducing switching energy per cycle and supporting high frequency operation
• Smaller system footprint with higher switching frequency reducing magnetics size and lowering overall system losses
• Optimized thermal management reduces fan and active cooling requirements, cutting system complexity and BOM cost

Additionally, with its lower total energy consumption per power stage, the new GaN family helps designers meet sustainability objectives. This is achieved by reducing the size of fans required for thermal and airflow management, enabling the use of smaller magnetics and shrinking overall PCB footprint, which contributes to AI data center and industrial energy efficiency targets.

The post Renesas Expands GaN Portfolio with First Low-Voltage GaN FETs for AI Data Centers and Robotics appeared first on ELE Times.

How leading enterprise AI platforms are helping organisations build, deploy, govern, and scale autonomous AI agents

Moving from chatbot and content generation to AI agents that think and plan, use tools, may incorporate enterprise data, and can take multiple actions. Generating several actions, generating enterprise data, and performing multiple actions. By 2026, enterprises will increasingly consider agent platforms for model quality, security, governance, integration, observability, and the ability to deploy AI endeavours at scale from proof of concept to production.

Here are 10 leading AI agent platforms enterprises should consider.

1. Microsoft Copilot Studio

Microsoft Copilot Studio enables customers to build their own generative AI agents with knowledge of your business, workflows, connectors, REST APIs, and MCP (Model Context Protocol) servers. These can be deployed to Microsoft Teams, websites, and enterprise apps, as well as communicate with each other. As a close Microsoft 365 and Power Platform partner, it targets organisations committed to the Microsoft ecosystem.

2. Google Gemini Enterprise Agent Platform

Google Cloud’s Gemini Enterprise Agent Platform, previously part of the agent capabilities of Vertex AI, is a complete platform for developing, deploying, governing, and refining enterprise AI agents. It includes the Gemini models as well as models from open source via Model Garden, Agent Development Kit (ADK), evaluation tools, and enterprise data grounding.

3. Amazon Bedrock AgentCore

AWS is growing the agent ecosystem by launching Amazon Bedrock Agent Core, a runtime for creating and managing agents with runtime, identity, access control, policy, memory, tool interface, evaluation, and observability. AWS has expanded Agent Core in the Asia Pacific (Hyderabad) region in August 2026. AWS has also announced Bedrock Managed Agents-powered by OpenAI in preview in September 2026.

4. Salesforce Agentforce

Salesforce Agentforce is for enterprise organisations looking to inject AI agent capabilities directly into their customer and business workflows. Agentforce 360, which provides the foundation for the Agentforce product, integrates agents with Salesforce data, metadata, applications and business logic. It fuses adaptive AI with deterministic controls and has security and observability functionality for enterprise deployments.

5. ServiceNow AI Platform

ServiceNow defines both an enterprise AI platform and the bundling of its advanced machine learning (AML) features called Otto as autonomous enterprise work. Its cloud platform automates integrations of AI agents with workflows, systems of record, business rules, and enterprise processes in IT, HR, security, finance, procurement, customer service, and others. ServiceNow’s managed execution strategy may attract enterprises that have made an investment in ServiceNow workflow automation.

6. IBM watsonx Orchestrate

IBM watsonx Orchestrate is about orchestrating enterprise AI agents across frameworks and environments. The 2026 Agentic Control Plane includes a centralised management, governance, and visibility system, agent management, agent cache, and scheduling. The system embraces the new open environment where agent builders from different teams and technologies can be combined.

7. Oracle AI Agent Studio

Oracle AI Agent Studio enables your organisation to design, assemble, test, and deploy AI agents and multi-agent orchestration workflows across your Oracle Fusion Cloud Applications. 2026 release of Oracle AI Agent Studio provides a new no-code and pro-code experience so you can author specialised agent teams to collaborate on the Fusion business objects, workflows, approvals, policies, and audit controls.

8. OpenAI Agents Platform

The 2026 agent stack comprised the Agent API, Agents SDK, Responses API, and Chat Kit. The agent’s API was a managed runtime for long-lived tasks; the agent’s SDK was an environment that enabled developers to manage tools, orchestration, handoffs, state, and guardrails within their applications. It’s why enterprise organisations focused on building customised agentic apps on top of OpenAI models: it was the perfect platform.

9. Databricks Agent Bricks

Agent Bricks and Mosaic AI Agent Framework from Databricks can help organizations build agents using the company’s enterprise data. It offers a single control plane for model, provider, and framework agents along with data governance, lineage, access controls, and cost management. This offering might be especially useful for companies with an AI strategy directly linked to their data platform.

10. Workato Agent Studio

Create enterprise Agents (Genies) with Workato Agent Studio. Workato Agent Studio is a no-code/low-code AI Agent (Genie) creation and management platform. It unifies Enterprise Applications, APIs, Workflows, MCPE Servers, Identify, approvals, observability, and governance into the Agents. The integration-first architecture enables the automation of sophisticated cross application enterprise workflows.

Choosing the Right Enterprise AI Agent Platform

The best AI agent platform for your organisation depends on the specific requirements of your organisation. For those already using their ecosystem extensively, Microsoft and Salesforce are good options. For others, AWS, Google Cloud and Databricks deliver a lot of the required infrastructure with lots of developer flexibility. For workflows focused on automation, ServiceNow, Oracle, and Workato are hard to beat, while IBM and OpenAI give a flexible platform for agent orchestration and app creation.

As AI agents grow more autonomous, companies will be able to evaluate the security, IAM, data management, human approval, observability, and auditability, model agility, integrations, and TCO of all aspects against model performance. Those that have platforms that unify autonomous execution and enterprise controls will be positioned to accelerate the automation revolution.

The post Top 10 AI Agent Platforms for Enterprises appeared first on ELE Times.

A TrueTime XL-AK GPS time server from 1995 is back at work, but with a new heart. The project replaces the original electronics with a Raspberry Pi 5 and a GNSS HAT, and the result is a stratum 1 NTP server for the local network. The enclosure, the 16×2 LCD display and the bicolour LED are still the ones from thirty years ago.

The board was purchased in June and received on 22 June. Sixteen days later, a similar GPS time server caused a 12-hour cellular service outage in Australia. An episode that shows how widespread these instruments were, and how much they still matter, even when they stop working.

The Raspberry Pi 5 and the GNSS module

The Raspberry Pi 5 runs Pi OS Lite and communicates with the u-blox NEO-M9N GNSS module through the GNSS HAT. The HAT software creates a bridge to transfer the NMEA sentences, which carry date and time, to gpsd and chrony. It also provides a PPS signal for precise timing.

You can also use a Raspberry Pi 5 with 1GB of RAM, at a cost of 44 dollars. The version used in the project has 4GB, but the difference is not in the memory: it is in clock stability and thermal management, which here matter more than anything else.

Configuring chrony and PPS

Chrony is configured to use the PPS refclock as the preferred source and the SHM refclock, which comes from gpsd, as a reference. The configuration includes an offset of 0.0 and a delay of 0.05 for the SHM. The PPS refclock is set with poll 3 and filter 16.

For maximum precision, the system was pushed on the clock parameters. Here are the main values of the chrony configuration:

• maxclockerror set to 0.5
• maxupdateskew 100.0 and makestep 1000 3
• maxchange 0.1 1 -1 to limit sudden corrections

Thermal stability is another key point. The Raspberry Pi is configured with force_turbo, which draws about 1W more continuously, and with a fan running at a constant duty cycle. The fan is set to 50% duty cycle to reduce noise, while 75% offers slightly better performance. Thermal insulation was also added.

The original LCD display and bicolour LED are driven by the Raspberry Pi to show the server status. The LED, for example, indicates the GPS status. The NTP server then provides time synchronisation services to clients on the local network through chrony.

The project was built with VCF Midwest in mind, an event dedicated to retrocomputing. The video documenting the restoration shows the whole process, from the original board to the working NTP server. Anyone who wants to redo the work will also find the GNSS HAT software and the fan control utility, included in the Time Pi repository.

Source: https://www.youtube.com/watch?v=1T9xQy-dsQo

The post A 1995 GPS Time Server Gets a Raspberry Pi 5 Heart Transplant appeared first on Open Electronics.

There are two major workloads that make up AI compute: training and inference. Training looks back. It digests a frozen body of past text, images and code, and distills it into weights. Inference looks forward. It takes those weights and, one token at a time, produces something that did not exist a moment ago.

Same model, same matrices, same multiply-accumulate at the bottom of it all. Yet the two faces ask the silicon to perform nearly opposite tasks.

Training wants arithmetic, and lots of it. Inference wants bytes delivered on time. Treating them as one market has cost the industry a decade of misplaced benchmarks.

Let’s look at each separately, then at what each requires of the processor running it.

The face that looks back: Training

Training is a loop repeated trillions of times, and every iteration has three stages:

1. Forward pass. A batch of token sequences flows through the neural network. Every layer is a large matrix-matrix multiply (GEMM): each accelerator (a single GPU such as an NVIDIA B300) processes thousands of tokens in parallel, and across the cluster a single training step covers millions. The intermediate results, the activations needed to calculate gradients later, must be kept.
2. Backward pass. The model’s predictions are compared with the true next tokens, yielding a single error score, the loss. Its gradient is then propagated back through the same layers. Each layer computes two more GEMMs: one for the gradient with respect to its input, the other for the gradient with respect to its weights. That is why the backward pass costs roughly twice the forward pass.
3. Optimizer step. Gradients from every replica of the model are averaged across the cluster, then the optimizer, typically Adaptive Moment Estimation (Adam) or a variant such as AdamW, updates every weight.

The arithmetic works out to about six 6 FLOPs per parameter per training token: two forward, four backward. Multiply by tens of billions of parameters and tens of trillions of tokens, and frontier training runs land in the range of 10²⁵ to 10²⁶ FLOPs.

Memory is the second issue. In one common mixed-precision Adam configuration, each parameter can require about 16 bytes of state: a BF16 weight and gradient (2 bytes each), an FP32 master weight (4), and two FP32 optimizer moments (4 each). A 70-billion-parameter model therefore needs about 1.1 terabyte (TB) before a single activation is stored. No single device holds that. Training is, by construction, a distributed problem.

A key feature of training is batching. Processing many tokens together lets the processor reuse model weights across a large amount of computation, raising arithmetic intensity—the number of FLOPs performed per byte moved. The large matrix operations that dominate much of training can therefore make effective use of compute throughput. Adding chips can increase training capacity and speed, but the gains depend on how quickly they exchange data and synchronize their work.

The face that looks forward: Inference

Inference omits the backward pass and the optimizer. For the main dense linear operations, a forward pass takes roughly two FLOPs per parameter per token, a third of training. That makes it sound like a lighter version of the same job. It is not. Look closer and inference has two faces of its own.

Prefill processes the prompt. All input tokens are known in advance, so they move through the network in parallel, as GEMMs. A sufficiently large prompt or batch can make its matrix operations compute intensive, making prefill resemble a forward training pass: compute-bound, high arithmetic intensity. Along the way, the model writes the keys and values of every token, in every layer, into the key-value (KV) cache that later tokens will use for attention. Prefill strongly affects time to first token.

Decode generates the answer, one token at a time. Each new token cannot be selected until the preceding step is complete, so there is nothing to parallelize along the sequence. Every layer collapses into a matrix-vector multiply (GEMV), reusing weights across relatively little work. To produce one token, the processor must stream all the weights and the entire KV cache for that sequence out of memory and start over.

Weight and cache traffic then dominate the time spent generating each token.

That is the crux. A current flagship accelerator can perform several hundred FLOPs in the time it moves one byte from high-bandwidth memory (HBM). Decode at small batch sizes supplies only one or two FLOPs per byte: each weight is fetched, used in a single multiply-add, and discarded. Meanwhile, the compute units are idle, waiting on memory.

Decode is memory-bandwidth bound, and in agentic workloads with long outputs, decode can reach around 90% of wall-clock time. At larger batches, weight reuse improves and the balance can shift, though not for the KV cache, which each sequence reads in full. Long generated answers can make decode dominate a request’s end-to-end time, but the share depends on prompt length, output length, batch size, and serving system. See block diagram below.

In a large language model (LLM) inference workflow, prefill processes the prompt in parallel and writes the KV cache in one pass; decode generates one token at a time, reading the full cache on every step. The time split is illustrative. Source: VSORA

The KV cache adds another constraint as context grows. In each layer, every cached token contributes a key and a value for each KV head. Assuming the full context remains resident at a fixed precision, the cache size per sequence is:

KV bytes = 2 x L x Hkv x dhead x S x b

Whereas L represents layers, H_kv key-value heads, d_head head dimension, S sequence length, and b bytes per element. For a Llama-3-70B-class model (80 layers, 8 KV heads, head dimension 128, BF16) that is about 320 KB per token.

At a 128k-token context, one conversation holds roughly 42 GB of cache, more than half a model’s worth of weights at FP8, for a single user.

Three workloads, side by side

Prefill sits closer to training than to decode. The real divide runs between batched, parallel math and sequential, memory-starved math, as shown in the table below.

What training asks of the silicon

A training processor is judged by how much of its rated arithmetic it turns into useful work across an entire cluster. Five pressures shape it:

1. Dense matrix throughput. Tensor or systolic arrays sized for large GEMMs fed from on-chip SRAM with enough reuse to stay busy. This is the ground where peak TFLOPS on the datasheet actually mean something.
2. Memory capacity, not only bandwidth. Weights, gradients, optimizer states, and activations must sit close to the compute. HBM stacks per package keep growing for this reason, and activation recomputation trades FLOPs for bytes when they don’t fit.
3. Every step ends with a gradient all-reduce, and tensor or pipeline parallelism adds traffic inside each layer. Scale-up links (NVLink-class) and scale-out fabrics (InfiniBand or Ethernet) often decide utilization more than the cores do. A cluster that spends 40% of each step waiting on collectives has thrown away 40% of its silicon.
4. Gradients span a huge dynamic range. BF16 won because it keeps FP32’s 8-bit exponent; FP16 needed loss scaling to avoid underflow. FP8 training works, but only with per-tensor or per-block scaling and a high-precision master copy of the weights.
5. Reliability at scale. A run on tens of thousands of chips for weeks will see failures. So, checkpointing, fast restart, and silent-data-corruption detection become architectural features, not operational afterthoughts.

Training has no user waiting for the next token, but time still matters: a stalled step delays the entire run. Sustained throughput, utilization, and time to completion are the measures that count.

What inference asks of the silicon

An inference processor is judged by cost and energy per token delivered within a latency target. That changes the priorities almost completely.

1. Bandwidth per FLOP. Decode throughput is set by how fast weights and KV cache reach the arithmetic units. A chip with half the TFLOPS and twice the effective bandwidth can win outright. This is the memory wall, and it’s where rated peak and sustained performance part ways.
2. KV cache capacity and management. The cache, not the model, becomes the binding constraint on how many users a chip serves at long context. Paging, compression, quantizing the cache itself, and offloading to cheaper tiers are now first-order design problems.
3. The batching dilemma. Batching many users together restores arithmetic intensity, because weights are fetched once and reused across requests. But every user in the batch waits for the slowest step. Operators trade throughput against per-user latency, and the hardware must make that trade cheap: fine-grained scheduling, continuous batching, and fast context switches.
4. Aggressive precision. Inference tolerates far lower precision than training. FP8 is routine, FP4 and INT4 weights are increasingly common, and each halving of bits nearly doubles effective bandwidth. The processor must execute these formats natively, with scaling factors handled in hardware.
5. Energy and TCO. Training is a capital expense paid once per model. Inference is an operating expense paid on every token, for the life of the product. Watts per token, not peak watts, determine which company makes money.
6. Utilization and predictability. Request lengths vary wildly, and traffic is bursty. Deterministic, well-scheduled architectures keep the pipeline full; architectures tuned for large uniform GEMMs spend much of decode underused.

Prefill complicates the picture: it’s compute-bound, like training, and it sets time to first token. A good inference chip must handle both regimes, even if decode dominates the bill.

Can one chip wear both faces?

The GPU’s answer has been yes. It’s a superb training engine, and its software ecosystem made it the default for inference too. But a die sized for training GEMMs carries a large compute budget that decode cannot use. At batch sizes that keep latency acceptable, much of that silicon sits idle while HBM does the real work. You Engineers pay for both faces and use one.

The industry is responding on three fronts:

1. Specialized inference silicon. Designs that raise bandwidth per FLOP by putting far more memory close to compute: SRAM-heavy dataflow chips, wafer-scale parts, multi-tier memory hierarchies, and architectures built around sustained rather than peak efficiency. Each trades differently between capacity and bandwidth, and each hits a different cliff when models or contexts outgrow their fast memory.
2. Disaggregated serving. Split prefill and decode onto different pools of hardware, each sized for its own bottleneck, and ship the KV cache between them. This admits openly that inference itself is two workloads.
3. Software that closes the gap. Speculative decoding, which lets a small model draft tokens that the big one verifies in a single batched pass, turns part of decode back into prefill-like math. Quantization and cache compression shrink the bytes to move.

None of this makes the GPU obsolete for training. It does end the assumption that the best training chip is automatically the best inference chip.

Choosing which face to serve

For 10 years, AI hardware was built for the face that looks back. Training was where the prestige was, and peak TFLOPS was the number on the slide. That made sense when models were trained often and served rarely.

The ratio has flipped. A frontier model is trained once and then queried billions of times, increasingly by agents that read long contexts and think out loud before answering. The economics of AI now live in the forward-looking face, and that face is starved for bytes, not FLOPs.

The challenge for processor architects is to deliver tokens economically within a latency target while still handling the bursts of parallel computation that begin each request.

Lauro Rizzatti is a business development executive with VSORA, a technology company offering silicon semiconductor solutions that redefine performance. He is a noted chip design verification consultant and industry expert on hardware emulation.

Related Content

• Chiplets Are The New Baseline for AI Inference Chips
• The next AI frontier: AI inference for less than $0.002 per query
• Purpose-built AI inference architecture: Reengineering compute design
• As AI Moves from Training to Inference, Optics Moves Closer to the Chip
• The truth about AI inference costs: Why cost-per-token isn’t what it seems

The post Training and inference: Two faces of AI compute appeared first on EDN.

Gallium nitride (GaN) power IC and silicon carbide (SiC) technology firm Navitas Semiconductor Corp of Torrance, CA, USA has completed its acquisition (announced on 25 August) of power management solutions company Claros Inc — which is developing integrated voltage regulator (IVR) technology for next-generation AI data centers — providing the last step to powering the xPU...

🎥 Всеукраїнський круглий стіл «Штучний інтелект як об’єкт судово-експертного дослідження: проблемні питання та шляхи їх вирішення» kpi ср, 10/07/2026 - 11:55

Qorvo Inc of Greensboro, NC, USA (which provides core technologies and RF solutions for mobile, infrastructure and defense applications) has announced a C-band radar solution that adds receiver frequency agility and reduces DC power and heat in the transmit chain. Designed for pulsed ESA (electronically scanned array) systems, the solution combines what is reckoned to be the industry’s first integrated C-band bulk acoustic wave (BAW)-switched filter bank with high-efficiency 50W and 200W gallium nitride GaN power amplifiers (PAs)...

Seeed Studio has introduced two new XIAO Plus development boards, the XIAO SAMD21 Plus and the XIAO RP2040 Plus, which address the main trade-off of the XIAO boards: the limited number of pins. The new versions offer up to 30 GPIO pins, compared to the 14 on the originals, while keeping the same 21 × 17.8 mm footprint. In addition, they integrate a PMIC for Li-ion battery management, making them suitable for advanced embedded projects and battery-powered devices.

Additional pins via SMD castellated pads

The XIAO Plus boards keep the dimensions and the 2.54 mm pin header layout of the other XIAO boards. The additional connections are exposed through SMD castellated pads with a 1.27 mm pitch on the back. This design allows the board to be soldered directly onto a custom PCB, like a true System-on-Module. So, anyone designing a compact device can use the full computing power without taking up extra space.

The XIAO SAMD21 Plus has 30 GPIO pins, including 27 digital pins, 11 analog inputs, two I2C interfaces, UART, SPI, I2S and a DAC. The XIAO RP2040 Plus has 29 GPIO pins, with 26 digital pins, four analog inputs, two I2C interfaces, UART, SPI and up to 26 PWM outputs. Both double the capabilities of the previous versions, which stopped at 14 pins, without increasing the board size.

PMIC and Li-ion battery management

Both boards include a PMIC that allows a Li-ion battery to be connected directly for integrated charging and protection against current backflow. The XIAO RP2040 Plus adds a battery monitoring circuit that can be enabled via software through GPIO24, to measure the voltage through the ADC on GPIO29. This feature is designed for those developing portable devices who want to know the state of charge in real time.

The XIAO SAMD21 Plus, on the other hand, adds a programmable WS2812 RGB LED and dedicated Reset and Boot buttons. These elements make debugging and programming easier without having to solder additional pins. Support for multiple development environments, including Arduino, MicroPython, CircuitPython, TinyGo, Rust and Zephyr, makes the boards flexible for different levels of experience.

Prices and compatibility with existing projects

The new boards cost $5.90 for the XIAO SAMD21 Plus and $4.90 for the XIAO RP2040 Plus, respectively. Despite the increase in pins, the footprint remains identical to the other XIAO boards, so existing projects can be upgraded without mechanical changes. For those starting from scratch, the maker’s website offers guides and ideas on how to get the most out of these boards.

These boards are particularly useful for those who want to move from breadboard prototyping to small-batch production. The SMD castellated pads allow the board to be soldered as a module onto a custom PCB, reducing development time. Furthermore, the presence of the PMIC eliminates the need for external charging modules, simplifying the overall design.

For those looking for a board with more pins and integrated battery management, the XIAO Plus boards represent a compact and economical solution. The maker’s website collects examples and documentation to get started right away.

Source: https://www.seeedstudio.com/Seeed-Studio-XIAO-RP2040-Plus-p-6932.html

The post XIAO Plus: More Pins Without Changing the Footprint appeared first on Open Electronics.

Qorvo Inc of Greensboro, NC, USA (which provides core technologies and RF solutions for mobile, infrastructure and defense applications) has announced an X-band RF front-end solution that combines high transmit output with low-noise, high-linearity receive performance for active electronically scanned array (AESA) radar. Developed around a quad architecture, the solution reduces RF content inside the array lattice...

Infineon Technologies AG has introduced the TRAVEOTM CYT4EN, a new microcontroller (MCU) for cost-effective high-performance instrument clusters and display applications in the automotive industry, including two-wheelers. The automotive cluster MCU is designed to leverage external LPDDR4 memory, resulting in capabilities that traditionally required more complex SoC (System-on-chip)-based platforms: The device supports advanced 2.5D graphics and 3D scene rendering, drives high-resolution displays up to Full HD, and can power two displays simultaneously. At the same time, it reduces system complexity and the bill of materials compared to SoC-based platforms.

“Cutting-edge cluster and display solutions are playing a central role for the user experience in connected and software-defined vehicles,” said Thomas Boehm, Senior Vice President Automotive Microcontrollers at Infineon. “With TRAVEO T2G CYT4EN, we are helping our customers bring them to market more quickly, efficiently and cost-effectively. By combining the simplicity, safety, and fast responsiveness of an MCU architecture with the high-bandwidth memory required for modern cockpit graphics, we are enabling a new generation of vehicle displays.”

While developing CYT4EN, Infineon collaborated closely with Micron to optimize the memory subsystem for the use of LPDDR4 memory to support advanced graphic capabilities while maintaining overall system efficiency.

“Micron’s automotive LPDDR4 memory provides a proven combination of bandwidth, reliability, and functional safety features for cost-optimized cockpit platforms,” said Amanda Henderson, Director of Ecosystem Enablement at Micron. “For vehicle programs where affordability, longevity, and functional safety are key requirements, LPDDR4 remains an effective solution for delivering modern display experiences.”

Built on the proven TRAVEO T2G architecture, the CYT4EN combines high-performance processing, advanced graphics, and automotive-grade safety and security in a highly integrated device. It includes features such as on-the-fly rendering and hardware-accelerated decompression to enable a rich graphical user experience. The device delivers deterministic boot times below 150 milliseconds that are significantly shorter than the multi-second initialization common to complex SoC platforms. It supports functional safety up to ASIL-B according to ISO 26262 and was developed in accordance with ISO 21434 for automotive cybersecurity. In addition, an independent voltage domain keeps central system functions such as communication and basic processing active in low-power modes, improving system efficiency and robustness.

The high level of integration enables cost-effective smart cockpit designs without complex system implementations. For example, CYT4EN allows designs without additional microcontrollers for system management and in-vehicle network communication, enables simplified PCB layouts with as few as six layers, and avoids the need for active cooling thanks to optimized power efficiency.

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Keysight Technologies has collaborated with the University of Glasgow, the National Physical Laboratory (NPL), and MPI Corporation to develop a new approach to broadband characterization of next-generation sub-terahertz (sub-THz) semiconductor devices. Together, the organizations demonstrated continuous on-wafer characterization of indium phosphide high-electron-mobility transistors (InP HEMTs) from near DC to 250 GHz in a single sweep, simplifying broadband measurements for advanced semiconductor research and design.

As semiconductor technologies move into millimeter-wave and sub-terahertz frequencies for next-generation applications, engineers need to accurately characterize transistor performance across increasingly broad frequency ranges. Conventional approaches can require multiple measurement setups and calibrations, adding complexity and making it more difficult to obtain consistent data for broadband device modeling.

The four organizations combined Keysight instrumentation, University of Glasgow semiconductor devices, MPI Corporation on wafer probing technology, and NPL metrology expertise to create the broadband measurement solution. The setup brought together:

• Keysight’s PNA-X Vector Network Analyzer
• Keysight’s Single-Sweep 250 GHz Frequency Extender
• Keysight’s Precision Source/Measure Unit (SMU)
• University of Glasgow’s InP HEMT devices and on-wafer calibration standards
• MPI Corporation’s broadband on-wafer probing technology and calibration software
• NPL’s high-frequency metrology and calibration methodologies

Together, these technologies enabled continuous measurement from near DC to 250 GHz with a single probe touchdown, eliminating the need for multiple setup changes and providing consistent broadband S-parameter measurements. Built-in source filtering and broadband source power calibration also helped ensure signal purity of the applied millimeter-wave signal at the probe-tip.

Thierry Locquette, VP of Sales, Europe, Middle East & Africa at Keysight said: “Characterizing devices continuously from near DC to 250 GHz in a single sweep can significantly simplify the measurement process for researchers developing next generation semiconductor technologies. By bringing together expertise in instrumentation, devices, probing, and metrology, this collaboration demonstrates a practical approach to generating the consistent broadband data engineers need to accelerate device development.”

Dr Xiaobang Shang, Principal Scientist and On-wafer Measurement Lead at NPL, said: “Accurate on-wafer measurement is essential for developing reliable semiconductor devices, particularly as technologies move further into the millimetre-wave and sub-terahertz frequency ranges. We were pleased to contribute NPL’s high-frequency on-wafer metrology and calibration expertise to this collaboration, helping demonstrate a practical route to consistent broadband device measurements using the state-of-the-art single sweep system.”

Matthew White, Director of Business Development at MPI Corporation, said: “Extending on-wafer characterization to 250 GHz requires the probing, calibration, and measurement platform operating as one seamlessly integrated system. This collaboration demonstrates a practical approach to achieving consistent broadband measurements from near DC to 250 GHz with a single probe touchdown, helping researchers simplify characterization and accelerate device development with great confidence.”

The post Keysight and Research Institutions Simplify Testing of Next- Generation Semiconductor Devices appeared first on ELE Times.

Infineon Technologies today announced the completion of its acquisition of C2i Semiconductors, a Bengaluru-based technology company specialising in software-defined multiphase controllers and smart power stages for AI data centre applications. C2i Semiconductors’ technology complements Infineon’s leading portfolio of power semiconductors and power systems, enabling intelligent and scalable power delivery architectures from grid to core for AI servers and high-performance computing platforms. The acquisition further strengthens Infineon’s leadership in power solutions for AI data centres, expands its engineering capabilities in India and reinforces the country’s role as a strategic innovation hub. With the completion of the transaction, the C2i Semiconductors team becomes part of Infineon’s Power Systems division.

“Completing this acquisition marks an important milestone for our AI power business and our innovation activities in India,” said Adam White, President of Infineon’s Power Systems division. “C2i Semiconductors brings exceptional expertise in software-defined power management and system-level power architectures, backed by a highly experienced engineering team. By combining these capabilities with Infineon’s semiconductor technologies, application know-how, manufacturing capabilities and global customer reach, we will accelerate innovation in power delivery solutions for AI data centres and create significant value for our customers. I am delighted to welcome the C2i team to Infineon.”

Software-defined power solutions combine advanced power semiconductors with intelligent digital control and software algorithms to optimise power conversion, regulation and system performance in real time. As increasingly powerful AI processors create highly dynamic and rapidly changing power demands, power delivery systems must respond faster and more precisely to sudden load fluctuations while maintaining efficiency and system stability. By adding intelligence to the power delivery architecture, software-defined solutions can help improve efficiency, reduce power losses and support the increasing power density requirements of next-generation AI processors.

The acquisition combines C2i Semiconductors’ digital power expertise with Infineon’s global scale, application know-how and broad portfolio of power semiconductors, including silicon, silicon carbide (SiC) and gallium nitride (GaN) technologies, as well as vertical power delivery solutions. Together, the teams will accelerate the development of more intelligent, efficient and scalable power delivery solutions for AI infrastructure, including future Substrate Integrated Voltage Regulators (SIVR).

C2i Semiconductors adds expertise in software-defined power management, multiphase controllers, smart power stages, digital control technologies and system-level power architectures. The combination strengthens Infineon’s capabilities across the entire power path from grid to core and supports the development of next-generation power solutions for AI servers and high-performance computing platforms.

The acquisition also adds highly specialised engineering expertise to Infineon’s global R&D network and further strengthens its innovation capabilities in India. The combined team will contribute to reinforcing Bengaluru’s role as an important innovation location for digital power technologies and to accelerating the development of next-generation power solutions for AI infrastructure. Infineon currently employs approximately 2,800 people across multiple locations in India.

The post Infineon completes acquisition of C2i Semiconductors to expand innovation capabilities in AI data centre power management solutions appeared first on ELE Times.

submitted by /u/GooberMcNutly [link] [comments]

Skyworks Solutions Inc of Irvine, CA, USA has announced the completion of its combination with Qorvo Inc of Greensboro, NC, USA, creating a US-based provider of high-performance radio frequency (RF), power management, and analog and mixed-signal semiconductor solutions...

Професорів КПІ ім. Ігоря Сікорського відзначено державними нагородами з нагоди Дня працівників освіти kpi вт, 10/06/2026 - 22:31

Renesas Electronics Corp of Tokyo, Japan has expanded its gallium nitride (GaN) portfolio into low-voltage applications with its first family of 100V enhancement-mode (E-mode) GaN-based discrete power transistors. The RTP100E005G1FL, RTP100E2P6G1FL, RTP100E1P8G1FL-DSC and RTP100E1P2G1FL-DSC low-voltage GaN FETs are said to deliver ultra-fast switching speeds and enhanced thermal performance in efficiency-critical, high-power-density applications, including AI data centers, humanoid robotics, factory automation and industrial motor drives, power tools and solar micro-inverters...

A portable square wave generator covering from 2 Hz to about 33.5 MHz, with adjustment steps of 2 Hz. The heart of the project is an AVR16EB28 microcontroller, which handles both signal generation and the user interface. Power is supplied by a LiPo battery, while an OLED display, rotary encoder, and push-button keypad provide full control. The project is by David Johnson-Davies, known for his experiments with AVR microcontrollers.

The frequency is set with precision, and the reading appears on the OLED display. The rotary encoder allows rapid variations, while the keypad is used to enter exact values. The whole thing fits in a compact enclosure, suitable for the workbench or the field. The 2 Hz resolution across the entire range is remarkable, and makes the device useful for testing audio circuits, filters, and timing.

Circuit and control with AVR16EB28

The schematic is simple: the AVR16EB28 microcontroller generates the square wave directly from a pin, with the frequency calculated in software. Control is via an OLED display, rotary encoder, and push-button keypad. The LiPo battery powers the whole system, with a regulator for a stable voltage. The project is designed to be replicated with easily available components.

The firmware handles the 2 Hz steps and updates the display in real time. In addition, the rotary encoder allows scrolling through frequencies smoothly, while the keypad allows direct entry of a value. The code is available on the maker’s website, and includes libraries for the display and encoder. The result is a stable and repeatable device.

Construction, power, and practical use

Construction requires a PCB, which can be made with a milling machine or through an external service. Assembly is within reach of those with SMD soldering experience, since the microcontroller is in a surface-mount package. The LiPo battery connects on the back, and the front panel hosts the display, encoder, and keypad. The whole thing is compact and easily portable.

For power, a 3.7 V LiPo battery is sufficient, with a voltage regulator for the 3.3 V of the microcontroller. Consumption is low, thanks to the OLED display and efficient sleep management. Practical use is immediate: turn it on, select the frequency, and connect the output to the circuit under test. The precision of the 2 Hz steps makes it suitable even for fine adjustments.

David Johnson-Davies’s website hosts the source code and construction details. Those who want to go deeper can consult the complete documentation, including schematics and assembly photos. The project demonstrates how a modern AVR microcontroller can generate high-frequency signals with precision, without complex external components. An elegant solution for those seeking a reliable square wave generator.

In summary, this square wave generator offers a wide range and fine resolution, all in a portable format. The choice of an AVR16EB28 ensures programming simplicity and low cost. The OLED display and manual controls make it intuitive to use, even for those unfamiliar with professional instruments. A project worth replicating.

Source: http://www.technoblogy.com/show?5QE2

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