Feed aggregator

In industrial applications using digital-to-analog converters (DACs), programmable logic controllers (PLCs) set an analog output voltage to control actuators, motors, and valves. PLCs can also regulate manufacturing parameters such as temperature, pressure, and flow.

In these environments, the DAC output may require overvoltage protection from accidental shorts to higher-voltage power supplies and other sustained high-voltage miswired connections. You can protect precision DAC outputs in two different ways, depending on whether the DAC output buffer has an external feedback pin.

Overvoltage damage

There are two potential consequences should an accidental sustained overvoltage event occur at the DAC output.

First, if the DAC output can drive an unsustainable current limit, then damage may occur as the output buffer drives an excess of current. This current limit may also occur if the output voltage is shorted to ground or to another voltage within the supply range of the DAC.

Second, electrostatic discharge (ESD) diodes latched to the supply and ground can source and sink current during sustained overvoltage events, as shown in Figure 1 and Figure 2. In many DACs, a pair of internal ESD diodes that shunt any momentary ESD current away from the device can help protect the output pin. In Figure 1, a large positive voltage causes an overvoltage event in the output and forward-biases the positive AVDD ESD diode. The VOUT pin sinks current from the overvoltage event into the positive supply.

Figure 1 Current is shunted to positive supply during a positive overvoltage event. Source: Texas Instruments

In Figure 2, the negative overvoltage sources current from the negative supply through the AVSS ESD diode to VOUT.

Figure 2 Current is shunted to positive supply during a negative overvoltage event. Source: Texas Instruments

In Figure 1 and Figure 2, internal ESD diodes are not designed to sink or source current associated with a sustained overvoltage event, which will typically damage the ESD diodes and voltage output. Any protection should limit this current during an overvoltage event.

Overvoltage protection

While two basic components will protect precision DAC outputs from an overvoltage event, the protection topology for the DAC depends on the internal or external feedback connection for the DAC output buffer.

If the DAC output does not have an external voltage feedback pin, you can set up protection as a basic buffer using an operational amplifier (op amp) and a current protection device at its output. If the DAC has an external voltage feedback pin, then you would place the current protection device at the output of the DAC, with the op amp driving the feedback sense pin.

Let’s explore both topologies.

Figure 3 shows protection for a DAC without a feedback sense pin, with the op amp set up as a unity gain buffer. Inside the op amp feedback, an eFuse opens the circuit if the op amp output current exceeds a set level.

Figure 3 Output protection for a DAC works without a feedback pin. Source: Texas Instruments

Again, if the output terminal voltage is within the supplies of the op amp, the output current comes from the short-circuit current limit. An output terminal set beyond the supplies of the op amp, as in a positive or negative overvoltage, will cause the supply rails to source or sink additional current, as previously shown in Figure 1 and Figure 2.

Because the output terminal connects to the op amp’s negative input, the op amp input must have some sort of overvoltage protection. For this protection circuit, an op amp with internal overvoltage protection that extends far beyond the op amp supply voltage is selected. When using a different op amp, series resistance that limits the input current can help protect the inputs.

The circuit shown in Figure 3 will also work for a precision DAC with a feedback sense pin. The DAC feedback sense pin would simply connect to the DAC VOUT pin, using the same protection buffer circuit. If you want to use the DAC feedback to reduce errors from long output and feedback sense wire resistances, you need to use a different topology for the protection circuit.

If the DAC has an external feedback sense pin, changing the protection preserves the sense connection. In Figure 4, the eFuse connects directly to the DAC output. The eFuse opens if the DAC output current exceeds a set level. Here, the op amp acts as a unity gain buffer to drive the DAC sense feedback pin.

Figure 4 This output protection for a DAC works with a feedback pin. Source: Texas Instruments

In both topologies, shown in Figure 3 and Figure 4, the two protection devices have the same requirements. For the eFuse, the break current must be lower than the current level that might damage the device it’s protecting. For the op amp, input protection is required, as the output overvoltage may significantly exceed the rail voltage. In operation, the offset voltage must be lower than the intended error, and the bandwidth must be high enough to satisfy the system requirements.

Overvoltage protection component selection

To help you select the required components, here are the system requirements for operation and protection:

• Supply range: ±15 V
• Sustained overvoltage protection: ±32 V
• Current at sustained overvoltage: approximately 30 mA
• Output protection should introduce as little error as possible, based on offset or bandwidth

The primary criteria for op amp selection were overvoltage protection of the inputs. For instance, the super-beta inputs of the OPA206 precision op amp have an integrated input overvoltage protection that extends up to ±40 V beyond the op amp supply voltage. Figure 5 shows the input bias current relative to the input common-mode voltage powering OPA206 with ±15 V supplies. Within the ±32 V range of overvoltage protection, the input bias current stays below ±5 mA of input current.

Figure 5 Input bias current for the OPA206 is shown versus the input common-mode voltage. Source: Texas Instruments

The OPA206 offset voltage is very low (typically ±4 µV at 25°C and ±55 µV from –40°C to 125°C) and the buffer contributes little error to the DAC output. When using a different op amp without integrated input overvoltage protection, adding series resistance at the inputs will limit the input current.

The TPS2661 eFuse was originally intended as a current-loop protector with input and output miswiring protection. If its output voltage exceeds the rail supplies, TPS2661 detects miswiring and cuts off the current path, restoring the current path when the output overvoltage returns below the supply.

If the output current exceeds TPS2661’s 32-mA current-limit protection, the device breaks the connection and retests the current path for 100 ms periodically every 800 ms. The equivalent resistance of the device is a maximum 12.5 Ω, which enables a high-current transmission output without large voltage headroom and footroom loss at the output.

Beyond the op amp and eFuse protection, applying an optional transient voltage suppression (TVS) diode will provide additional surge protection as long as the chosen breakdown voltage is higher than any sustained overvoltage. If the breakdown voltage is less than the sustained overvoltage, then an overvoltage can damage the TVS diode. In this circuit, the expected sustained overvoltage is ±32 V, with an optional TVS3301 device that has a bidirectional 33-V breakdown for surge protection.

Another TVS3301 added to the ±15-V supplies is an additional option. An overvoltage on the terminal will direct any fault current into the power supplies. If the supply cannot sink the current or is not fast enough to respond to the overvoltage, then the TVS diode absorbs excess current as the overvoltage occurs.

Constructed circuit: Precision DAC without a feedback sense pin

You can build and test the overvoltage protection buffer from Figure 3 with the DAC81416-08 evaluation module (EVM). This multichannel DAC doesn’t have an external feedback sense pin. Figure 6 shows the constructed protection buffer tested on one of the DAC channels.

Figure 6 The constructed overvoltage protection circuit employs the DAC81416-08 evaluation module. Source: Texas Instruments

Ramping the output of DAC from –10 V to 10 V drives the buffer input. Figure 7 shows that the measured offset of the buffer is less than 10 µV over the full range.

Figure 7 Protection buffer output offset error is shown versus buffer input voltage. Source: Texas Instruments

Connecting the output to a variable supply tests the output overvoltage connection, driving the output voltage and then recording the current at the output. The measurement starts at –32 V, increases to +32 V, then changes back from +32 V down to –32 V. Figure 8 shows the output current set to overvoltage and its recovery from overvoltage.

Figure 8 Protection buffer output current is shown versus buffer output overvoltage. Source: Texas Instruments

The measurements show hysteresis in both the positive and negative overvoltage of the protection buffer that comes from extra voltage across the series resistor at the output of the TPS26611. During normal operation (without an overvoltage), the TPS26611 current path turns off when the output rises and is driven above 17.2 V, at which point the remaining output current comes from the overvoltage of the OPA206 input. As the output voltage decreases, the TPS26611 current path conducts current again when the output drops below 15 V.

When driving the output to a negative overvoltage, the current path turns off at –17.5 V and turns on again when the output returns above –15 V.

Constructed circuit: Protection for a DAC with output feedback

Like the previous circuit, you can test the overvoltage protection from Figure 4. This test attaches an overvoltage protection buffer to the output of a DAC with an external feedback sense pin. The DAC8760 EVM tests for an output overvoltage event. As shown in Figure 9, a 1-kΩ resistor placed between VOUT and +VSENSE prevents the output buffer feedback loop of the DAC from breaking if the feedback sense signal is cut.

Figure 9 This constructed overvoltage protection circuit is used with the DAC8760 evaluation module. Source: Texas Instruments

Ramping the output of the DAC from –10 V to +10 V drives the feedback buffer input. Shown in Figure 10, the offset of the feedback to +VSENSE is again <10 μV over the full range.

Figure 10 Feedback buffer offset error is shown versus buffer input voltage. Source: Texas Instruments

The DAC is again set to 0 V, with the output connected to a variable supply to check the output current against output overvoltage. Figure 11 shows the output current as the output voltage increases from –32 V to +32 V and decreases to –32 V.

Figure 11 Protection buffer output current is shown versus buffer output overvoltage. Source: Texas Instruments

As before, there is current path hysteresis. The TPS26611 current path shuts off when the output goes above 16.5 V and turns on when the output returns to about 15 V. For the negative overvoltage, the current path turns off when the output is below –16.8 V and turns on again when the output returns above –15 V.

Two overvoltage protection topologies

Industrial control applications for analog outputs require specialized protection from harsh conditions. This article presented two topologies for precision DAC protection against sustained overvoltage events:

• DAC without external feedback: Protecting the output from an overvoltage by using an op amp buffer with an eFuse in the op amp output.
• DAC with external feedback: Protecting the output from overvoltage by using an eFuse to limit the DAC output current and with an op amp acting as a unity gain buffer for sense feedback.

In both cases, the tested circuits show a limited offset error (<10 µV) through the range of operation (±10-V output) and protection from sustained overvoltage of ±32 V.

Joseph Wu is applications engineer for digital-to-analog converters (DACs) at Texas Instruments.

 

 

Art Kay is applications engineer for precision signal conditioning products at Texas Instruments.

 

 

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The post Protecting precision DACs against industrial overvoltage events appeared first on EDN.

now granted falstad probably isn't the best sim around, but for a free one its really easy to use and intuitive. I am shopping around for good sims though so if yall have any suggestions on better sims that match falsteds simulation im open ears. submitted by /u/Lagfoundry [link] [comments]

GlobalFoundries of Malta, NY (GF, the only US-based pure-play foundry with a global manufacturing footprint, including facilities in the USA, Europe and Singapore) has entered into a technology licensing agreement with Taiwan Semiconductor Manufacturing Company Ltd (TSMC) for 650V and 80V gallium nitride (GaN) technology. The strategic move will accelerate GF’s next generation of GaN products for data-center, industrial and automotive power applications and provide US-based GaN capacity for a global customer base...

Specialty semiconductor and performance materials producer 5N Plus Inc (5N+) of Montréal, Québec, Canada has been included in the MSCI Canada Small Cap Index, effective as of the close of trading on 24 November...

BluGlass Ltd of Silverwater, Australia — which develops and manufactures gallium nitride (GaN) blue laser diodes based on its proprietary low-temperature, low-hydrogen remote-plasma chemical vapor deposition (RPCVD) technology — has appointed non-executive director Omer Granit as executive chair to lead a refreshed board during the next phase of commercial growth for the company...

When you're prototyping but the SOIC package IC you ordered is in actuality apparently a "wide body SOIC" Got to get creative fitting it onto a SOIC-2-DIP converter! If it works, it works! submitted by /u/Peter-Langton [link] [comments]

Earlier this summer, I detailed my travails struggling with (and ultimately recovering from) buggy firmware updates I’d been “pushed” on my combo of EcoFlow’s DELTA 2 portable power station and its Smart Extra Battery supplemental capacity companion:

Toward the end of that earlier writeup, I mentioned that I’d subsequently been offered a further firmware update, which (for, I think, understandable reasons) I was going to hold off on tackling for a while, until I saw whether other, braver souls had encountered issues of their own with it:

DELTA 2 firmware update success(es)

In late August, I eventually decided to take the upgrade plunge, after enduring the latest in an occasional but enduring series of connectivity glitches. Although I could still communicate with the device “stack” via Bluetooth, its Wi-Fi connection had dropped and needed to be reinstated within the app. The firmware update’s documentation indicated it’d deal with this issue:

The upgrade attempt was thankfully successful this time, although candidly, I can’t say that the Wi-Fi connectivity is noticeably more robust now than it had been previously:

I was then immediately offered another firmware upgrade, which I’d heard on Facebook’s “EcoFlow Official Club“ group had just been released. Tempting fate, I plunged ahead again:

Thankfully, this one completed uneventfully as well:

As did another offered to me in early September (gotta love that descriptive “Fixes some known issues” phrasing, eh? I’m being sarcastic, if it wasn’t already obvious…):

There have been no more firmware upgrades in the subsequent ~1.5 months. More generally, since the DELTA 2 line is mature and EcoFlow has moved on to the DELTA 3 series, I’m hopeful for ongoing software stability (accompanied by no more functional misbehavior) at this point.

Initial impressions of DELTA 3 devices

Speaking of which, what about the DELTA 3 Plus and its accompanying Smart Extra Battery, mentioned at the end of my earlier write-up, which EcoFlow support had sent as replacements for the DELTA 2-generation predecessors prior to my successful resurrection of them?

Here again is what the new DELTA 3 stack (left) looks like next to its DELTA 2 precursors (right):

The stored-charge capacity of the DELTA 2 is 1024Wh, which matches that of the DELTA 3 Plus. I’d mentioned in my earlier DELTA 2 coverage that the DELTA 3 Plus was based on newer,  denser (but still LiFePO₄ aka LFP) 40135 batteries. Why then do the two portable power stations have nearly the same sizes? The answer, of course, is that there’s more than just batteries inside ‘em:

The (presumed) varying battery generation-induced size differential is much more evident with the two generations of Smart Extra Batteries…which are (essentially) just batteries.

Despite their 1,024-Wh capacity commonality, the DELTA 3 version (again on top of the stack at left in the earlier photo) has dimensions of 15.7 x 8 x 7.8 in (398 x 200 x 198 mm) and weighs 21.1 lbs. (9.6 kg).

Its DELTA 2-generation predecessor at top right weighs essentially the same (21 lbs./9.5 kg), and it’s nearly 50% taller (15.7 × 8.3 × 11.1 in./40 × 21.1 × 28.1 cm).

By the way, back when I was fearing that the base DELTA 2 unit was “toast” but hoping that its Smart Extra Battery might still be saved, I confirmed EcoFlow’s claim that the DELTA 3 Plus worked not only with multiple capacity variants of the DELTA 3-generation Smart Extra Battery, for capacity expansion up to 5 KWh, but also with my prior-generation storage capacity expansion solution:

Charging (and other) enhancements

Aside from the height-therefore-volume differential, the most visually obvious other difference between the two portable power stations is the relocation of AC power outlets to the front panel in the DELTA 3 Plus case. Other generational improvements include:

• Faster sub-10-ms switchover from wall outlet-sourced to inverter-generated AC for more robust (albeit not comprehensive…no integrated surge protection support, for example) UPS functional emulation
• Improved airflow, leading to claimed 30-dB noise levels in normal operation
• A newer-generation battery-induced boosted recharge cycle count to 4,000
• Inverter-generated AC output power up to 3600 W (X-Boost surge)
• Higher power, albeit fewer, USB-A ports (two, each 36 W, compared to two 12 W and two 18 W)
• Higher power USB-C ports (two, each 140 W, versus two 100 W)
• And faster charging (sub-1-hour to 100%), enabled by factors such as:
  • AC input power up to 1500 W
  • Solar input power up to 1000 W (two 500-W-max XT60i connectors) with maximum power point tracking (MPPT) support
  • And simultaneous multi-charging capabilities from solar and AC when both are available, prioritizing the former to save money.

Speaking of solar, I haven’t forgotten about the two 220W panels:

And a more recently acquired 400W one:

For which I’m admittedly belated in translating testing aspiration into reality. The issue at the moment isn’t snow on the deck, although that’ll be back soon enough. It’s high winds:

That said, my procrastination has had at least one upside: a larger number of interesting options (and combinations) to evaluate than before. Now, I can tether either the two parallel-connected 220-W panels or the single 400-W one to the DELTA 2’s single XT60i input.

And for the DELTA 3 Plus, thanks to the aforementioned dual XT60i inputs and 1000-W peak input support, I can hook up all three panels simultaneously, although doing so will likely take up a notable chunk of my deck real estate in the process. Please remain on standby for observations and results to come!

More on charging and firmware upgrading

Two other comments to note, in closing:

Speaking of the XT60i input, how do I charge the DELTA 3 Plus (or the DELTA 2, for that matter) in-vehicle using EcoFlow’s 800W Alternator Charger (which, yes, I already realize that I’m also overdue in installing and then testing!):

Specifically, when the portable power station is simultaneously connected to its Smart Extended Battery companion? Ordinarily, the Alternator Charger would tether to the portable power station over the XT150 connector-equipped cable that comes bundled with the former:

But, in this particular case, the portable power station’s XT150 interface is already in use (and for that matter, isn’t even an available option for lower-end devices such as my RIVER 2):

The trick is to instead use one of the two orange-color XT60i connectors also shown at the bottom left of the DELTA 3 stack setup photo.

EcoFlow alternatively bundles an XT60 connector-equipped cable with the 500-W version of the Alternator Charger, intended for use with smaller vehicles and/or more modest portable power stations, but that same cable is also available for standalone purchase:

It’ll be lower power (therefore slower) than the XT150 alternative, but it’s better than nothing! And it’ll recharge both the portable power station and (via the separate XT150-to-XT150 cable) the tethered Smart Extended Battery. Just be sure to secure the stack so it doesn’t tip over!

Also, regarding firmware upgrades, I’d been pleasantly surprised to not receive any DELTA 3 Plus update notifications since late April when it and its Smart Extra Battery companion had come into my possession. Software stability nirvana ended, in late August, alas, and since the update documentation specifically mentioned a “Better experience when using the device with an extra battery,” I decided to proceed. Unfortunately, my first several subsequent upgrade attempts terminated prematurely, at random percentage-complete points, after slower-than-usual progress, and with worrying failure status messages:

Eventually, I crossed my fingers and followed the guidance to restart the device, a process which, I eventually realized after several frustrating, unsuccessful initial attempts, can only be accomplished with the portable power station disconnected from AC. The device was stuck in a partially updated state post-reboot, albeit thankfully still accessible over Bluetooth:

And doubly thankfully, this time the upgrade completed successfully to both the DELTA 3 Plus:

And its tethered Smart Extra Battery:

Phew! As before with the DELTA 2, I think I’ll delay my next update (which hasn’t been offered yet) until I wait an appropriate amount of time and then check in with the user community first for feedback on their experiences. And with that, I await your thoughts in the comments!

—Brian Dipert is the Editor-in-Chief of the Edge AI and Vision Alliance, and a Senior Analyst at BDTI and Editor-in-Chief of InsideDSP, the company’s online newsletter.

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The post EcoFlow’s DELTA 3 Plus and Smart Extra Battery: Product line impermanence curiosity appeared first on EDN.

For third-quarter 2025, AXT Inc of Fremont, CA, USA — which makes gallium arsenide (GaAs), indium phosphide (InP) and germanium (Ge) substrates and raw materials at plants in China — has reported revenue of $28m, rebounding by 56% on $18m last quarter and up 18% on $23.6m a year ago, and far exceeding the guidance of $19–21m...

The semiconductor industry is at a pivotal moment as the limits of Moore’s Law motivate a transition to three-dimensional integrated circuit (3D IC) technology. By vertically integrating multiple chiplets, 3D ICs enable advances in performance, functionality, and power efficiency. However, stacking dies introduces layers of complexity driven by multi-physics interactions—thermal, mechanical, and electrical—which must be addressed at the start of design.

This shift from two-dimensional (2D) system-on-chips (SoC) to stacked 3D ICs fundamentally alters the design environment. 2D SoCs benefit from well-established process design kits (PDKs) and predictable workflows.

Figure 1 The 3D IC technology takes IC design to another dimension. Source: Siemens EDA

In contrast, 3D integration often means combining heterogeneous dies that use different process nodes and new interconnection technologies, presenting additional variables throughout the design and verification flow. Multi-physics phenomena are no longer isolated concerns—they are integral to the design’s overall success.

Multi-physics: a new design imperative

The vertical structure of 3D ICs—interconnected by through-silicon vias and micro-bumps and enclosed in advanced packaging materials—creates a tightly coupled environment where heat dissipation, mechanical integrity, and electrical behavior interact in complex ways.

For 2D chips, thermal and mechanical checks were often deferred until late in the cycle, with manageable impact. For 3D ICs, postponing these analyses risks costly redesigns or performance and reliability failures.

Traditional SoC design often relies on high-level RTL descriptions, where many physical optimizations are fixed early and are hard to change later. On the other hand, 3D IC’s complexity and physical coupling require earlier feedback from physics-driven analysis during RTL and floorplanning, enabling designers to make informed choices before costly constraints are locked in.

A chiplet may operate within specifications in isolation, yet face degraded reliability and performance once subjected to the real-world conditions of a 3D stack. Only early, predictive, multi-physics analysis can reveal—and enable cost-effective mitigation of—these risks.

Continuous multi-physics evaluation must begin at floorplanning and continue through every design iteration. Each change to layout, interfaces, or materials can introduce new thermal or mechanical stress concerns, which must be re-evaluated to maintain system reliability and yield.

Moving IC design to the system-level

3D ICs require close coordination among specialized teams: die designers, interposer experts, packaging engineers, and, increasingly, electronic system architects and RTL developers. Each group has its own toolchains and data standards, often with differing net naming conventions, component orientations, and functional definitions, leading to communication and integration challenges.

Adding to the internal challenges, 3D IC design often involves chiplets from multiple vendors, foundries and OSAT providers, each with different methodologies and data formats. While using off-the-shelf chiplets offers flexibility and accelerates development, integration can expose previously hidden multi-physics issues. A chiplet that works in isolation may fail specification after stacking, emphasizing the need for tighter industry collaboration.

Addressing these disparities requires a system-level owner, supported by comprehensive EDA platforms that unify methodologies and aggregate data across domains. This ensures consistency and reduces errors inherent to siloed workflows. For EDA vendors, developing inclusive environments and tools that enable such collaboration is essential.

Inter-company collaboration now also depends on more robust data exchange tools and methodologies. Here, EDA vendors play a central role by providing platforms and standards for seamless communication and data aggregation between fabless houses, foundries, and OSATs.

At the industry level, new standards and 3D IC design kits—such as those developed by the CDX working group and industry partners—are emerging to address these challenges, forging a common language for describing 3D IC components, interfaces, and package architectures. These standards are vital for enabling reliable data exchanges and integration across diverse teams and supply chain partners.

Figure 2 Here is a view of a chiplet design kit (CDK) as per JEDEC JEP30 part model. Source: Siemens EDA

Programs such as TSMC’s 3Dblox initiative provide upfront placement and interconnection definitions, reducing ambiguity and fostering tool interoperability.

Digital twin and predictive multi-physics

The digital twin concept extends multi-physics analysis throughout the entire product lifecycle. Maintaining an accurate digital representation—from transistor-level detail up to full system integration—enables predictive simulation and optimization, accounting for interactions down to the package, board, or even system level. By transferring multi-physics results between levels of abstraction, teams can verify that chiplet behavior under thermal and mechanical loads accurately predicts final product reliability.

Figure 3 A digital twin extends multi-physics analysis throughout the entire product lifecycle. Source: Siemens EDA

For 3D ICs, chiplet electrical models must be augmented by multi-physics data captured from stack-level simulations. Back-annotating temperature and stress outcomes from package-level analysis into chiplet netlists provides the foundation for more accurate system-level electrical simulations. This feedback loop is becoming a critical part of sign-off, ensuring that each chiplet performs within its operational window in the assembled system.

Keeping it cool

Thermal management is the single most important consideration for die-to-die interfaces in 3D ICs. The vertical proximity of active dies can lead to rapid heat accumulation and risks, such as thermal runaway, where ongoing heat generation further degrades electrical performance and creates mechanical stress from varying thermal expansion rates in different materials. Differential expansion between materials can even warp dies and threaten the reliability of interconnects.

To enable predictive design, the industry needs standardized “multi-physics Liberty files” that define temperature and stress dependencies of chiplet blocks, akin to the Liberty files used for place-and-route in 2D design. These files will allow designers to evaluate whether a chiplet within the stack stays within its safe operating range under expected thermal conditions.

Multi-physics analysis must also support back-annotation of temperature and stress information to individual chiplets, ensuring electrical models reflect real operating environments. While toolchains for this process are evolving, the trajectory is clear: comprehensive, physics-aware simulation and data exchange will be integral to sign-off for 3D IC design, ensuring reliable operation and optimal system performance.

Shaping the future of 3D IC design

The journey into 3D IC technology marks a transformative period for the semiconductor industry, fundamentally reshaping how complex systems are designed, verified, and manufactured. 3D IC technology marks a leap forward for semiconductor innovation.

Its success hinges on predictive, early multi-physics analysis and collaboration across the supply chain. Establishing common standards, enabling system-level optimization, and adopting the digital twin concept will drive superior performance, reliability, and time-to-market.

Pioneers in 3D IC design—across EDA, semiconductor and system developers—are moving toward unified, system-level platforms that allow designers to iterate and optimize multi-physics analyses within a “single cockpit” environment that allows designers to optimize and iterate across different types of multi-physics analyses.

Figure 4 The Innovator3D IC solution provides the single, integrated cockpit 3D IC designers need. Source: Siemens EDA

With continued advances in EDA tools, methodologies and collaboration, the semiconductor industry can unlock the full promise of 3D integration, delivering the next generation of electronic systems that push the boundaries of capability, efficiency, and innovation.

Todd Burkholder is a senior editor at Siemens DISW. For over 30 years, he has worked as editor, author, and ghost writer with internal and external customers to create print and digital content across a broad range of high-tech and EDA technologies. Todd began his career in marketing for high-technology and other industries in 1992 after earning a Bachelor of Science at Portland State University and a Master of Science degree from the University of Arizona.

Tarek Ramadan is applications engineering manager for the 3D-IC Technical Solutions Sales (TSS) organization at Siemens EDA. He drives EDA solutions for 2.5D-IC, 3D-IC, and wafer level packaging applications. Prior to that, Tarek was a technical product manager in the Siemens Calibre design solutions organization. Ramadan holds BS and MS degrees in electrical engineering from Ain Shams University, Cairo, Egypt.

John Ferguson brings over 25 years of experience at Siemens EDA to his role as senior director of product management for Caliber 3D IC solutions. With a background in physics and deep expertise in design rule checking (DRC), John has been at the forefront of 3D IC technology development for more than 15 years, witnessing its evolution from early experimental approaches to today’s production-ready solutions.

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The post Mastering multi-physics effects in 3D IC design appeared first on EDN.

CORNERSTONE Photonics Innovation Centre (C-PIC) — the UK’s dedicated Innovation and Knowledge Centre (IKC) for silicon photonics (affiliated with the University of Southampton and the University of Glasgow, as well as the UK government’s Science and Technology Facilities Council) — has partnered with Future Worlds (the University of Southampton’s startup accelerator) to launch a dedicated Silicon Photonics Stream at a Future Worlds Bootcamp on 29–30 November...

A research team led by the School of Engineering of The Hong Kong University of Science and Technology (HKUST) is said to have set a record efficiency level for red quantum rod light-emitting diodes (QR-LEDs), which could be applied to boost color vividness and brightness in next-generation display and lighting technologies for smartphones and TVs (Liao Zebing et al, ‘Inverted Device Engineering for Efficient and Bright Quantum Rod LEDs’, Advanced Materials...

Адаптаційні курси: для кого, для чого, і що на них вивчають Інформація КП пн, 11/10/2025 - 11:11

Gallium nitride (GaN) power IC and silicon carbide (SiC) technology firm Navitas Semiconductor of Torrance, CA, USA has entered into a definitive securities purchase agreement for the purchase and sale of 14,814,813 shares of Class A common stock at a purchase price of $6.75 per share. The private placement is expected to close on or about 10 November, subject to customary closing conditions. Needham & Company is acting as the sole placement agent...

Вітаємо команду ІСЗЗІ із здобуттям срібла на престижних кіберзмаганнях! kpi пн, 11/10/2025 - 10:36

Courtesy: Nvidia

When the Society of Automotive Engineers established its framework for vehicle autonomy in 2014, it created the industry-standard roadmap for self-driving technology.

The levels of automation progress from level 1 (driver assistance) to level 2 (partial automation), level 3 (conditional automation), level 4 (high automation) and level 5 (full automation).

Predicting when each level would arrive proved more challenging than defining them. This uncertainty created industry-wide anticipation, as breakthroughs seemed perpetually just around the corner.

That dynamic has shifted dramatically in recent years, with more progress in autonomous driving in the past three to four years than in the previous decade combined. Below, learn about recent advancements that have made such rapid progress possible.

What Is Level 4 Autonomous Driving?

Level 4 autonomous driving enables vehicles to handle all driving tasks within specific operating zones, such as certain cities or routes, without the need for human intervention. This high automation level uses AI breakthroughs including foundation models, end-to-end architectures and reasoning models to navigate complex scenarios.

Today, level 4 “high automation” is bringing the vision of autonomous driving closer to a scalable, commercially viable reality.

Six AI Breakthroughs Advancing Autonomous Vehicles

Six major AI breakthroughs are converging to accelerate level 4 autonomy:

1. Foundation Models

Foundation models can tap internet-scale knowledge, not just proprietary driving fleet data.

When humans learn to drive at, say, 18 years old, they’re bringing 18 years of world experience to the endeavour. Similarly, foundation models bring a breadth of knowledge — understanding unusual scenarios and predicting outcomes based on general world knowledge.

With foundation models, a vehicle encountering a mattress in the road or a ball rolling into the street can now reason its way through scenarios it has never seen before, drawing on information learned from vast training datasets.

2. End-to-End Architectures

Traditional autonomous driving systems used separate modules for perception, planning and control — losing information at each handoff.

End-to-end autonomy architectures have the potential to change that. With end-to-end architectures, a single network processes sensor inputs directly into driving decisions, maintaining context throughout. While the concept of end-to-end architectures is not new, architectural advancements and improved training methodologies are finally making this paradigm viable, resulting in better autonomous decision-making with less engineering complexity.

3. Reasoning Models

Reasoning vision language action (VLA) models integrate diverse perceptual inputs, language understanding, and action generation with step-by-step reasoning. This enables them to break down complex situations, evaluate multiple possible outcomes and decide on the best course of action — much like humans do.

Systems powered by reasoning models deliver far greater reliability and performance, with explainable, step-by-step decision-making. For autonomous vehicles, this means the ability to flag unusual decision patterns for real-time safety monitoring, as well as post-incident debugging to reveal why a vehicle took a particular action. This improves the performance of autonomous vehicles while building user trust.

4. Simulation

With physical testing alone, it would take decades to test a driving policy in every possible driving scenario, if ever achievable at all. Enter simulation.

Technologies like neural reconstruction can be used to create interactive simulations from real-world sensor data, while world models like NVIDIA Cosmos Predict and Transfer produce unlimited novel situations for training and testing autonomous vehicles.

With these technologies, developers can use text prompts to generate new weather and road conditions, or change lighting and introduce obstacles to simulate new scenarios and test driving policies in novel conditions.

5. Compute Power

None of these advances would be possible without sufficient computational power. The NVIDIA DRIVE AGX and NVIDIA DGX platforms have evolved through multiple generations, each designed for today’s AI workloads as well as those anticipated years down the road.

Co-optimization matters. Technology must be designed anticipating the computational demands of next-generation AI systems.

6. AI Safety

Safety is foundational for level 4 autonomy, where reliability is the defining characteristic distinguishing it from lower autonomy levels. Recent advances in physical AI safety enable the trustworthy deployment of AI-based autonomy stacks by introducing safety guardrails at the stages of design, deployment and validation.

For example, NVIDIA’s safety architecture guardrails the end-to-end driving model with checks supported by a diverse modular stack, and validation is greatly accelerated by the latest advancements in neural reconstruction.

Why It Matters: Saving Lives and Resources

The stakes extend far beyond technological achievement. Improving vehicle safety can help save lives and conserve significant amounts of money and resources. Level 4 autonomy systematically removes human error, the cause of the vast majority of crashes.

NVIDIA, as a full-stack autonomous vehicle company — from cloud to car — is enabling the broader automotive ecosystem to achieve level 4 autonomy, building on the foundation of its level 2+ stack already in production. In particular, NVIDIA is the only company that offers an end-to-end compute stack for autonomous driving.

The post How AI Is Powering the Road to Level 4 Autonomous Driving appeared first on ELE Times.

Courtesy: Cadence

The rising demand for AI infrastructure is driving faster innovation and smarter resource utilization throughout the design lifecycle. Accelerated computing shortens design and simulation cycles, streamlines workflows, and amplifies human creativity through data-driven insights. Together, AI and accelerated computing empower engineers to explore ideas in real time and bring their visions to life. Cadence, with its GPU-accelerated Cadence Fidelity CFD Software, collaborated with NVIDIA to generate high-fidelity simulation data for airframe simulations, generating thousands of simulations in the span of weeks using NVIDIA GB200, available through the Cadence Millennium M2000 AI Supercomputer. This was followed by using NVIDIA PhysicsNeMo, an AI physics framework, to train a physics-accurate AI surrogate model for a digital twin that provides interactive what-if design changes and analyses for aircraft design.

This breakthrough in real-time simulation is a powerful example of the Cadence strategy for innovation, “The Three Layer Cake,” in action. This strategic framework unifies Cadence’s technology stack and drives our solutions. At the foundation is accelerated compute, exemplified by the Millennium M2000 AI Supercomputer, built with NVIDIA Blackwell systems. In the middle is Cadence’s Fidelity CFD Software, enabling high-fidelity, physics-based modeling of the system under design. At the top sits AI, where frameworks like NVIDIA PhysicsNeMo and Cadence’s AI-driven design intelligence transform simulation data into interactive, predictive digital twins. Combined, these layers form a cohesive platform that empowers engineers to design, simulate, and optimize complex systems faster and more intelligently than ever before. A demonstration of the technology shows real-time airframe performance simulation while varying the design configuration. Other applications, including automotive aerodynamics or aeroacoustics, 3D-IC thermal and electromagnetic analysis, and data center thermal analysis, are possible.

How AI for Physics Is Transforming Engineering Design?

Computational fluid dynamics (CFD) is a cornerstone of modern engineering. It allows designers to simulate the flow of fluids—like air over a plane’s wings or fuel through an engine—to predict performance, identify issues, and optimize designs. However, traditional CFD methods are incredibly resource-intensive. Historically, running a single high-fidelity simulation on conventional computing systems can take days or even weeks, limiting the number of design iterations engineers can perform. Applying AI technology speeds the calculations and turnaround time, making real-time what-if design analysis practical.

High-quality results from AI are dependent on accurate and representative training data, in sufficient quantities. The availability of such data for computational engineering purposes is relatively limited in comparison to typical data used to train foundational AI models. In this example, the Cadence Fidelity CFD Software, accelerated on the Millennium M2000 AI Supercomputer, produced the high-quality dataset for the NVIDIA PhysicsNeMo framework. Thousands of detailed, time-dependent simulations were computed in a matter of weeks, with each simulation comprising hundreds of millions of degrees of freedom. This volume of high-quality data, generated from the design itself, is critical to being able to trust the AI’s predictions.

The collaboration between NVIDIA and Cadence addresses these challenges head-on. By leveraging GPU acceleration and AI, this integrated solution fundamentally changes the speed and scale of engineering simulation.

Cadence and NVIDIA Transform Aerospace and Automotive Design with AI Physics

NVIDIA is unveiling ground-breaking advancements in AI-powered simulation, transforming aerospace and automotive design with up to 500X faster engineering workflows. Cadence is at the forefront of this transformation, leveraging its Fidelity CFD Software with the Millennium M2000 AI Supercomputer built on NVIDIA Blackwell to empower aerospace leaders. By combining high-fidelity Multiphysics simulations with modern accelerated computing, Cadence enables rapid design iteration, enhanced efficiency, and optimized performance for next-generation systems. Together, Cadence and NVIDIA are accelerating innovation and redefining the future of computational engineering.

Shaping the Future of AI Infrastructure

NVIDIA has unveiled the NVIDIA AI Factory Research Center in Virginia, designed to leverage the NVIDIA Vera Rubin platform and NVIDIA DSX blueprint to enable gigawatt-scale AI factory design and development.

To ensure design precision and operational excellence, Cadence is developing a high-fidelity digital twin of the facility through its Reality DC Platform. This platform, integrated with NVIDIA Omniverse libraries, provides a physics-based simulation environment that allows engineers to model thermal, energy, and airflow dynamics across the entire infrastructure—from chip to chiller. By combining computational fluid dynamics (CFD) and Multiphysics analysis, the Cadence Reality DC Platform empowers teams to explore design configurations, predict failure scenarios, and optimize performance before physical implementation.

Together, these innovations pave the way for smarter, more sustainable data center designs—accelerating the journey toward the next generation of AI-powered infrastructure.

The post Revolutionizing System Design with AI-Powered Real-Time Simulation appeared first on ELE Times.

Microchip Technology has expanded its India footprint with the acquisition of 1.72 lakh square feet (16,000 square meters) of premium office space at the Export Promotion Industrial Park (EPIP) Zone in Whitefield, Bengaluru. This move highlights the company’s continued focus on strengthening its engineering and design capabilities in the region.

The facility will serve as a strategic extension of Microchip’s Bengaluru Development Center that can easily accommodate over 3,000 employees in the next 10 years. It is designed to support the company’s growing workforce and future hiring plans, encourage stronger collaboration across global and regional teams, and provide them with modern infrastructure for advanced research and development.

Talking on the new acquisition, Srikanth Settikere, vice president and managing director of Microchip’s India Development Center stated, “At Microchip, growth is about creating opportunities as much as scaling operations. With India contributing to nearly 20% of global semiconductor design talent, our new Bengaluru facility will sharpen our advanced IC design focus and strengthen our engagement in one of the country’s most dynamic technology hubs.”

Steve Sanghi, President and CEO of Microchip added, “We recently celebrated Microchip’s 25th anniversary in India and this office acquisition is a testament to our commitment in India. We believe our investments in the region will enable us to both benefit from and contribute to the country’s increasingly important role in the global semiconductor industry.”

The Bengaluru acquisition is Microchip’s second facility in Bengaluru besides its physical presence in Hyderabad, Chennai, Pune and New Delhi, reinforcing its long-term commitment to product development, business enablement and talent growth in India. With this expansion, the company further positions itself to deliver innovative semiconductor solutions across industrial, automotive, consumer, aerospace and defense, communications and computing markets.

The post Microchip Technology Expands its India Footprint with a New Office Facility in Bengaluru appeared first on ELE Times.

Ayo guys this is follow up on my post 10 days ago about changing the micro usb port on third party controller so I finally got thr tp4056 and did lots of soldering and sanding t the shell of the controller but couldn't tget it to stay inside so it's gonna be external as i use it only once in a while😅 submitted by /u/vIp_bLACK444 [link] [comments]

submitted by /u/CIemson [link] [comments]

Amazing how you can have spare parts sit in draws for 25 years untouched. I'm a fan of AMD so I was excited to find two of these are from them. I'm wishing I had a better microscope to de-cap and view the die. I'll have to figure out how to see if Evil Monkeyz Designz is interested in any of these for a de-capping. Parts Shown Above: submitted by /u/TheMadHatter1337 [link] [comments]