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▶️ 43-я Міжнародна конференція IEEE з електроніки та нанотехнологій (ELNANO) kpi чт, 11/13/2025 - 10:00

Caliber Interconnects Pvt. Ltd., announced that it has achieved accelerated turnaround times and first-time-right outcomes for complex chiplet and Automated Test Equipment (ATE) hardware projects. The company has refined its proprietary design and verification workflow, which integrates powerful Cadence solutions to optimize performance, power, and reliability from the earliest stages of design.

Caliber’s advanced methodology significantly enhances the efficiency and precision of designing high-complexity IC packages and dense PCB layouts. By leveraging the Cadence Allegro X Design Platform for PCB and advanced package designs, which features sub- rawing management and auto- routing, Caliber’s teams can work in parallel across various circuit blocks, compressing overall project timelines by up to 80 percent. This streamlined framework is reinforced by a rigorous in-house verification process and custom automation utilities developed using the Allegro X Design Platform’s SKILL-based scripting, ensuring consistent quality and compliance with design rules.

To meet the demands of next-generation interconnects operating at over 100 Gbps, Caliber’s engineers utilize Cadence’s Sigrity X PowerSI and Sigrity X PowerDC solutions. These advanced simulation tools allow the team to analyze critical factors such as signal loss, crosstalk, and power delivery network (PDN) impedance. By thoroughly evaluating IR drop, current density, and Joule heating, Caliber can confidently deliver design signoff, reducing the risk of costly respins and speeding time to market for its customers.

“Our team has elevated our engineering leadership by creating a disciplined workflow that delivers exceptional quality and faster turnaround times for our customers across the semiconductor ecosystem,” said Suresh Babu, CEO of Caliber Interconnects. “Integrating Cadence’s advanced design and simulation environment into our proprietary methodology empowers us to push the boundaries of performance and reliability in complex chiplet and ATE hardware design.”

The post Caliber Interconnects Accelerates Complex Chiplet and ATE Hardware Design with Cadence Allegro X and Sigrity X Solutions appeared first on ELE Times.

The TCP/IP functionality of a connected device uses dynamic RAM allocation because of the unpredictable nature of network behavior. For example, if a device serves a web dashboard, we cannot control how many clients might connect at the same time. Likewise, if a device communicates with a cloud server, we may not know in advance how large the exchanged messages will be.

Therefore, limiting the amount of RAM used by the TCP/IP stack improves the device’s security and reliability, ensuring it remains responsive and does not crash due to insufficient memory.

Microcontroller RAM overview

It’s common that on microcontrollers, available memory resides in several non-contiguous regions. Each of these regions can have different cache characteristics, performance levels, or power properties, and certain peripheral controllers may only support DMA operations to specific memory areas.

Let’s take the STM32H723ZG microcontroller as an example. Its datasheet, in section 3.3.2, defines embedded SRAM regions:

Here is an example linker script snippet for this microcontroller generated by the CubeMX:

Ethernet DMA memory

We can clearly see that RAM is split into several regions. The STM32H723ZG device includes a built-in Ethernet MAC controller that uses DMA for its operation. It’s important to note that the DMA controller is in domain D2, meaning it cannot directly access memory in domain D1. Therefore, the linker script and source code must ensure that Ethernet DMA data structures are placed in domain D2; for example, in RAM_D2.

To achieve this, first define a section in the linker script and place it in the RAM_D2 region:

Second, the Ethernet driver source code must put respective data into that section. It may look like this:

Heap memory

The next important part is the microcontroller’s heap memory. The standard C library provides two basic functions for dynamic memory allocation:

Typically, ARM-based microcontroller SDKs are shipped with the ARM GCC compiler, which includes the Newlib C library. This library, like many others, has a concept of so-called “syscalls” featuring low level routines that user can override, and which are called by the standard C functions. In our case, the malloc() and free() standard C routines call the _sbrk() syscall, which firmware code can override.

It’s typically done in the sycalls.c or sysmem.c file, and may look this:

As we can see, the _sbrk() operates on a single memory region:

That means that such implementation cannot be used in several RAM regions. There are more advanced implementations, like FreeRTOS’s heap4.c, which can use multiple RAM regions and provides pvPortMalloc() and pvPortFree() functions.

In any case, standard C functions malloc() and free() provide heap memory as a shared resource. If several subsystems in a device’s firmware use dynamic memory and their memory usage is not limited by code, any of them can potentially exhaust the available memory. This can leave the device in an out-of-memory state, which typically causes it to stop operating.

Therefore, the solution is to have every subsystem that uses dynamic memory allocation operate within a bounded memory pool. This approach protects the entire device from running out of memory.

Memory pools

The idea behind a memory pool is to split a single shared heap—with a single malloc and free—into multiple “heaps” or memory pools, each with its own malloc and free. The pseudo-code might look like this:

The next step is to make each firmware subsystem use its own memory pool. This can be achieved by creating a separate memory pool for each subsystem and using the pool’s malloc and free functions instead of the standard ones.

In the case of a TCP/IP stack, this would require all parts of the networking code—driver, HTTP/MQTT library, TLS stack, and application code—to use a dedicated memory pool. This can be tedious to implement manually.

RTOS memory pool API

Some RTOSes provide a memory pool API. For example, Zephyr provides memory heaps:

The other example of an RTOS that provides memory pools is ThreadX:

Using external allocator

The other alternative is to use an external allocator. There are many implementations available. Here are some notable ones:

• umm_malloc is specifically designed to work with the ARM7 embedded processor, but it should work on many other 32-bit processors, as well as 16- and 8-bit processors.
• o1heap is a highly deterministic constant-complexity memory allocator designed for hard real-time high-integrity embedded systems. The name stands for O(1) heap.

Example: Mongoose and O1Heap

The Mongoose embedded TCP/IP stack makes it easy to limit its memory usage, because Mongoose uses its own functions mg_calloc() and mg_free() to allocate and release memory. The default implementation uses the C standard library functions calloc() and free(), but Mongoose allows user to override these functions with their own implementations.

We can pre-allocate memory for Mongoose at firmware startup, for example 50 Kb, and use o1heap library to use that preallocated block and implement mg_calloc() and mg_free() using o1heap. Here are the exact steps:

1. Fetch o1heap.c and o1heap.h into your source tree
2. Add o1heap.c to the list of your source files
3. Preallocate memory chunk at the firmware startup

4. Implement mg_calloc() and mg_free() using o1heap and preallocated memory chunk

You can see the full implementation procedure in the video linked at the end of this article.

Avoid memory exhaustion

This article provides information on the following design aspects:

• Understand STM32’s complex RAM layout
• Ensure Ethernet DMA buffers reside in accessible memory
• Avoid memory exhaustion by using bounded memory pools
• Integrate the o1heap allocator with Mongoose to enforce TCP/IP RAM limits

By isolating the network stack’s memory usage, you make your firmware more stable, deterministic, and secure, especially in real-time or resource-constrained systems.

If you would like to see a practical application of these principles, see the complete tutorial, including a video with a real-world example, which describes how RAM limiting is implemented in practice using the Mongoose embedded TCP/IP stack. This video tutorial provides a step-by-step guide on how to use Mongoose Wizard to restrict TCP/IP networking on a microcontroller to a preallocated memory pool.

As part of this tutorial, a real-time web dashboard is created to show memory usage in real time. The demo uses an STM32 Nucleo-F756ZG board with built-in Ethernet, but the same approach works seamlessly on other architectures too.

Sergey Lyubka is the co-founder and technical director of Cesanta Software Ltd. He is known as the author of the open-source Mongoose Embedded Web Server and Networking Library, which has been on the market since 2004 and has over 12K stars on GitHub. Sergey tackles the issue of making embedded networking simpler to access for all developers.

Related Content

• Developing Energy-Efficient Embedded Systems
• Can MRAM Get EU Back in the Memory Game?
• An MCU test chip embeds 10.8 Mbit STT-MRAM memory
• How MCU memory dictates zone and domain ECU architectures
• Breaking Through Memory Bottlenecks: The Next Frontier for AI Performance

The post How to limit TCP/IP RAM usage on STM32 microcontrollers appeared first on EDN.

Vishay Intertechnology, Inc. introduced a new high speed silicon PIN photodiode with enhanced sensitivity to visible and infrared light. Featuring a compact 3.2 mm by 2.0 mm top-view, surface-mount package with a low 0.6 mm profile, the Vishay Semiconductors VEMD8083 features high reverse light current and fast response times for improved performance in biomedical applications such as heart rate and blood oxygen monitoring.

The device offers a smaller form factor than previous-generation solutions, allowing for integration into compact wearables, such as smart rings, and consumer health monitoring devices. However, while its chip size is reduced, the photodiode’s package is optimized to support a large radiant sensitive area of 2.8 mm², which enables high reverse light current of 11 μA at 525 nm, 14 μA at 660 nm, and 16 μA at 940 nm.

The VEMD8083’s high sensitivity is especially valuable in biomedical applications like photo plethysmography (PPG), where it detects variations in blood volume and flow by measuring light absorption or reflection from blood vessels. Accurate detection in these scenarios is essential for diagnosing and monitoring conditions such as cardiovascular disease.

Pin to pin compatible with competing solutions, the device detects visible and near infrared radiation over a wide spectral range from 350 nm to 1100 nm. For high sampling rates, the VEMD8083 offers fast rise and fall times of 30 ns and diode capacitance of 50 pF. The photodiode features a ± 60° angle of half-sensitivity and an operating temperature range of -40 °C to +85 °C.

RoHS-compliant, halogen-free, and Vishay Green, the device provides a moisture sensitivity level (MSL) of 3 in accordance with J-STD-020 for a floor life of 168 hours.

Samples and production quantities of the VEMD8083 are available now.

The post New Vishay Intertechnology Silicon PIN Photodiode for Biomedical Applications appeared first on ELE Times.

thought it looked coo submitted by /u/PoweredBy555 [link] [comments]

This is more of a vent I guess. So maybe it’s because my workbench is in such disarray; my home office is trashed so I started doing work in the downstairs dining room and fucked that place up, too. Wreaking havoc around the house and the other half isn’t having it lol I’m trying to work on this board and wasn’t thinking about serviceability. Only after everything was done, I was like, “oh shit this thing better work”. Got everything wired up and proper, did point to point verification with a multimeter and resolved shorts on the 5v bus and come to find out, when powered on, the ESP32 is not working as expected. Everything is point to point soldered. So I need to rebuild this stupid thing from scratch, but the proper way using wire wrap techniques and socketing the ESP32 and logic level converter boards. Just FYI, this board I’m trying to build is meant to drive a HUB75 RGB panel with text/graphics from a Raspberry Pi’s UART interface. Prototype wise, it’s working as you can see in the background, now I’m trying to put everything on this perfboard as it is mean to be displayed in the open. The ESP32 is also driving 8 x MAX7219 8x8 LED matrix. This is an effort to build a thing centered around AI/LLM. My idea/concept got everyone in the AI community in an uproar, so I’m making an art piece out of it submitted by /u/Prijent_Smogonk [link] [comments]

Пам'яті Микити Купцова kpi ср, 11/12/2025 - 21:33

submitted by /u/Ready_Rain_2646 [link] [comments]

Cree LED Inc of Durham, NC, USA (a Penguin Solutions brand) has filed a patent infringement lawsuit in the US District Court for the Northern District of Illinois alleging that Promier Products (trading as LitezAll) and Tractor Supply Co have infringed its rights in the following patents by selling certain portable lighting products: United States Patent Nos. 9070850, 9754926, 10439112, 11791442, D790486 and D892066...

South Korea-based SK keyfoundry — which provides specialty analog and mixed-signal foundry services on 8-inch wafers for consumer, communications, computing, automotive and industrial applications — says that it is accelerating the development of silicon carbide (SiC)-based compound power semiconductor technology, bolstering its efforts for the global power semiconductor market. Leveraging its manufacturing expertise and intellectual property (IP) portfolio across the semiconductor manufacturing process, in first-half 2025 the firm acquired SK powertech (formerly Yes Power Technix, until its acquisition by SK Inc in 2022), which has core competencies in the SiC sector...

Під час ворожої атаки загинув випускник КПІ, фотограф і морпіх Костянтин Гузенко kpi ср, 11/12/2025 - 17:46

😉 Запрошення до публічного обговорення проєкту Положення про отримання та використання благодійної допомоги kpi ср, 11/12/2025 - 17:11

КПІшники — перші серед 787 команд на міжнародних змаганнях з кіберзбезпеки! KPI4U-2 ср, 11/12/2025 - 16:35

Blockchain Forensic Forum kpi ср, 11/12/2025 - 16:06

Infineon Technologies AG of Munich, Germany says that it is providing its gallium nitride (GaN) technology for the next generation of solar microinverters from global energy technology company Enphase Energy Inc, which is said to be the world’s leading supplier of microinverter-based solar and battery systems. Infineon’s CoolGaN bi-directional switch (BDS) technology enables significant enhancements in power output, energy efficiency and system reliability for Enphase’s IQ9 Series Microinverters. For the new IQ9N-3P Commercial Microinverter, this helps to simplify design complexity and lower installation and balance of system costs...

In the era of Industry 4.0, manufacturing is no longer defined solely by mechanical precision; it’s now driven by data, connectivity, and intelligence. Yet downtime remains one of the most persistent threats to productivity. When a machine unexpectedly fails, the impact ripples across the entire digital supply chain: Production lines stop, delivery schedules are missed, and teams scramble to diagnose the issue. For connected factories running lean operations, even a short interruption can disrupt synchronized workflows and compromise overall efficiency.

For decades, scheduled maintenance has been the industry’s primary safeguard against unplanned downtime. Maintenance was rarely data-driven but rather scheduled at rigid intervals based on estimates (in essence, educated guesses). Now that manufacturing is data-driven, maintenance should be data-driven as well.

Time-based, or ISO-guided, maintenance can’t fully account for the complexity of today’s connected equipment because machine behaviors vary by environment, workload, and process context. The timing is almost never precisely correct. This approach risks failing to detect problems that flare up before scheduled maintenance, often leading to unexpected downtime.

In addition, scheduled maintenance can never account for faulty replacement parts or unexpected environmental impacts. Performing maintenance before it is necessary is inefficient as well, leading to unnecessary downtime, expenses, and resource allocations. Maintenance should be performed only when the data says maintenance is necessary and not before; predictive maintenance ensures that it will.

To realize the promise of smart manufacturing, maintenance must evolve from a reactive (or static) task into an intelligent, autonomous capability, which is where Industry 4.0 becomes extremely important.

From scheduled service to smart systems

Industry 4.0 is defined by convergence: the merging of physical assets with digital intelligence. Predictive maintenance represents this convergence in action. Moving beyond condition-based monitoring, AI-enabled predictive maintenance systems use active AI models and continuous machine learning (ML) to recognize and alert stakeholders as early indicators of equipment failure before they trigger costly downtime.

The most advanced implementations deploy edge AI directly to the individual asset on the factory floor. Rather than sending massive data streams to the cloud for processing, these AI models analyze sensor data locally, where it’s generated. This not only reduces latency and bandwidth use but also ensures real-time insight and operational resilience, even in low-connectivity environments. In an Industry 4.0 context, edge intelligence is critical for achieving the speed, autonomy, and adaptability that smart factories demand.

AI-enabled predictive maintenance systems use AI models and continuous ML to detect early indicators of equipment failure before they trigger costly downtime. (Source: Adobe AI Generated) Edge intelligence in Industry 4.0

Traditional monitoring solutions often struggle to keep pace with the volume and velocity of modern industrial data. Edge AI addresses this by embedding trained ML models directly into sensors and devices. These models continuously analyze vibration, temperature, and motion signals, identifying patterns that precede failure, all without relying on cloud connectivity.

Because the AI operates locally, insights are delivered instantly, enabling a near-zero-latency response. Over time, the models adapt and improve, distinguishing between harmless deviations and genuine fault signatures. This self-learning capability not only reduces false alarms but also provides precise fault localization, guiding maintenance teams directly to the source of a potential issue. The result is a smarter, more autonomous maintenance ecosystem aligned with Industry 4.0 principles of self-optimization and continuous learning.

Building a future-ready predictive maintenance framework

To be truly future-ready for Industry 4.0, a predictive maintenance platform must seamlessly integrate advanced intelligence with intuitive usability. It should offer effortless deployment, compatibility with existing infrastructure, and scalability across diverse equipment and facilities. Features such as plug-and-play setup and automated model deployment minimize the load on IT and operations teams. Customizable sensitivity settings and severity-based analytics empower tailored alerting aligned with the criticality of each asset.

Scalability is equally vital. As manufacturers add or reconfigure production assets, predictive maintenance systems must seamlessly adapt, transferring models across machines, lines, or even entire facilities. Hardware-agnostic solutions offer the flexibility required for evolving, multivendor industrial environments. The goal is not just predictive accuracy but a networked intelligence layer that connects all assets under a unified maintenance framework.

Real-world impact across smart industries

Predictive maintenance is a cornerstone of digital transformation across manufacturing, energy, and infrastructure. In smart factories, predictive maintenance monitors robotic arms, elevators, lift motors, conveyors, CNC machines, and more, targeting the most critical assets in connected production lines. In energy and utilities, it safeguards turbines, transformers, and storage systems, preventing performance degradation and ensuring safety. In smart buildings, predictive maintenance monitors HVAC systems and elevators for advanced notice of needed maintenance or replacement of assets that are often hard to monitor and cause great discomfort and loss of productivity during unexpected downtime.

The diversity of these applications underscores an Industry 4.0 truth: Interoperability and adaptability are as important as intelligence. Predictive maintenance must be able to integrate into any operational environment, providing actionable insights regardless of equipment age, vendor, or data format.

Intelligence at the industrial edge

The edgeRX platform from TDK SensEI, for example, embodies the next generation of Industry 4.0 machine-health solutions. Combining industrial-grade sensors, gateways, dashboards, and cloud interfaces into a unified system, edgeRX delivers immediate visibility into machine-health conditions. Deployed in minutes, it immediately begins collecting data to build ML models for deployment from the cloud back to the sensor device for real-time inference on the sensor at the edge.

By processing data directly on-device, edgeRX eliminates the latency and energy costs of cloud-based analytics. Its ruggedized, IP67-rated hardware and long-life batteries make it ideal for demanding industrial environments. Most importantly, edgeRX learns continuously from each machine’s unique operational profile, providing precise, actionable insights that support smarter, faster decision-making.

TDK SensEI’s edgeRX advanced machine-health-monitoring platform (Source: TDK SensEI) The road to autonomous maintenance

As Industry 4.0 continues to redefine manufacturing, predictive maintenance is emerging as a key enabler of self-healing, data-driven operations. EdgeRX transforms maintenance from a scheduled obligation into a strategic function—one that is integrated, adaptive, and intelligent.

Manufacturers evaluating their digital strategies should ask:

• Am I able to remotely and simultaneously monitor and alert on all my assets?
• Are our automated systems capturing early, subtle indicators of failure?
• Can our current solutions scale with our operations?
• Are insights available in real time, where decisions are made?

If the answer is no, it’s time to rethink what maintenance means in the context of Industry 4.0. Predictive, edge-enabled AI solutions don’t just prevent downtime; they drive the autonomy, efficiency, and continuous improvement that define the next industrial revolution.

The post Predictive maintenance at the heart of Industry 4.0 appeared first on EDN.

Just finished installing the new desk for electronics. I used to both study and do my electronics on the white desk but it would take too long to move all of my electronics every time that I wanted to study and reversed. So I just got this cheap ikea desk for electronics and the white desk is for studying strictly. I still have many ideas to improve it, starting with a rotating chair for convenience and a whiteboard on the wall which is already waiting for me to mount it. If you have any tips or criticisms feel free to share submitted by /u/DaddyPattyBatman [link] [comments]

This project made me feel a kind of kinship with Diogenes, although I was searching for the item described in the title rather than for an honest man.

Figure 1 “Diogenes Looking for an Honest Man,” a painting attributed to Johann Heinrich Wilhelm Tischbein (1751-1829). The author of this DI has a more modest goal.

Wow the engineering world with your unique design: Design Ideas Submission Guide

I wanted a design that did not require the evaluation and selection of one out of a group of components. I’d tolerate (though not welcome) the use of frequency compensation and even an automatic gain control (AGC) to achieve predictable performance characteristics. Let’s call my desired design “reliably repeatable.”

Standard MLS digital circuit

Initially, I thought none of the listed accommodations would be necessary, and that a simple well-known digital circuit—a maximal length sequence (MLS) Generator [1]—would fit the bill. This circuit produces a pseudorandom sequence whose spectral characteristics are white. A general example of such is shown in Figure 2.

Figure 2 The general form of an MLS generator. A reference lists a table of 2 to 5 specific taps for register lengths from N = 2 to 32 to produce repeating sequences of length 2N-1. Register initialization must include at least one non-zero value. The author first listened to a version using only one exclusive or gate with N = 31 registers, in which the outputs of only the 28th and 31st registers were sampled.

It was simple to code up the one described in the Figure 2 caption with an ATtiny13A microprocessor and obtain a 1.35 µs clock period. Of course, validation is in the listening. And indeed, the predominant sound is the “shush” of white noise.

But there are also audible pops, clicks, and other unwanted artifacts in the background. I had a friend with hearing better than mine listen to confirm my audition’s disappointing conclusion. And so, I picked up my lantern and moved on to the next candidate.

Reverse-biased NPN

I was intrigued by reverse-biasing a transistor’s base-emitter junction with the collector floating (see Figure 3).

Figure 3 Jig for testing the noise characteristics of NPN transistors with reverse-biased base-emitter junctions.

I tested ten 2N3906 transistors with values of R equal to 103, 104, 105, and 106 ohms. Both DC voltages and frequency sweeps (of voltage per square-root spectral densities in units of dBVrms / Hz1/2) were collected.

It was evident that as R decreased, average noise decreased and DC voltages rose slightly, remaining in the range between 7.2 and 8.3 volts. This gave me hope that a simple AGC scheme in which the transistor bias current was varied might satisfy my requirements.

Alas, it was not to be. Figure 4a, Figure 4b, Figure 4c, and Figure 4d show spectral noise in the lower frequency range. (Additional filtering of the 18-V supply had no effect on the 60 Hz power line fundamental or harmonics—these were being picked up from my test environment. The 60-Hz fundamental’s level was about 10 µV rms.)

Figure 4a Note the power line harmonics “hum” problem that the “quiet orange” transistor in particular introduces.

Figure 4b Biasing the “orange” transistor at a lower current raised the noise and hid the power line harmonics, but not the fundamental.

Figure 4c As the bias current is reduced, some but not all transistors’ noises mask the 60 Hz fundamental.

Figure 4d Regardless of whether the power line noise can be masked or eliminated, it’s clear for all resistor R values that there is no consistent shape to the frequency response.

I’ve tried other transistors with similar results. Being unable to depend on a specific frequency response shape, the reverse-biased base-emitter transistor is not a suitable signal source for a reliably predictable design. It’s time to pick up the lantern again and continue the search.

A shunt regulator

Within several datasheets of components in the ‘431 family and in the TLVH431B’s in particular, there is a figure showing the devices’ equivalent input noise. See Figure 5.

Figure 5 The equivalent input noise and test circuit for the TLVH431B (Figure 5-9 in the part’s datasheet). Source: Texas Instruments

The almost 3 dB of rise in noise from 300 Hz down to 10 Hz could be compensated for if it were repeatable from device to device. I looked at the cathode of ten devices using the test jig of Figure 6. The spectral responses are presented in Figure 7.

Figure 6 The test jig for TLVH431B spectral noise. There was no significant difference in the results shown in Figure 7 when values of 1kΩ and 10 kΩ were used for R. 100kΩ and  1MΩresistances supplied insufficient currents for the devices’ operation.

Figure 7 The TVH431B spectral noise, 10 samples with the same date code.

Although the TLVH431B is a better choice than the 2N3904, there are still variations in its noise levels, necessitating some sort of AGC. And the power line signals were still present, with no mitigation available from different values of R. The tested parts all have the same date code, and there are no numerical specs available for limits on noise amplitudes or frequency responses.

Who knows how other date codes would behave? I certainly can’t claim from the data that this component could be part of a “reliably repeatable” design as I defined the term. But you know what? Carrying this lantern around is getting to be pretty annoying.

Xorshift32

I kept thinking that there had to be a digital solution to this problem, even if it couldn’t be the one that produces an MLS. I did some research, and the option of what is called “xorshift” came up, specifically xorshift32 [2].

Xorshift32 starts by initializing a 32-bit variable to a non-zero value. A copy of this variable is created, and 13 zeros are left-shifted into the copy, eliminating the 13 left-most original register values.

The original and the shifted copy are bit-for-bit exclusive-OR’d and stored in the original variable. A copy of this result is made. 17 zeros are then right-shifted into the copy, eliminating the 17 right-most copy’s values. The shifted copy is again exclusive-OR’d bit-by-bit with the updated original register and stored in that register.

Again, a copy of the original’s latest update is made. 5 zeroes are left-shifted into the newest copy, which is then exclusive-OR’d with the latest original update and stored in that original. As this three-step process is repeated, a random sequence of length 232-1 consisting of unique 32-bit integers is generated.

This algorithm was coded into an ATtiny13A microprocessor running at a clock speed of 9.6 MHz, yielding a bit shift period of 5.8 µs. (Assembly source code and hex file are available upon request.) The least significant register bit was routed to bit 0 of the device’s portb (pin 5 of the eight-pin PDIP package.)

This pin was AC-coupled to a power amplifier driving a Polk Audio bookshelf speaker. My friend and I agreed that all we heard was white noise; the pops and clicks of the MLS sequence were absent.

Figure 8 and Figure 9 display frequency sweeps of the voltage per square-root spectral densities of the MLS and the xorshift sequences.

Figure 8 Noise spectral densities from 4 to 1550 Hz of the two auditioned digital sequences produced with 5V-powered ATtiny13A microprocessors.

Figure 9 Noise spectral densities from 63 to 25000 Hz of the two auditioned digital sequences produced with 5V-powered ATtiny13A microprocessors.

There are a few takeaways from Figures 8 and 9.

The white noises of the sequences are at high enough levels to mask my testing environment’s power line fundamental and harmonics that are apparent when evaluating the 2N3904 and the TLVH431B.

The difference in levels of the two digital sequences is due to the higher clock rate of the MLS, which spreads the same total energy as the xorshift over a wider bandwidth and results in a lower energy density within any given band of frequencies in the audible range.

Finally, the xorshift32 has a dip of perhaps 0.1 dBVrms per root Hz at 25 kHz. If the ATtiny13A were clocked from an external 20-MHz source, even this small response dip would disappear.

Audibly pure white noise source

 An audibly pure white noise source for the band from sub-sonic frequencies to 20 kHz can be had by implementing the xorshift32 algorithm on an inexpensive microprocessor.

The result is reliably repeatable, precluding the need to select an optimal component from a group. The voltage over the audio range is:

10 (-39dBVrms/20 ) / √Hz · (200000.5 √Hz),

which evaluates to a 1.6-Vrms signal. This method has none of the disadvantages of the analog noise sources investigated. There is no need to deal with low values and uncertainties of signal level, necessitating the application of a large amount of gain and an AGC, frequency-shaping below 300 Hz or elsewhere, and environmental power line noise at levels comparable to the intentional noise.

I can finally put that darn lantern down. I wonder how Diogenes made out.

Related Content

• Earplugs ready? Let’s make some noise!
• A Portable White Noise Generator Circuit
  
• Pocket-Size White Noise Generator for Quickly Testing Circuit Signal Response
• Simple White Noise Generator
• White noise source flat from 1Hz to 100kHz

References

1. https://liquidsdr.org/doc/msequence/. In the table, the exponents of the polynomials in x are the outputs of the shift registers numbered so that the first (input) register is assigned the number 1.
2. https://en.wikipedia.org/wiki/Xorshift

The post A non-finicky, mass-producible audio frequency white noise generator appeared first on EDN.

submitted by /u/Acceptable-Joke16 [link] [comments]

The world is not just connected; it is smart, fast, and relentlessly wireless. From the milliseconds it takes for a smart doorbell to notify your phone, to the instantaneous navigation updates in a self-driving car, modern life operates on a foundation of seamless, high-reliability data transfer. This relentless demand for stability, speed, and ubiquity, largely driven by consumer and industrial “smart” technologies, has radically transformed the invisible backbone of our digital existence: Radio Frequency (RF) and Microwave engineering.

Once considered a niche domain dominated by military and aerospace contractors, RF and microwave technology has sprinted into the mainstream, changing its development trajectory entirely. This shift is not just about moving to higher frequencies; it is about a fundamental change in material science, component integration, and system architecture to guarantee flawless connectivity.

The Original Spectrum: From Radar to GaAs

The initial development track of RF and microwave technology was defined by the defense. The invention of radar during the World Wars solidified the strategic importance of high-frequency electromagnetic waves. For decades, the primary goal was high power, long range, and robustness in harsh environments.

Semiconductor development in this era focused heavily on specialized materials. While early commercialization saw the use of Germanium and then Silicon Bipolar Junction Transistors (BJTs) for lower-frequency consumer applications (TVs, early analog cellular), high-frequency, high-power needs necessitated the use of compound semiconductors. Gallium Arsenide (GaAs) became the workhorse. With its higher electron mobility compared to Silicon, GaAs enabled the creation of high-performance Low-Noise Amplifiers (LNAs) and Power Amplifiers (PAs) necessary for satellite communication and early digital cellular systems.

However, the components remained largely discrete or housed in specialized Monolithic Microwave Integrated Circuits (MMICs), making them expensive and power-hungry—adequate for a small, specialized market, but fundamentally unsuitable for the coming wave of mass-market, battery-powered smart devices.

The Reliability Catalyst: Smart Devices and the Data Deluge

The true turning point arrived with the proliferation of the smartphone and the emergence of the Internet of Things (IoT). Suddenly, RF and microwave systems were no longer serving a few specialized users; they were serving billions, demanding not just speed, but absolute, unwavering reliability.

This reliability challenge manifests in several ways:

1. Capacity and Latency: The shift to 5G and beyond required exponentially more data capacity and ultra-low latency. This pushed engineers into the extremely high-frequency world of millimeter-wave (mmWave) (30 GHz to 300 GHz). At these frequencies, signals travel shorter distances and are more susceptible to attenuation, demanding sophisticated beamforming and massive Multiple-Input, Multiple-Output (Massive MIMO) antenna systems—systems that require hundreds of highly integrated, reliable RF components.
2. Energy Efficiency: Billions of IoT sensors and smartphones demand low power consumption to maximize battery life. This forced a pivot away from power-intensive legacy architectures.
3. Integration and Size (SWaP-C): Smart technology requires components that adhere to stringent Size, Weight, Power, and Cost (SWaP-C) constraints. RF chips needed to shrink and integrate baseband and analog functionality seamlessly.

The Semiconductor Pivot: GaN and the Silicon Comeback

This new reality forced the development track of RF semiconductors to split and evolve dramatically, prioritizing materials that could handle high power density while also promoting system-level integration.

1. The GaN Power Leap (High Reliability/High Power)

The most significant change in material science has been the adoption of Gallium Nitride (GaN). GaN, a wide-bandgap (WBG) semiconductor, is a game-changer because it offers superior power density and thermal conductivity compared to both Si and GaAs.

• Impact: GaN is now revolutionizing the base station infrastructure and defense systems. Its ability to produce five times more power than conventional GaAs amplifiers makes it the material of choice for the high-power, high-efficiency needs of 5G Massive MIMO radios, Active Electronically Scanned Array (AESA) radar, and electronic warfare systems, where reliable, sustained performance under stress is non-negotiable.

2. The SiGe/CMOS Integration Push (High Volume/High Integration)

For high-volume, low-cost consumer devices and integrated modules, the trend shifted toward maximizing the performance of existing Silicon processes. Silicon Germanium (SiGe) BiCMOS and advanced RF CMOS have seen a resurgence.

• Impact: By leveraging the huge, low-cost fabrication capability of the silicon industry and combining it with heterojunction structures (SiGe HBTs) or clever process engineering (RF CMOS), engineers can now integrate complex RF front-ends, digital baseband processing, and control logic onto a single, reliable chip. This capability is vital for mmWave modules in consumer electronics (like 60 GHz WiGig or short-range 5G), ensuring a reliable, low-cost solution where integration outweighs the need for maximum power.

The Next Frontier: Cognitive RF and Terahertz

Looking ahead, the evolution of RF and microwave technology continues to be driven by the quest for unparalleled reliability and spectral efficiency.

The upcoming 6G standard is already pushing semiconductor research towards Terahertz (THz) frequencies (above 300 GHz), promising truly massive bandwidth. Furthermore, the integration of Artificial Intelligence (AI) and Machine Learning (ML) is redefining system reliability through Cognitive Radio. AI algorithms are optimizing network performance in real-time, dynamically adjusting beamforming vectors, predicting component maintenance needs, and ensuring signal quality far beyond what fixed human-designed systems can achieve.

In the span of two decades, RF and microwave engineering has transitioned from a specialized, discrete component field to the vibrant heart of the semiconductor industry. Its current development track is focused entirely on materials like GaN and integrated platforms like SiGe BiCMOS—all working to meet the insatiable, non-negotiable demand for high-speed, always-on, and utterly reliable connectivity that defines the smart world. The invisible hand of wireless demand is now shaping the visible future of electronics.

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