Feed aggregator

“Facts are stubborn things” (John Adams, et al).

I added two 50-ohm outputs to the schematic of my published voltage-to-frequency converter (VFC) circuit (Figure 1). Then, I designed a PCB, purchased the (mostly) surface-mount components, loaded and re-flow soldered them onto the PCB, and then tested the design.

Figure 1 VFC design that operates from 100 kHz to beyond 100 MHz with a single 5.25-V supply, providing square wave outputs at 1/2 and 1/4 the main oscillator frequency.  

The hardware implementation of the circuit can be seen in Figure 2.

Figure 2  The hardware implementation of the 100MHz VFC was created in order to root out the facts that can only be obtained after it was built.

My objective was to get the facts about the operation of the circuit. 

Theory and simulation are important, but the facts are known only after the circuit is built and tested. That is when the unintended/unexpected consequences are seen.

The circuit mostly performed as expected, but there were some significant issues that had to be addressed in order to get the circuit performing well.

Sensitivity of the v-to-f

My first concern was the high sensitivity of the circuit to minute changes in the input voltage.  The sensitivity is 100 MHz per 5 volts, i.e., 20 MHz per volt. That means a 1-mV change on the input results in a 20-kHz change in the output frequency!

So, how do you supply an input voltage that is almost totally devoid of noise and/or ripple, which will cause jitter on the oscillator signal? To deal with this problem, I used a battery supply, four alkaline batteries in series, connected to a 10-turn, 100-kΩ potentiometer to drive the input of the circuit with about 0 to 6 V. This worked quite well. I added a 10 kΩ resistor in series with the non-inverting input of U1 for protection against overvoltage.

Problems and fixes

The first unexpected problem was that the NE555 timer did not provide sufficient drive to the voltage inverter circuit and the voltage doubler circuit. This one is on me; I didn’t look carefully at the datasheet, which says it can supply a lot of output current, but at high current, the output voltage drops so much that the inverter and the doubler circuits don’t provide enough output voltage. And the LTspice model I used for simulation was a very unrealistic model. I recommend that it not be used!

I fixed this by using a 74HC14 Schmitt trigger chip to replace the NE555 timer chip. The 74HC14 provides plenty of current and voltage to drive the two circuits. I implemented the 74HC14 circuitry as an outboard attachment to the main PCB. 

I changed the output of the voltage doubler circuit to a regulated 6 V (R16 changed to 274 Ω and R18 to 3.74 kΩ, and D8, D9 changed to SD103). This allows U1 to operate with an input voltage of up to about 5.9 V. Also, I substituted a TLV9162 dual op-amp for U1/U2 because the cost of the TLV9162 is much less than that of the LT1797. 

With the correct voltages supplied to U1/U2, I began testing the circuit, and I found that the oscillator would hang at a frequency of about 2 MHz. This was caused by the paralleled Schmitt trigger inverters. One inverter would switch before the other one, which would then sink the current from the inverter that had switched to the HIGH output state, and the oscillator would stop functioning. Paralleling inverters, which are driven by a relatively slowly falling (or rising) input signal, is definitely not a viable idea!

To fix the problem, I removed U4 from the circuit and put a 22-Ω resistor in series with the output of inverter U3 to lessen the current load on it, and the oscillator operated as expected.

I made some changes to the current-to-voltage converter circuit to provide more adjustment range and to use the optimum values for the 5-V supply. I changed R8 to 3.09 kΩ, potentiometer R9 to 1 kΩ, and R13 to 2.5 kΩ.

Adjustments

There are two adjustments provided: R9 is an adjustment for the current-to-voltage converter U2, and R11 is an offset current adjustment. 

I adjusted R9 to set the oscillator frequency to 100 MHz with the input voltage set to 5.00 V, and then adjusted R11 at 2 MHz.

The percent error of the circuit increases at the lower frequencies; possibly due to diode leakage currents, or nonlinear behavior of the frequency to voltage converter consisting of D2 – D4 and C8 – C11?

Test results

With the noted changes implemented, I began testing the VFC. The problem of jitter on the output signal was apparent, especially at the lower frequencies. 

I realized that ripple and noise on the 5-V supply would cause jitter on the output signal. As noted on the schematic, the oscillator frequency is a function of the supply voltage.

To avoid this problem, I once again opted to use batteries to provide the supply voltage. I used six alkaline batteries to supply about +9 V and regulated the voltage down to +5 V with an LM317T regulator and a few other components. 

This setup achieves about the minimum ripple and noise on the supply and the minimum oscillator jitter. The remaining possible sources of noise/jitter are the switching supplies for U1, the feedback voltage to U1, and the switching on and off of the counters and the inverters, which can cause noise on the +5-V supply.

The frequency versus input voltage plot is not as linear as expected, but it is pretty good over a wide range of input voltage from 50 mV to 5.00 V for a corresponding frequency range of 1.07 MHz to 103.0 MHz (Figure 3 and Figure 4). The percent error versus frequency is shown in Figure 5.

Figure 3 The frequency from 1.07 MHz to 103.0 MHz versus input voltage from 50 mV to 5.00 V.

Figure 4 The frequency (up to 2 MHz) versus input voltage when Vin < 0.1 V.

Figure 5 The percent error versus frequency.

Waveforms

Some waveforms are shown in Figure 6, Figure 7, Figure 8, and Figure 9. Most are from the divide-by-2 output because it is more visually interesting than the 3.4-ns output from the oscillator (multiply the divide-by-2 frequency by 2 to get the oscillator frequency). 

The input voltage ranges from 10 mV to 5 V to produce the 200 kHz to 100 MHz oscillator/inverter output.

Figure 6 Oscilloscope waveform with a divide-by-two output at 100 kHz.

Figure 7 Oscilloscope waveform with a divide-by-two output at 500 kHz.

Figure 8 Oscilloscope waveform with a divide-by-two output at 5 MHz.

Figure 9 Oscilloscope waveform with a divide-by-two output at 50 MHz.

Figure 10 displays the output of the oscillator/inverter at 100 MHz.  Figure 11 shows the 3.4 ns oscillator/inverter output pulse. 

Figure 10 Oscilloscope waveform with the oscillator output at 100 MHz.

Figure 11 Oscilloscope waveform with a 3.4-ns oscillator pulse.

The facts

So, here are the facts. 

The two inverters in parallel did not work in this application. This was fixed by eliminating one of them and putting a larger resistor in series with the output of the remaining one to reduce the current load on it.

The high sensitivity of the circuit to the input voltage presents a challenge in practice. Generating a sufficiently quiet input voltage is difficult.

Battery operation provides some help, but this presents its own challenges in practice. Noise on the 5-V supply is a related problem. The supply for the second divide-by-two circuit, U7, must be tightly regulated and extremely free of noise and ripple to minimize jitter on the oscillator signal.

And, as noted above, some changes in the values of several components were necessary to get acceptable operation.

Finally, more accurate voltage-versus-frequency operation at lower frequencies will require more careful engineering, if desired. I leave this to the user to work this out, if necessary. 

At this point, I am satisfied with the circuit as it is (I feel that it is time to take a break!).

Some suggestions for improved results

The circuit is compromised by the challenge to make it work with a single 5-V supply. It would be less challenging if separate, well-regulated, well-filtered supplies were used for U1/U2, for example, a 14 V regulated down to 11 V for the positive supply, and a negative 5 V regulated down to -2.5 V (use linear regulators for both supplies!) 

The input could then range from 0 to 10 V, which would reduce the input sensitivity by a factor of two and make it easier to design quieter supplies for the input amplifier and current-to-voltage circuits, U1/U2.

At the lower frequencies, some investigation should be done to expose the causes of the nonlinearity in that frequency range, and to indicate changes that would improve the circuit operation.

Another option would be to split the operation into two ranges, such as 100 kHz to 1 MHz and 1 MHz to 100 MHz.

Final fact

The operation of the circuit is pretty impressive when the circuit is modified as suggested. I think actualizing an oscillator that provides an output from 200 kHz to 113 MHz is quite a remarkable result. Thanks to the late Jim Williams [2] and to the lively Stephen Woodward [3] for leading the way to the implementation of this circuit!

Jim McLucas retired from Hewlett-Packard Company after 30 years working in production engineering and on the design and test of analog and digital circuits.

References/Related Content

1. A simulated 100-MHz VFC
2. 1-Hz to 100-MHz VFC features 160-dB dynamic range
3. 100-MHz VFC with TBH current pump
4. Take-Back-Half precision diode charge pump

The post My 100-MHz VFC – the hardware version appeared first on EDN.

III–V Epi Ltd of Glasgow, Scotland, UK — which provides a molecular beam epitaxy (MBE) and metal-organic chemical vapor deposition (MOCVD) service for custom compound semiconductor wafer design, manufacturing, test and characterization — says that its chief technical officer professor Richard Hogg is chairing two sessions at PCSEL 2025 (the International Workshop on PCSELs) held at the University of Glasgow on 10–12 November. This includes the Keynote Session ‘Progress of PCSELs’ from PCSEL research pioneer Susumu Noda, professor of Electronic Science and Engineering at Kyoto University in Japan...

STMicroelectronics has revealed the ISM6HG256X, a tiny three-in-one motion sensor for data-hungry industrial IoT applications, serving as an additional catalyst for edge AI advancement. This smart, highly accurate IMU sensor uniquely combines simultaneous detection of low-g (±16g) and high-g (±256g) accelerations with a high performance and stable gyroscope within a single compact package, ensuring no critical event—from subtle motion or vibrations to severe shocks—is ever missed.

The ISM6HG256X addresses the growing demand for reliable, high-performance sensors in industrial IoT applications such as asset tracking, worker safety wearables, condition monitoring, robotics, factory automation, and black box event recording. By integrating accelerometer with dual full-scale ranges, it eliminates the need for multiple sensors, simplifying system design and reducing overall complexity. Its embedded edge processing and self-configurability support real-time event detection and context-adaptive sensing, which are essential for long lasting asset tracking sensor nodes, wearable safety devices, continuous industrial equipment monitoring, and automated factory systems.

“Traditional solutions require multiple sensors to cover low and high acceleration ranges, increasing system complexity, power consumption, and cost. The ISM6HG256X addresses these challenges by providing a single, highly integrated sensor,” said Simone Ferri, APMS Group VP & MEMS Sub-Group GM, STMicroelectronics. “These new sensing dimensions, made possible also in harsh environment, combined with machine-learning running inside the IMU sensor itself, allows to quickly recognize, track and classify motion, activities and events while using very little power, helping businesses make smart, data-driven decisions as they move toward digital transformation.”

Technical information

The ISM6HG256X contains the unique machine-learning core (MLC) and finite state machine (FSM), together with adaptive self-configuration (ASC) and sensor fusion low power (SFLP). These features bring edge AI directly into the sensor to autonomously classify detected events, ensuring real-time, low-latency performance and ultra-low system power consumption. This embedded technology can reconstruct signal dynamics to provide high-fidelity motion tracking. Thanks to the embedded SFLP algorithm, also 3D orientation tracking is possible with just few µA of current consumption. 

ST’s new X-NUCLEO-IKS5A1 industrial expansion board with MEMS Studio design environment and extensive software libraries, X-CUBE-MEMS1, are available to assist developers, helping implement functions including high-g and low-g fusion, sensor fusion, context awareness, asset tracking, and calibration.

The ISM6HG256X is available now, in a 2.5mm x 3mm surface-mount package built to withstand harsh industrial environments from -40°C to 105°C. Pricing starts at $4.27 for orders of 1000 pieces, from the eSTore and through distributors.

The ISM6HG256X is part of ST’s longevity program, which ensures long-term availability of critical components for at least 10 years to support customers’ industrial product ranges.

The post STMicroelectronics empowers data-hungry industrial transformation with unique dual-range motion sensor appeared first on ELE Times.

Wolfspeed Inc of Durham, NC, USA — which makes silicon carbide (SiC) materials and power semiconductor devices — is collaborating with renewable energy solutions firm Hopewind of Shenzhen City (one of the largest wind power converter suppliers in China). Together, the two firms will advance the development of the next generation of wind power solutions by integrating Wolfspeed’s 2.3kV LM Pack Module into Hopewind’s highly modular and lightweight 950Vac Wind Power Converter...

🚀 Підсумкова науково-практична конференція Міжнародного конкурсу студентських наукових робіт зі штучного інтелекту в КПІ ім. Ігоря Сікорського kpi вт, 11/11/2025 - 10:00

Іван Пишнограєв. Застосовує ШІ для прийняття рішень Інформація КП вт, 11/11/2025 - 10:00

In industrial applications using digital-to-analog converters (DACs), programmable logic controllers (PLCs) set an analog output voltage to control actuators, motors, and valves. PLCs can also regulate manufacturing parameters such as temperature, pressure, and flow.

In these environments, the DAC output may require overvoltage protection from accidental shorts to higher-voltage power supplies and other sustained high-voltage miswired connections. You can protect precision DAC outputs in two different ways, depending on whether the DAC output buffer has an external feedback pin.

Overvoltage damage

There are two potential consequences should an accidental sustained overvoltage event occur at the DAC output.

First, if the DAC output can drive an unsustainable current limit, then damage may occur as the output buffer drives an excess of current. This current limit may also occur if the output voltage is shorted to ground or to another voltage within the supply range of the DAC.

Second, electrostatic discharge (ESD) diodes latched to the supply and ground can source and sink current during sustained overvoltage events, as shown in Figure 1 and Figure 2. In many DACs, a pair of internal ESD diodes that shunt any momentary ESD current away from the device can help protect the output pin. In Figure 1, a large positive voltage causes an overvoltage event in the output and forward-biases the positive AVDD ESD diode. The VOUT pin sinks current from the overvoltage event into the positive supply.

Figure 1 Current is shunted to positive supply during a positive overvoltage event. Source: Texas Instruments

In Figure 2, the negative overvoltage sources current from the negative supply through the AVSS ESD diode to VOUT.

Figure 2 Current is shunted to positive supply during a negative overvoltage event. Source: Texas Instruments

In Figure 1 and Figure 2, internal ESD diodes are not designed to sink or source current associated with a sustained overvoltage event, which will typically damage the ESD diodes and voltage output. Any protection should limit this current during an overvoltage event.

Overvoltage protection

While two basic components will protect precision DAC outputs from an overvoltage event, the protection topology for the DAC depends on the internal or external feedback connection for the DAC output buffer.

If the DAC output does not have an external voltage feedback pin, you can set up protection as a basic buffer using an operational amplifier (op amp) and a current protection device at its output. If the DAC has an external voltage feedback pin, then you would place the current protection device at the output of the DAC, with the op amp driving the feedback sense pin.

Let’s explore both topologies.

Figure 3 shows protection for a DAC without a feedback sense pin, with the op amp set up as a unity gain buffer. Inside the op amp feedback, an eFuse opens the circuit if the op amp output current exceeds a set level.

Figure 3 Output protection for a DAC works without a feedback pin. Source: Texas Instruments

Again, if the output terminal voltage is within the supplies of the op amp, the output current comes from the short-circuit current limit. An output terminal set beyond the supplies of the op amp, as in a positive or negative overvoltage, will cause the supply rails to source or sink additional current, as previously shown in Figure 1 and Figure 2.

Because the output terminal connects to the op amp’s negative input, the op amp input must have some sort of overvoltage protection. For this protection circuit, an op amp with internal overvoltage protection that extends far beyond the op amp supply voltage is selected. When using a different op amp, series resistance that limits the input current can help protect the inputs.

The circuit shown in Figure 3 will also work for a precision DAC with a feedback sense pin. The DAC feedback sense pin would simply connect to the DAC VOUT pin, using the same protection buffer circuit. If you want to use the DAC feedback to reduce errors from long output and feedback sense wire resistances, you need to use a different topology for the protection circuit.

If the DAC has an external feedback sense pin, changing the protection preserves the sense connection. In Figure 4, the eFuse connects directly to the DAC output. The eFuse opens if the DAC output current exceeds a set level. Here, the op amp acts as a unity gain buffer to drive the DAC sense feedback pin.

Figure 4 This output protection for a DAC works with a feedback pin. Source: Texas Instruments

In both topologies, shown in Figure 3 and Figure 4, the two protection devices have the same requirements. For the eFuse, the break current must be lower than the current level that might damage the device it’s protecting. For the op amp, input protection is required, as the output overvoltage may significantly exceed the rail voltage. In operation, the offset voltage must be lower than the intended error, and the bandwidth must be high enough to satisfy the system requirements.

Overvoltage protection component selection

To help you select the required components, here are the system requirements for operation and protection:

• Supply range: ±15 V
• Sustained overvoltage protection: ±32 V
• Current at sustained overvoltage: approximately 30 mA
• Output protection should introduce as little error as possible, based on offset or bandwidth

The primary criteria for op amp selection were overvoltage protection of the inputs. For instance, the super-beta inputs of the OPA206 precision op amp have an integrated input overvoltage protection that extends up to ±40 V beyond the op amp supply voltage. Figure 5 shows the input bias current relative to the input common-mode voltage powering OPA206 with ±15 V supplies. Within the ±32 V range of overvoltage protection, the input bias current stays below ±5 mA of input current.

Figure 5 Input bias current for the OPA206 is shown versus the input common-mode voltage. Source: Texas Instruments

The OPA206 offset voltage is very low (typically ±4 µV at 25°C and ±55 µV from –40°C to 125°C) and the buffer contributes little error to the DAC output. When using a different op amp without integrated input overvoltage protection, adding series resistance at the inputs will limit the input current.

The TPS2661 eFuse was originally intended as a current-loop protector with input and output miswiring protection. If its output voltage exceeds the rail supplies, TPS2661 detects miswiring and cuts off the current path, restoring the current path when the output overvoltage returns below the supply.

If the output current exceeds TPS2661’s 32-mA current-limit protection, the device breaks the connection and retests the current path for 100 ms periodically every 800 ms. The equivalent resistance of the device is a maximum 12.5 Ω, which enables a high-current transmission output without large voltage headroom and footroom loss at the output.

Beyond the op amp and eFuse protection, applying an optional transient voltage suppression (TVS) diode will provide additional surge protection as long as the chosen breakdown voltage is higher than any sustained overvoltage. If the breakdown voltage is less than the sustained overvoltage, then an overvoltage can damage the TVS diode. In this circuit, the expected sustained overvoltage is ±32 V, with an optional TVS3301 device that has a bidirectional 33-V breakdown for surge protection.

Another TVS3301 added to the ±15-V supplies is an additional option. An overvoltage on the terminal will direct any fault current into the power supplies. If the supply cannot sink the current or is not fast enough to respond to the overvoltage, then the TVS diode absorbs excess current as the overvoltage occurs.

Constructed circuit: Precision DAC without a feedback sense pin

You can build and test the overvoltage protection buffer from Figure 3 with the DAC81416-08 evaluation module (EVM). This multichannel DAC doesn’t have an external feedback sense pin. Figure 6 shows the constructed protection buffer tested on one of the DAC channels.

Figure 6 The constructed overvoltage protection circuit employs the DAC81416-08 evaluation module. Source: Texas Instruments

Ramping the output of DAC from –10 V to 10 V drives the buffer input. Figure 7 shows that the measured offset of the buffer is less than 10 µV over the full range.

Figure 7 Protection buffer output offset error is shown versus buffer input voltage. Source: Texas Instruments

Connecting the output to a variable supply tests the output overvoltage connection, driving the output voltage and then recording the current at the output. The measurement starts at –32 V, increases to +32 V, then changes back from +32 V down to –32 V. Figure 8 shows the output current set to overvoltage and its recovery from overvoltage.

Figure 8 Protection buffer output current is shown versus buffer output overvoltage. Source: Texas Instruments

The measurements show hysteresis in both the positive and negative overvoltage of the protection buffer that comes from extra voltage across the series resistor at the output of the TPS26611. During normal operation (without an overvoltage), the TPS26611 current path turns off when the output rises and is driven above 17.2 V, at which point the remaining output current comes from the overvoltage of the OPA206 input. As the output voltage decreases, the TPS26611 current path conducts current again when the output drops below 15 V.

When driving the output to a negative overvoltage, the current path turns off at –17.5 V and turns on again when the output returns above –15 V.

Constructed circuit: Protection for a DAC with output feedback

Like the previous circuit, you can test the overvoltage protection from Figure 4. This test attaches an overvoltage protection buffer to the output of a DAC with an external feedback sense pin. The DAC8760 EVM tests for an output overvoltage event. As shown in Figure 9, a 1-kΩ resistor placed between VOUT and +VSENSE prevents the output buffer feedback loop of the DAC from breaking if the feedback sense signal is cut.

Figure 9 This constructed overvoltage protection circuit is used with the DAC8760 evaluation module. Source: Texas Instruments

Ramping the output of the DAC from –10 V to +10 V drives the feedback buffer input. Shown in Figure 10, the offset of the feedback to +VSENSE is again <10 μV over the full range.

Figure 10 Feedback buffer offset error is shown versus buffer input voltage. Source: Texas Instruments

The DAC is again set to 0 V, with the output connected to a variable supply to check the output current against output overvoltage. Figure 11 shows the output current as the output voltage increases from –32 V to +32 V and decreases to –32 V.

Figure 11 Protection buffer output current is shown versus buffer output overvoltage. Source: Texas Instruments

As before, there is current path hysteresis. The TPS26611 current path shuts off when the output goes above 16.5 V and turns on when the output returns to about 15 V. For the negative overvoltage, the current path turns off when the output is below –16.8 V and turns on again when the output returns above –15 V.

Two overvoltage protection topologies

Industrial control applications for analog outputs require specialized protection from harsh conditions. This article presented two topologies for precision DAC protection against sustained overvoltage events:

• DAC without external feedback: Protecting the output from an overvoltage by using an op amp buffer with an eFuse in the op amp output.
• DAC with external feedback: Protecting the output from overvoltage by using an eFuse to limit the DAC output current and with an op amp acting as a unity gain buffer for sense feedback.

In both cases, the tested circuits show a limited offset error (<10 µV) through the range of operation (±10-V output) and protection from sustained overvoltage of ±32 V.

Joseph Wu is applications engineer for digital-to-analog converters (DACs) at Texas Instruments.

 

 

Art Kay is applications engineer for precision signal conditioning products at Texas Instruments.

 

 

Related Content

• Pressures grow for circuit protection
• Overvoltage-protection circuit saves the day
• Do You Have the Right Power Supply Protections?
• How to prevent overvoltage conditions during prototyping
• Adding over-voltage protection to your mobile/portable embedded design

The post Protecting precision DACs against industrial overvoltage events appeared first on EDN.

now granted falstad probably isn't the best sim around, but for a free one its really easy to use and intuitive. I am shopping around for good sims though so if yall have any suggestions on better sims that match falsteds simulation im open ears. submitted by /u/Lagfoundry [link] [comments]

GlobalFoundries of Malta, NY (GF, the only US-based pure-play foundry with a global manufacturing footprint, including facilities in the USA, Europe and Singapore) has entered into a technology licensing agreement with Taiwan Semiconductor Manufacturing Company Ltd (TSMC) for 650V and 80V gallium nitride (GaN) technology. The strategic move will accelerate GF’s next generation of GaN products for data-center, industrial and automotive power applications and provide US-based GaN capacity for a global customer base...

Specialty semiconductor and performance materials producer 5N Plus Inc (5N+) of Montréal, Québec, Canada has been included in the MSCI Canada Small Cap Index, effective as of the close of trading on 24 November...

BluGlass Ltd of Silverwater, Australia — which develops and manufactures gallium nitride (GaN) blue laser diodes based on its proprietary low-temperature, low-hydrogen remote-plasma chemical vapor deposition (RPCVD) technology — has appointed non-executive director Omer Granit as executive chair to lead a refreshed board during the next phase of commercial growth for the company...

When you're prototyping but the SOIC package IC you ordered is in actuality apparently a "wide body SOIC" Got to get creative fitting it onto a SOIC-2-DIP converter! If it works, it works! submitted by /u/Peter-Langton [link] [comments]

Earlier this summer, I detailed my travails struggling with (and ultimately recovering from) buggy firmware updates I’d been “pushed” on my combo of EcoFlow’s DELTA 2 portable power station and its Smart Extra Battery supplemental capacity companion:

Toward the end of that earlier writeup, I mentioned that I’d subsequently been offered a further firmware update, which (for, I think, understandable reasons) I was going to hold off on tackling for a while, until I saw whether other, braver souls had encountered issues of their own with it:

DELTA 2 firmware update success(es)

In late August, I eventually decided to take the upgrade plunge, after enduring the latest in an occasional but enduring series of connectivity glitches. Although I could still communicate with the device “stack” via Bluetooth, its Wi-Fi connection had dropped and needed to be reinstated within the app. The firmware update’s documentation indicated it’d deal with this issue:

The upgrade attempt was thankfully successful this time, although candidly, I can’t say that the Wi-Fi connectivity is noticeably more robust now than it had been previously:

I was then immediately offered another firmware upgrade, which I’d heard on Facebook’s “EcoFlow Official Club“ group had just been released. Tempting fate, I plunged ahead again:

Thankfully, this one completed uneventfully as well:

As did another offered to me in early September (gotta love that descriptive “Fixes some known issues” phrasing, eh? I’m being sarcastic, if it wasn’t already obvious…):

There have been no more firmware upgrades in the subsequent ~1.5 months. More generally, since the DELTA 2 line is mature and EcoFlow has moved on to the DELTA 3 series, I’m hopeful for ongoing software stability (accompanied by no more functional misbehavior) at this point.

Initial impressions of DELTA 3 devices

Speaking of which, what about the DELTA 3 Plus and its accompanying Smart Extra Battery, mentioned at the end of my earlier write-up, which EcoFlow support had sent as replacements for the DELTA 2-generation predecessors prior to my successful resurrection of them?

Here again is what the new DELTA 3 stack (left) looks like next to its DELTA 2 precursors (right):

The stored-charge capacity of the DELTA 2 is 1024Wh, which matches that of the DELTA 3 Plus. I’d mentioned in my earlier DELTA 2 coverage that the DELTA 3 Plus was based on newer,  denser (but still LiFePO₄ aka LFP) 40135 batteries. Why then do the two portable power stations have nearly the same sizes? The answer, of course, is that there’s more than just batteries inside ‘em:

The (presumed) varying battery generation-induced size differential is much more evident with the two generations of Smart Extra Batteries…which are (essentially) just batteries.

Despite their 1,024-Wh capacity commonality, the DELTA 3 version (again on top of the stack at left in the earlier photo) has dimensions of 15.7 x 8 x 7.8 in (398 x 200 x 198 mm) and weighs 21.1 lbs. (9.6 kg).

Its DELTA 2-generation predecessor at top right weighs essentially the same (21 lbs./9.5 kg), and it’s nearly 50% taller (15.7 × 8.3 × 11.1 in./40 × 21.1 × 28.1 cm).

By the way, back when I was fearing that the base DELTA 2 unit was “toast” but hoping that its Smart Extra Battery might still be saved, I confirmed EcoFlow’s claim that the DELTA 3 Plus worked not only with multiple capacity variants of the DELTA 3-generation Smart Extra Battery, for capacity expansion up to 5 KWh, but also with my prior-generation storage capacity expansion solution:

Charging (and other) enhancements

Aside from the height-therefore-volume differential, the most visually obvious other difference between the two portable power stations is the relocation of AC power outlets to the front panel in the DELTA 3 Plus case. Other generational improvements include:

• Faster sub-10-ms switchover from wall outlet-sourced to inverter-generated AC for more robust (albeit not comprehensive…no integrated surge protection support, for example) UPS functional emulation
• Improved airflow, leading to claimed 30-dB noise levels in normal operation
• A newer-generation battery-induced boosted recharge cycle count to 4,000
• Inverter-generated AC output power up to 3600 W (X-Boost surge)
• Higher power, albeit fewer, USB-A ports (two, each 36 W, compared to two 12 W and two 18 W)
• Higher power USB-C ports (two, each 140 W, versus two 100 W)
• And faster charging (sub-1-hour to 100%), enabled by factors such as:
  • AC input power up to 1500 W
  • Solar input power up to 1000 W (two 500-W-max XT60i connectors) with maximum power point tracking (MPPT) support
  • And simultaneous multi-charging capabilities from solar and AC when both are available, prioritizing the former to save money.

Speaking of solar, I haven’t forgotten about the two 220W panels:

And a more recently acquired 400W one:

For which I’m admittedly belated in translating testing aspiration into reality. The issue at the moment isn’t snow on the deck, although that’ll be back soon enough. It’s high winds:

That said, my procrastination has had at least one upside: a larger number of interesting options (and combinations) to evaluate than before. Now, I can tether either the two parallel-connected 220-W panels or the single 400-W one to the DELTA 2’s single XT60i input.

And for the DELTA 3 Plus, thanks to the aforementioned dual XT60i inputs and 1000-W peak input support, I can hook up all three panels simultaneously, although doing so will likely take up a notable chunk of my deck real estate in the process. Please remain on standby for observations and results to come!

More on charging and firmware upgrading

Two other comments to note, in closing:

Speaking of the XT60i input, how do I charge the DELTA 3 Plus (or the DELTA 2, for that matter) in-vehicle using EcoFlow’s 800W Alternator Charger (which, yes, I already realize that I’m also overdue in installing and then testing!):

Specifically, when the portable power station is simultaneously connected to its Smart Extended Battery companion? Ordinarily, the Alternator Charger would tether to the portable power station over the XT150 connector-equipped cable that comes bundled with the former:

But, in this particular case, the portable power station’s XT150 interface is already in use (and for that matter, isn’t even an available option for lower-end devices such as my RIVER 2):

The trick is to instead use one of the two orange-color XT60i connectors also shown at the bottom left of the DELTA 3 stack setup photo.

EcoFlow alternatively bundles an XT60 connector-equipped cable with the 500-W version of the Alternator Charger, intended for use with smaller vehicles and/or more modest portable power stations, but that same cable is also available for standalone purchase:

It’ll be lower power (therefore slower) than the XT150 alternative, but it’s better than nothing! And it’ll recharge both the portable power station and (via the separate XT150-to-XT150 cable) the tethered Smart Extended Battery. Just be sure to secure the stack so it doesn’t tip over!

Also, regarding firmware upgrades, I’d been pleasantly surprised to not receive any DELTA 3 Plus update notifications since late April when it and its Smart Extra Battery companion had come into my possession. Software stability nirvana ended, in late August, alas, and since the update documentation specifically mentioned a “Better experience when using the device with an extra battery,” I decided to proceed. Unfortunately, my first several subsequent upgrade attempts terminated prematurely, at random percentage-complete points, after slower-than-usual progress, and with worrying failure status messages:

Eventually, I crossed my fingers and followed the guidance to restart the device, a process which, I eventually realized after several frustrating, unsuccessful initial attempts, can only be accomplished with the portable power station disconnected from AC. The device was stuck in a partially updated state post-reboot, albeit thankfully still accessible over Bluetooth:

And doubly thankfully, this time the upgrade completed successfully to both the DELTA 3 Plus:

And its tethered Smart Extra Battery:

Phew! As before with the DELTA 2, I think I’ll delay my next update (which hasn’t been offered yet) until I wait an appropriate amount of time and then check in with the user community first for feedback on their experiences. And with that, I await your thoughts in the comments!

—Brian Dipert is the Editor-in-Chief of the Edge AI and Vision Alliance, and a Senior Analyst at BDTI and Editor-in-Chief of InsideDSP, the company’s online newsletter.

Related Content

• Firmware-upgrade functional defection and resurrection
• EcoFlow’s Delta 2: Abundant Stored Energy (and Charging Options) for You
• Portable power station battery capacity extension: Curious coordination
• EcoFlow’s RIVER 2: Svelte portable power with lithium iron phosphate fuel

The post EcoFlow’s DELTA 3 Plus and Smart Extra Battery: Product line impermanence curiosity appeared first on EDN.

For third-quarter 2025, AXT Inc of Fremont, CA, USA — which makes gallium arsenide (GaAs), indium phosphide (InP) and germanium (Ge) substrates and raw materials at plants in China — has reported revenue of $28m, rebounding by 56% on $18m last quarter and up 18% on $23.6m a year ago, and far exceeding the guidance of $19–21m...

The semiconductor industry is at a pivotal moment as the limits of Moore’s Law motivate a transition to three-dimensional integrated circuit (3D IC) technology. By vertically integrating multiple chiplets, 3D ICs enable advances in performance, functionality, and power efficiency. However, stacking dies introduces layers of complexity driven by multi-physics interactions—thermal, mechanical, and electrical—which must be addressed at the start of design.

This shift from two-dimensional (2D) system-on-chips (SoC) to stacked 3D ICs fundamentally alters the design environment. 2D SoCs benefit from well-established process design kits (PDKs) and predictable workflows.

Figure 1 The 3D IC technology takes IC design to another dimension. Source: Siemens EDA

In contrast, 3D integration often means combining heterogeneous dies that use different process nodes and new interconnection technologies, presenting additional variables throughout the design and verification flow. Multi-physics phenomena are no longer isolated concerns—they are integral to the design’s overall success.

Multi-physics: a new design imperative

The vertical structure of 3D ICs—interconnected by through-silicon vias and micro-bumps and enclosed in advanced packaging materials—creates a tightly coupled environment where heat dissipation, mechanical integrity, and electrical behavior interact in complex ways.

For 2D chips, thermal and mechanical checks were often deferred until late in the cycle, with manageable impact. For 3D ICs, postponing these analyses risks costly redesigns or performance and reliability failures.

Traditional SoC design often relies on high-level RTL descriptions, where many physical optimizations are fixed early and are hard to change later. On the other hand, 3D IC’s complexity and physical coupling require earlier feedback from physics-driven analysis during RTL and floorplanning, enabling designers to make informed choices before costly constraints are locked in.

A chiplet may operate within specifications in isolation, yet face degraded reliability and performance once subjected to the real-world conditions of a 3D stack. Only early, predictive, multi-physics analysis can reveal—and enable cost-effective mitigation of—these risks.

Continuous multi-physics evaluation must begin at floorplanning and continue through every design iteration. Each change to layout, interfaces, or materials can introduce new thermal or mechanical stress concerns, which must be re-evaluated to maintain system reliability and yield.

Moving IC design to the system-level

3D ICs require close coordination among specialized teams: die designers, interposer experts, packaging engineers, and, increasingly, electronic system architects and RTL developers. Each group has its own toolchains and data standards, often with differing net naming conventions, component orientations, and functional definitions, leading to communication and integration challenges.

Adding to the internal challenges, 3D IC design often involves chiplets from multiple vendors, foundries and OSAT providers, each with different methodologies and data formats. While using off-the-shelf chiplets offers flexibility and accelerates development, integration can expose previously hidden multi-physics issues. A chiplet that works in isolation may fail specification after stacking, emphasizing the need for tighter industry collaboration.

Addressing these disparities requires a system-level owner, supported by comprehensive EDA platforms that unify methodologies and aggregate data across domains. This ensures consistency and reduces errors inherent to siloed workflows. For EDA vendors, developing inclusive environments and tools that enable such collaboration is essential.

Inter-company collaboration now also depends on more robust data exchange tools and methodologies. Here, EDA vendors play a central role by providing platforms and standards for seamless communication and data aggregation between fabless houses, foundries, and OSATs.

At the industry level, new standards and 3D IC design kits—such as those developed by the CDX working group and industry partners—are emerging to address these challenges, forging a common language for describing 3D IC components, interfaces, and package architectures. These standards are vital for enabling reliable data exchanges and integration across diverse teams and supply chain partners.

Figure 2 Here is a view of a chiplet design kit (CDK) as per JEDEC JEP30 part model. Source: Siemens EDA

Programs such as TSMC’s 3Dblox initiative provide upfront placement and interconnection definitions, reducing ambiguity and fostering tool interoperability.

Digital twin and predictive multi-physics

The digital twin concept extends multi-physics analysis throughout the entire product lifecycle. Maintaining an accurate digital representation—from transistor-level detail up to full system integration—enables predictive simulation and optimization, accounting for interactions down to the package, board, or even system level. By transferring multi-physics results between levels of abstraction, teams can verify that chiplet behavior under thermal and mechanical loads accurately predicts final product reliability.

Figure 3 A digital twin extends multi-physics analysis throughout the entire product lifecycle. Source: Siemens EDA

For 3D ICs, chiplet electrical models must be augmented by multi-physics data captured from stack-level simulations. Back-annotating temperature and stress outcomes from package-level analysis into chiplet netlists provides the foundation for more accurate system-level electrical simulations. This feedback loop is becoming a critical part of sign-off, ensuring that each chiplet performs within its operational window in the assembled system.

Keeping it cool

Thermal management is the single most important consideration for die-to-die interfaces in 3D ICs. The vertical proximity of active dies can lead to rapid heat accumulation and risks, such as thermal runaway, where ongoing heat generation further degrades electrical performance and creates mechanical stress from varying thermal expansion rates in different materials. Differential expansion between materials can even warp dies and threaten the reliability of interconnects.

To enable predictive design, the industry needs standardized “multi-physics Liberty files” that define temperature and stress dependencies of chiplet blocks, akin to the Liberty files used for place-and-route in 2D design. These files will allow designers to evaluate whether a chiplet within the stack stays within its safe operating range under expected thermal conditions.

Multi-physics analysis must also support back-annotation of temperature and stress information to individual chiplets, ensuring electrical models reflect real operating environments. While toolchains for this process are evolving, the trajectory is clear: comprehensive, physics-aware simulation and data exchange will be integral to sign-off for 3D IC design, ensuring reliable operation and optimal system performance.

Shaping the future of 3D IC design

The journey into 3D IC technology marks a transformative period for the semiconductor industry, fundamentally reshaping how complex systems are designed, verified, and manufactured. 3D IC technology marks a leap forward for semiconductor innovation.

Its success hinges on predictive, early multi-physics analysis and collaboration across the supply chain. Establishing common standards, enabling system-level optimization, and adopting the digital twin concept will drive superior performance, reliability, and time-to-market.

Pioneers in 3D IC design—across EDA, semiconductor and system developers—are moving toward unified, system-level platforms that allow designers to iterate and optimize multi-physics analyses within a “single cockpit” environment that allows designers to optimize and iterate across different types of multi-physics analyses.

Figure 4 The Innovator3D IC solution provides the single, integrated cockpit 3D IC designers need. Source: Siemens EDA

With continued advances in EDA tools, methodologies and collaboration, the semiconductor industry can unlock the full promise of 3D integration, delivering the next generation of electronic systems that push the boundaries of capability, efficiency, and innovation.

Todd Burkholder is a senior editor at Siemens DISW. For over 30 years, he has worked as editor, author, and ghost writer with internal and external customers to create print and digital content across a broad range of high-tech and EDA technologies. Todd began his career in marketing for high-technology and other industries in 1992 after earning a Bachelor of Science at Portland State University and a Master of Science degree from the University of Arizona.

Tarek Ramadan is applications engineering manager for the 3D-IC Technical Solutions Sales (TSS) organization at Siemens EDA. He drives EDA solutions for 2.5D-IC, 3D-IC, and wafer level packaging applications. Prior to that, Tarek was a technical product manager in the Siemens Calibre design solutions organization. Ramadan holds BS and MS degrees in electrical engineering from Ain Shams University, Cairo, Egypt.

John Ferguson brings over 25 years of experience at Siemens EDA to his role as senior director of product management for Caliber 3D IC solutions. With a background in physics and deep expertise in design rule checking (DRC), John has been at the forefront of 3D IC technology development for more than 15 years, witnessing its evolution from early experimental approaches to today’s production-ready solutions.

Related Content

• Putting 3D IC to work for you
• Making your architecture ready for 3D IC
• The multiphysics challenges of 3D IC designs
• Advanced IC Packaging: The Roadmap to 3D IC Semiconductor Scaling
• Automating FOWLP design: A comprehensive framework for next-generation integration

The post Mastering multi-physics effects in 3D IC design appeared first on EDN.

CORNERSTONE Photonics Innovation Centre (C-PIC) — the UK’s dedicated Innovation and Knowledge Centre (IKC) for silicon photonics (affiliated with the University of Southampton and the University of Glasgow, as well as the UK government’s Science and Technology Facilities Council) — has partnered with Future Worlds (the University of Southampton’s startup accelerator) to launch a dedicated Silicon Photonics Stream at a Future Worlds Bootcamp on 29–30 November...

A research team led by the School of Engineering of The Hong Kong University of Science and Technology (HKUST) is said to have set a record efficiency level for red quantum rod light-emitting diodes (QR-LEDs), which could be applied to boost color vividness and brightness in next-generation display and lighting technologies for smartphones and TVs (Liao Zebing et al, ‘Inverted Device Engineering for Efficient and Bright Quantum Rod LEDs’, Advanced Materials...

Адаптаційні курси: для кого, для чого, і що на них вивчають Інформація КП пн, 11/10/2025 - 11:11

Gallium nitride (GaN) power IC and silicon carbide (SiC) technology firm Navitas Semiconductor of Torrance, CA, USA has entered into a definitive securities purchase agreement for the purchase and sale of 14,814,813 shares of Class A common stock at a purchase price of $6.75 per share. The private placement is expected to close on or about 10 November, subject to customary closing conditions. Needham & Company is acting as the sole placement agent...

Вітаємо команду ІСЗЗІ із здобуттям срібла на престижних кіберзмаганнях! kpi пн, 11/10/2025 - 10:36