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Frontgrade has successfully screened its GaN DC/DC converter and complementary EMI filter to MIL-PRF-38534 Class L requirements. Under the Defense Logistics Agency’s specification, Class L screening ensures these devices meet stringent performance requirements for space missions, from Low Earth Orbit (LEO) to Geostationary Earth Orbit (GEO).

The 51028xxx series of 28-V single-stage converters uses GaN FET technology for efficient power conversion, achieving 93% efficiency at half load. With faster switching and enhanced performance, the GaN-based devices respond quickly to dynamic power demands and provide multiple voltage outputs from 0.8 V to 12.0 V. Direct power conversion from the bus to the point of load ensures optimal performance for both current and future space applications.

Frontgrade’s 51028xxx converters are efficient isolated step-down regulators rated at 50 W, with a total dose radiation tolerance of 50 krads (Si) and immunity to SEL/SEB/SEGR up to 60 MeV-cm²/mg. Output voltage remote sense provides accurate point-of-load voltage regulation.

Flight and engineering modules, along with evaluation test boards, are available to support development, testing, and deployment in mission-critical spacecraft systems.

51028xxx series product page

Frontgrade Technologies

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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With the exponential growth of AI computing needs, challenges arise in performance and energy efficiency across computing, memory, power supply and the interconnections linking them. STMicroelectronics of Geneva, Switzerland says that it is helping hyperscalers, and the leading optical module provider, to overcome these challenges by unveiling its next generation of proprietary technologies for higher-performing optical interconnect in data centers and AI clusters. Its new silicon photonics and next-gen BiCMOS technologies are scheduled to ramp up from second-half 2025 for 800Gb/s and 1.6Tb/s optical modules...

💥 Стартап-школа Sikorsky Challenge розпочала прийом заявок kpi чт, 02/20/2025 - 16:39

In today’s world, motors are ubiquitous, powering everything from household appliances to industrial machinery. The importance of optimizing motor control for energy efficiency cannot be overstated, given that motors account for a significant portion of global energy consumption. This article delves into the structure of motors, the use of variable frequency drives (VFDs), and the solutions for motor control applications, including hardware support and advanced algorithms.

The prevalence of motors

Motors are integral to our daily lives, found in household appliances like washers, dryers, dishwashers, and pool pumps. They are also essential in automotive applications, with modern cars containing anywhere from 40 to 100 motors, depending on the model and trim level. Industrial environments are heavily reliant on motors, particularly in robotics and factory automation. Figure 1 shows the range of motor applications from household appliances to automotive and industrial.

Figure 1 The range of applications involving motors highlights the prevalence of this technology and thus the importance of considering their energy consumption and efficiency. Source: Microchip

According to the Energy Information Administration, approximately 50% of global energy consumption is attributed to motors. In industrial applications, this figure can exceed 80%. For instance, in the United States, the total energy consumption in 2022 was 4.07 trillion kilowatt-hours, equating to a daily consumption of 11.2 billion kilowatt-hours. Improving motor efficiency by just 1% could save 56 million kilowatt-hours of energy daily.

Key trends in motor efficiency

Figure 2 shows the four avenues to improve motor efficiency: energy efficiency motors, the use of drives and better electronics, advanced algorithms, and the integration of IoT. This section will touch upon these four topics and go into more detail.

Figure 2 The four avenues to improve motor efficiency: energy efficiency motors, the use of drives and better electronics, the integration of IoT, and advanced algorithms. Source: Microchip

Energy efficient motors

One of the primary trends in motor efficiency is the transition from traditional motors, such as AC induction motors, to more efficient types like brushless DC (BLDC) motors, permanent magnet synchronous motors (PMSM) and interior permanent magnet (IPM) motors. These motors offer higher efficiency and improved performance. Additionally, advancements in materials, such as the use of amorphous metals and rare earth magnets, have further enhanced motor efficiency.

Material advancements

In the realm of motor technology, advancements in materials and design have significantly enhanced the efficiency and performance of motors over the past century. As shown in Figure 3, a motor typically consists of end bells, a rotor, bearings, and a stator with windings.

Figure 3 The basic structure of a motor where rotor and stator coils materials have shifted from aluminum to copper. Source: Microchip

Over the years, the materials used in these components have evolved. For instance, the transition from aluminum to copper in the rotor and stator coils has improved conductivity and efficiency. Additionally, advancements in manufacturing tolerances have reduced noise and further increased efficiency.

One notable trend in motor technology is the use of amorphous materials in rotors and stators. Traditionally, silicon steels were used, but they had high eddy current and hysteresis losses. These are now being replaced by amorphous materials like metallic glasses, which have lower losses and thus higher efficiency.

For permanent magnet motors, stronger magnets, such as those made from rare earth materials like neodymium, iron and boron, provide more torque and efficiency. However, due to sustainability concerns, alternatives like aluminum, nickel, chromium, and ferrite-based magnets are being explored for their good properties over a range of temperatures and strong magnetic fields.

Motor structure

The transition from journal bearings to ball bearings has played a significant role in reducing friction and improving tolerances, thereby enhancing motor efficiency. Over the past century, motors have become considerably smaller while maintaining the same power output. As shown in Figure 4, a modern 5-horsepower, squirrel-cage rotor, three-phase induction electric motor (SCIM) is substantially smaller and weighs approximately 20% of what a motor with the same power rating did in 1910. This reduction in size can be attributed to the use of lighter and more efficient materials, as well as advancements in thermal and electrical insulation.

Figure 4 A timeline of the reduction in mass for a 3.7 kW SCIM motor from 1910 to 2020. Source: Hitachi

Lighter motors are particularly beneficial for automotive applications, where reducing weight can lead to increased efficiency and the ability to integrate motors into more compact spaces. As we continue to explore new materials and designs, the potential for even greater efficiency and performance in motor systems remains promising.

Variable frequency drives

Variable frequency drives (VFDs) have become increasingly popular for controlling motor speed and improving efficiency. VFDs adjust the motor’s speed to match the load requirements, reducing energy consumption. The transition from insulated gate bipolar transistors (IGBTs) to silicon carbide (SiC) and gallium nitride (GaN) technology in VFDs has also contributed to higher efficiency and faster switching.

VFD impact

Variable Frequency Drives (VFDs) have revolutionized motor control by allowing precise control over motor speed and torque. This technology optimizes motor performance and significantly improves system efficiency. A VFD adjusts the frequency and voltage supplied to the motor, enabling it to operate at the most efficient point for a given load.

For instance, traditional motor systems often operate at full power, with flow rates controlled by throttling valves, leading to substantial energy losses. In contrast, VFDs eliminate the need for throttling by adjusting the motor speed to match the required flow rate, thereby reducing energy consumption and increasing overall system efficiency. As shown in Figure 5, studies have shown that switching to a VFD can more than double the efficiency of a motor system, from around 31% to 72%.

Figure 5 Switching to a VFD can more than double the efficiency of a motor system, from around 31% to 72%. Source: [1]

Motor control hardware

As shown in Figure 6 a range of power management devices are necessary to effectively benefit from VFDs.

Figure 6 Basic block diagram of supporting power management devices for motor control. Source: Microchip

AC-DC converters utilizing SiC in tandem with gate drivers enable precision switching for efficient power conversion. MCUs with motor-specific peripherals and specialized algorithms, e.g. dsPIC33 digital signal controllers (DSCs), can be optimized to convert DC to variable AC. Finally, integrated sensors offer real-time feedback on current, voltage and temperature, enhancing system reliability.

Advanced control algorithms

Traditional methods, such as V/F control for AC induction motors, are cost-effective and straightforward but may not offer the highest efficiency. More advanced algorithms, such as six-step commutation for BLDC and PMSM motors, can offer sensor or sensor-less precision torque control. Field-oriented control (FOC), for example, uses a single-cycle MAC with data saturation as well a zero overhead looping and barrel shifting for high performance speed, position, and torque control. Figure 7 shows a sample block diagram for FOC of a motor using the least FPGA resources to execute a full motor control algorithm.

Figure 7 The block diagram for modular sensorless BLDC motor control algorithm using coordinate rotation digital computer (CORDIC) with sine-cosine required for FOC of motors. Source: Microchip

The Zero-Speed/Maximum-Torque (ZS/MT) control algorithm is a new variation of the sensorless FOC algorithm that enables the adoption of sensorless control techniques in high-torque or low-speed motor control applications. ZS/MT eliminates the need for Hall effect sensors by using a reliable initial position detection (IPD) method based on high-frequency injection (HFI) to determine the exact rotor position at zero and low speeds, making it ideal for applications like drilling machines, garage door openers, automotive starters and e-bikes.

Integration with IoT and AI/ML

The integration of IoT and AI technologies has revolutionized motor control. Sensors are used to detect current, torque, and rotor position, among other parameters, information that is then fed to MCUs for processing. With the integration of ML, these systems can perform predictive maintenance by analyzing sensor data to predict potential motor failures or maintenance needs.

Predictive maintenance ensures that motors operate at peak efficiency and performance, reducing the likelihood of unexpected breakdowns. By continuously analyzing parameters such as current, torque and vibration, predictive maintenance ensures efficient motor operation and minimizes downtime. Systems can, for instance, employ a classification model to determine the operational state of a motor, identifying whether it is functioning normally or experiencing anomalies such as an unbalanced load or a broken bearing, by monitoring the quiescent current of the motor.

Optimizing motor control

Optimizing motor control for energy efficiency is crucial for reducing global energy consumption and improving the performance of various applications. By transitioning to efficient motors, utilizing VFDs, implementing advanced control algorithms and integrating IoT and AI technologies, significant energy savings can be achieved. As the demand for energy-efficient solutions continues to grow, advancements in motor control technology will play a vital role in meeting these needs.

Pramit Nandy is a product marketing manager at Microchip Technology Inc., focused on motor control applications. Nandy has been with Microchip since 2021 and his previous experience includes a product marking manger position with Onsemi. He holds a master’s degree in electrical engineering from Arizona State University.

Reference

1. T. de Almeida, F. J. T. E. Ferreira and D. Both, “Technical and economical considerations in the application of variable-speed drives with electric motor systems,” in IEEE Transactions on Industry Applications, vol. 41, no. 1, pp. 188-199, Jan.-Feb. 2005, doi: 10.1109/TIA.2004.841022.

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SemiQ Inc of Lake Forest, CA, USA — which designs, develops and manufactures silicon carbide (SiC) power semiconductors and 150mm SiC epitaxial wafers for high-voltage applications — has announced a family of three 1200V SiC full-bridge modules, each integrating two of the company’s rugged high-speed switching SiC MOSFETs with reliable body diode...

BluGlass Ltd of Silverwater, Australia — which develops and manufactures gallium nitride (GaN) blue laser diodes based on its proprietary low-temperature, low-hydrogen remote-plasma chemical vapor deposition (RPCVD) technology — has received an AUS$120,000 order for semi-custom GaN laser diode bar products from a repeat customer, the College of Optics and Photonics (CREOL) at the University of Central Florida...

📢 Курс «Інтенсив підготовки до НМТ-2025» від КПІ! kpi чт, 02/20/2025 - 12:09

День Героїв Небесної Сотні kpi чт, 02/20/2025 - 11:27

Dynamic random-access memory (DRAM) chips contain many other transistors besides the access transistor to enable full operation of the DRAM memory. These peripheral transistors must meet stringent requirements which preclude a ‘copy-paste’ of regular logic transistor process flows.

One critical requirement imposed by present DRAM chip architectures is the ability of the periphery to withstand thermal treatments at 550-600°C and above. While the first part of this article series focused on DRAM basics and peripheral circuits, this part will provide a detailed account of DRAM periphery, explaining different generations of thermally stable peripheral transistor technology ranging from planar high-k/metal-gate transistors to FinFETs.

DRAM periphery: From SiON-based gate stacks to high-k/metal gates

Until 2018, DRAM peripheral transistors were predominantly made in planar logic MOSFET technology with poly-Si/SiO2 or poly-Si/SiON gates. These technologies were less advanced than the transistors used for high-performance logic in order to maintain the DRAM cost-per-bit trendline.

However, an improved technology for the periphery became necessary to keep pace with the performance enhancement enabled by subsequent generations of DRAM memory. The most obvious candidate was moving to a planar transistor architecture with a high-k/metal-gate stack—a transition that occurred as early as 2007 in the high-volume manufacturing of logic technologies.

Since about 2007, imec, together with its partners, has actively explored a DRAM-compatible version of high-k/metal-gate transistors and proposed multiple material and integration options to the memory industry. Today, almost every device with a DRAM memory inside contains a planar peripheral transistor technology with high-k/metal gates, which imec has been pioneering for more than 15 years.

Below is a grasp of some of the proposed material, module, and integration options, all differing in fabrication complexity and performance levels.

High-k/metal-gate integration: Thermally stable gate-first and gate-last integration flows

One of the solutions demonstrated by imec for potential early introduction was based on a gate-first integration approach, in which the metal gate is deposited before the high-temperature source/drain junction activation anneal. Gate stacks for nMOS and pMOS can be optimized separately by using different work function metals and layer thicknesses for the high-k/metal-gate stack (for example, TiN/Mg/TiN for n; TiN for p).

One of the critical parameters is obtaining an effective work function that is low enough for nMOS and high enough for pMOS to ensure a good Ion/Ioff ratio. Researchers achieved this by doping the gate stacks (with different dopants for pMOS and nMOS), which enabled a shift in the threshold voltages.

The choice of the dopant materials and their integration also provided a knob for improving the thermal stability of the gate stack and enabling the different Vth required by the DRAM chip. The DRAM-specific requirement for low gate leakage was addressed, among others, by adopting thicker gate stacks compared to logic-oriented solutions.

Figure 1 Sketch of the critical fabrication steps is shown in a gate-first integration approach for planar high-k/metal-gate peripheral transistors. Source: PSS

Imec also successfully demonstrated a thermally improved version of a gate-last integration approach, also called replacement metal gate (RMG) flow. In a gate-last flow, a poly-Si capped dummy gate is deposited and remains in place until the junction activation anneal is applied. After that, the dummy poly is replaced by the target metal gate.

Optimized source/drain junctions

Source/drain junctions are critical to ensure the functionality of MOSFET transistors. They are formed by creating a dopant gradient in the source/drain areas. As conduction channel lengths continued to shrink, ultra-shallow junctions became indispensable to ensure good electrostatic control over the channel. However, for peripheral transistors, the thermal treatments during DRAM memory anneal trigger an unwanted diffusion of the dopants, requiring more complex process flows to maintain the dopant gradient.

This issue can be addressed by changing the junction implant scheme using, for example, pre-amorphization implants and junction co-implants. Imec demonstrated several sets of optimized junctions suited for various threshold voltage targets.

A thermally stable silicide process

A general challenge for all transistors is to keep the source/drain contact resistance as low as possible. Source/drain contacts are formed by bringing a metal in contact with the source/drain regions, creating a Schottky barrier at the interface.

To ensure low resistance, two techniques are typically applied: (1) heavy doping of the source/drain regions and (2) complete silicidation of the source/drain areas—the silicides being formed through the reaction of the contact metal with the doped Si.

However, Ni(Pt) silicide, traditionally used in logic devices, cannot withstand the DRAM-related anneal temperatures. Imec proposed a thermally stable NiPt-based silicide module with low contact resistance by implementing additional implants and annealing steps for silicide stabilization.

Thermally stable, FinFET-based peripheral platform

Applications like automotive, artificial intelligence (AI) and machine learning (ML) impose increasingly stringent requirements on DRAM memories, driving the need for faster, more reliable and power efficient peripheral transistors. One option is to retrace the path of ‘logic’ and move from planar high-k/metal-gate transistors to FinFETs.

The logic roadmap made this transition as early as 2011 after R&D clearly showed the superior performance of transistors with fin-shaped conduction channels: improved Ion/Ioff, better short channel control, higher drive current at reduced footprint (due to a higher effective width of the channel), and lower power consumption—while keeping cost under control. On top of that, the use of tall fins provides a way to reduce the threshold voltage mismatch, which can particularly benefit the DRAM sense amplifiers.

Just like for the planar versions, the DRAM-specific requirements preclude a copy-paste of FinFET process flows developed for regular logic. In response, imec developed a thermally stable FinFET-based peripheral technology platform with integrated modules optimized for DRAM. Multiple flavors with different performance-cost trade-offs have been proposed to the industry for their next-generation DRAM products.

Thermally stable gate-first and gate-last FinFET integration flows

In 2021, imec reported the first experimental demonstration of a thermally robust integration flow for FinFETs using an optimized gate-first approach for implementing the high-k/metal-gate stack. Compared to a traditional gate-first approach, the modified flow implements gate stacks with the same thickness and the same work function metal for both nMOS and pMOS. So-called Vth shifter materials are then diffused into the high-k dielectric to tune the effective work function of the nMOS and pMOS devices.

This modified gate-first approach reduces the gate asymmetry and enhances the thermal stability of the flow. By using this flow, the researchers demonstrated improved Ion/Ioff and short channel control over planar high-k/metal-gate counterparts. These metrics did not degrade after the DRAM-specific anneal. Flavors with taller fins (with up to 80-nm height) have also been developed, with improved threshold voltage mismatch and area gain.

Figure 2 Example of a fabricated high-k/metal-gate fin displays transmission electron microscope (TEM) cross sections for 40-nm, 65-nm, and ~80-nm tall fins. Source: imec

A drawback of the gate-first integration approach is the relatively high threshold voltage, which originates from the impact of the high-temperature anneal on the gate stack during junction activation. This issue can be solved using a gate-last (or RMG) integration approach, which, however, comes with additional process steps. At IEDM in 2022, imec showed a thermally stable version of a FinFET gate-last flow.

Figure 3 The above image shows a selection of relevant process step for the proposed gate-last process flow for thermally stable FinFETs. Source: 10.1109/IEDM45625.2022.10019422

An optimized and thermally stable gate-last FinFET flow with a Mo-based work function metal for pMOS

Typical for a gate-last flow is the use of different work function metals for nMOS and pMOS devices. At VLSI in 2024, imec demonstrated the performance benefits of using a novel Mo-based work function metal for pMOS instead of the conventional TiN-based approach. The new gate stack module was successfully integrated into a gate-last FinFET flow and proven to be thermally stable.

The DRAM-compatible flow with integrated Mo-based p-work function metal yielded sufficiently low Ioff current and low threshold voltage (0.12 V) for the pMOS devices. The FinFETs were also benchmarked against a thermally stable planar high-k/metal-gate reference, showing a three times higher Ion (at target Ioff) for the same Si footprint. These results make the thermally stable gate-last FinFET flow a valuable candidate for sub-10 nm DRAM peripheral logic.

Figure 4 On left and middle are TEM images across fins on a ring oscillator and on right is elemental mapping across gate (EDS) showing CMOS patterning and decent conformality of the Mo-based p-work function metal stacks. Source: VLSI 2024

Thermally stable Nb-based metal contacts with low contact resistance

In earlier work on planar high-k/metal-gate based peripheral transistors, imec researchers lowered the source/drain contact resistance by improving the dopant profile and adding pre-amorphization implants. At IEDM in 2024, imec introduced a different approach: replacing the conventional Ti contact metal with Nb for pMOS devices.

The thermal stability of the Nb-based contact module was demonstrated for the first time. In addition, superior performance was observed when integrated into the gate-last FinFET platform: record low contact resistance, reduced overall parasitic resistance, and improved Ion.

Figure 5 The above chart shows a comparison of the contact resistivities of Ti- and Nb-based contact modules (different thicknesses) for before and after DRAM anneal. Source: IEDM 2024

Ahead of DRAM mass production

Imec pioneered peripheral transistor technology 10 years ahead of the industry’s mass production introduction. In its most recent R&D work, imec demonstrated an industry-relevant, thermally stable FinFET-based platform to meet the requirements for sub-10 nm DRAM. Multiple flavors have been developed as possible solutions for next-generation DRAM products, providing different levels of fabrication complexity and transistor performance.

More disruptive concepts are envisioned in the longer term to continue the DRAM scaling path. One of these is building the periphery on a separate wafer and integrating it with the memory array using advanced wafer bonding techniques. Although this approach comes with additional process steps, a true benefit is the relaxed requirement for thermal stability, as the periphery is now manufactured separately from the memory array.

Imec recently initiated R&D work on peripheral transistors for this new DRAM architecture, guided by insights obtained from planar and FinFET-based technology.

Alessio Spessot, technical account director, has been involved in developing advanced CMOS, DRAM, NAND, emerging memory array, and periphery during his stints at Micron, Numonyx, and STMicro.

Naoto Horiguchi, director of CMOS device technology at imec, has worked in Fujitsu and the University of California Santa Barbara while being involved in advanced CMOS device R&D.

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