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I recently published a Design Idea (DI) showing some very simple circuits for PWM programming of standard regulator chips, both linear and switching, “Revisited: Three discretes suffice to interface PWM to switching regulators.”

Figure 1 shows one of the topologies “Revisited” visited, where:

R1 = recommended value from U1 datasheet
DF = PWM duty factor = 0 to 1
R2 = R1/(Vomax/Vsense – 1)
Vout = Vsense(R1/(R2/DF) + 1) = DF(Vout_max – Vsense) + Vsense
DF = (Vout/Vsense – 1)(R2/R1) = (Vout – Vsense)/(Vout_max – Vsense)
DF = (Vout – 0.8)/9.2 for parts shown

Figure 1 Five discrete parts comprise a circuit for linear regulator programming with PWM.

Wow the engineering world with your unique design: Design Ideas Submission Guide

An inherent limitation of the Figure 1 circuit is its inability to program Vout < Vsense. Its minimum

Vout = Vsense @ DF = 0. For most applications this doesn’t amount to much, if any, of a problem. But sometimes it would be useful, or at least convenient, for Vout to be zero (or thereabout) when DF = zero. Figure 2 shows an easy modification that can make that happen, where:

R1 and R2 chosen as in Figure 1
(R4 + R5/2) = (5v – Vsense)/(Vsense/R1) – R2
R5 ~ R4/5
Vout = R1 DF(Vsense(1/R2 + 1/R1)) = DF Vout_max
DF = Vo/(R1(Vsense(1/R2 + 1/R1)) = Vout/Vout_max
DF = Vout/10 for part values shown

Figure 2 In order to make Vout programmable down to zero volts, add R4 and (optionally) R5 trimmer.

A cool feature of the Figure 1 topology is that, unlike some other schemes for digital power supply control, only the precision of R1, R2, and the regulator’s own internal voltage reference determines regulation accuracy. Precision is wholly independent of external voltage references. It remains equal to the precision of R1, R2, and Vsense (e.g., ±1%) for all output voltages.

Unfortunately, as the ancient maxim says, something’s (usually) lost when something’s gained. In gaining Vout < Vsense capability, the Figure 2 circuit loses that feature, and for outputs less than full scale, Vout precision becomes somewhat dependent on the +5v rail. This is where the R5 trimmer comes in handy. 

The design equation (R4 + R5/2) = (5v – Vsense)/(Vsense/R1) – R2, makes the values chosen for the R4, R5 pair dependent on the accuracy of the 5v rail. They can only be as correct as it is. This makes output voltages somewhat suspect, especially when they approach zero. Including R5 and adjusting it for Vout = 0 @ DF = 0 makes low Vout settings accurately programmable. If that isn’t a critical factor, then R5 can be omitted, just make R4 = (5v – Vsense)/(Vsense/R1) – R2.

The simplicity of the arithmetic for computing DF from the desired Vout is also a desirable feature of Figure 2.

In closing: This DI revises an earlier submission: “Three discretes suffice to interface PWM to switching regulators.” My thanks go to comment makers oldrev, Ashutosh Sapre, and Val Filimonov for their helpful advice and constructive criticism. And special thanks go to editor Shaukat for her creation of an environment friendly for the DI teamwork that made it possible.

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

Related Content

• Revisited: Three discretes suffice to interface PWM to switching regulators
• Three discretes suffice to interface PWM to switching regulators
• Cancel PWM DAC ripple with analog subtraction
• Add one resistor to allow DAC control of switching regulator output

The post Simple PWM interface can program regulators for Vout < Vsense appeared first on EDN.

🚀 Запрошуємо на «День вступника. Відчуй КПІ!» kpi ср, 06/18/2025 - 15:47

What are signal-conditioning aspects for amplifiers that design engineers must grasp for precision applications? What are the design considerations for selecting and implementing a signal-conditioning solution for a Wheatstone bridge sensor? Here is a technology brief on instrumentation amplifiers (INAs) and ASSPs carrying out Wheatstone bridge measurements. It covers areas such as intrinsic noise, gain drift, nonlinearity, and diagnostics.

Read the full article at EDN’s sister publication, Planet Analog.

Related Content

• Signal conditioning for high-impedance sensors
• What’s behind signal conditioner growth in sensors
• Conditioning network delivers precision for sensor calibration
• Using a strain-gauge transducer in a Wheatstone-bridge configuration
• Design solutions: Latest MEMS and sensor signal conditioning architectures

The post Wheatstone bridge measurements with instrumentation amplifiers appeared first on EDN.

Focus Is on Protecting Critical Markets Such as Automotive, Industrial IoT, and Secure Infrastructure

CEA-Leti and Soitec announced a strategic partnership to enhance the cybersecurity of integrated circuits (ICs) through the innovative use of fully depleted silicon-on-insulator (FD-SOI) technologies. This collaboration aims to position FD-SOI as a foundational platform for secure electronics by leveraging and extending its inherent resistance to physical attacks.

At the heart of the initiative is a joint effort to experimentally validate and augment the security benefits of FD-SOI—from the substrate level up to circuit design. The project aims to deliver concrete data, practical demonstrations, and roadmap guidance to meet the surging cybersecurity demands in critical markets such as automotive, industrial IoT, and secure infrastructure.

Combining Expertise to Secure the Future of Electronics

The partnership, which will utilize GlobalFoundries’ advanced chip manufacturing capabilities, will address a growing need for trusted components in embedded and cyber-physical systems—systems that must deliver security services and withstand both software- and hardware-level attacks. With FD-SOI’s proven advantages against laser fault injection (LFI) attacks due to its thin-film architecture and channel isolation, the technology presents a compelling foundation for next-generation secure IC design.

Key goals of the partnership include:

• Highlighting FD-SOI’s existing strengths in cybersecurity.
• Co-developing innovations across the substrate-design stack to boost physical robustness and meet security requirements in automotive and other embedded systems.
• Demonstrating empirical security data to reinforce FD-SOI’s credibility in certification contexts such as SESIP and Common Criteria.

Context: Rising Threats, Rising Demand

“In an era marked by increasing attacks on connected systems and autonomous vehicles, the need for embedded hardware capable of resisting physical tampering has never been greater,” said CEA-Leti CTO Jean-René Lequepeys. “FD-SOI’s unique combination of performance, energy efficiency, and attack resistance offers an ideal answer for industries that demand both trust and efficiency. This project will leverage research results from the FAMES Pilot Line.”

FD-SOI’s critical benefits include:

• Physical attack resistance, enabled by electrical isolation between the channel and substrate.
• Power-performance optimization, vital for battery-constrained applications like automotive ECUs and industrial sensors.
• Security design enablement, allowing tailored countermeasures such as fault detection and isolation of sensitive circuit domains.

Long-Term Vision: Toward a New Cyber-Substrate

While the initial phase focuses on leveraging existing FD-SOI capabilities, the project sets the stage for long-term innovation. The envisioned next-generation cyber-substrate would expand upon FD-SOI’s strengths by incorporating:

• Enhanced protection against backside and invasive physical attacks.
• Embedded anti-tamper features and physical unclonable functions (PUFs) for hardware fingerprinting.
• Dynamic response mechanisms to detect and counter emerging threats.

This future-oriented work will address both cyber and supply-chain vulnerabilities—making FD-SOI not only more secure, but also more indispensable.

Soitec’s Senior Executive Vice President in charge of Innovation and Chief Technology Officer Christophe Maleville said: “This partnership with CEA-Leti reflects our strategic ambition to position FD-SOI as a reference platform for secure and energy-efficient electronics. By combining our substrate innovation capabilities with CEA-Leti’s research excellence, we aim to demonstrate the full potential of FD-SOI in addressing today’s most pressing security challenges. Together, we are paving the way for a new generation of trusted technologies that are essential to the future of connected systems.”

The post CEA-Leti and Soitec Announce Strategic Partnership to Leverage FD-SOI for Enhanced Security of Integrated Circuits appeared first on ELE Times.

Delta Electronics India, a leading provider of power management and smart green solutions, has signed three Memorandums of Understanding (MOU) with KP Group, a prominent renewable energy conglomerate based in Surat. Under the agreements, Delta plans to provide its high-efficiency solar PV inverters, battery energy storage systems (BESS), green hydrogen energy systems, and EV charging infrastructure to KP Group’s projects across India and abroad, including approximately 1 GW of next-generation grid-connected solar PV inverters over the next 12 months.

Speaking on the occasion, Mr. Niranjan Nayak, MD of Delta Electronics India, said, “Delta Electronics India and KP Group already share a long-standing relationship. This new collaboration is a step further and a strong testament to the trust and shared values between Delta and KP Group, such as sustainability, innovation, and reliability. With this 1 GW PV inverter partnership and extended collaboration on BESS and green hydrogen, we are committed to delivering best-in-class technology and lifecycle support to support India’s decarbonization journey.”

Mr. Farukh Patel, Chairman and Managing Director of KP Group, said, “We are proud to partner with Delta Electronics India, a company that exemplifies innovation, reliability, and vision in clean technology. Our partnership is not just about products—it’s about co-creating solutions that empower India’s energy independence. Whether it is solar, storage, or hydrogen, we believe our combined strengths can build a cleaner, more sustainable tomorrow.”

Delta’s advanced solar PV inverters will feature high efficiency, cutting-edge grid support functionalities (e.g., voltage/frequency ride-through, reactive power support, low harmonic distortion), integrated smart monitoring, and remote diagnostics. They will also be future-ready, with hybrid compatibility for solar and storage integration. Delta will ensure strong after-sales support through preventive maintenance, rapid troubleshooting, spare parts support, and technical training tailored for KP Group’s operational teams. The two companies will also conduct regular joint technology workshops to ensure alignment with Delta’s latest innovations.

In view of India’s growing need for energy storage to support renewable integration and ensure grid stability, the BESS MOU outlines a detailed framework for developing and deploying scalable BESS projects. Delta will supply BESS systems, PV inverters, and energy management systems, along with design, integration, and commissioning support. Delta Will provide for advanced grid support features, as well as integrated smart monitoring and remote diagnostics for proactive maintenance.

KP Group will spearhead project development by leveraging its engineering, procurement, and construction (EPC) capabilities. Together, they will jointly deliver energy storage projects in India and potentially overseas markets. Delta will also offer post-installation services, including maintenance training, remote monitoring, and long-term operational support.

In a forward-looking step toward clean mobility, the third MOU focuses on integrated green hydrogen refueling and EV charging infrastructure. KP Group will lead the development of green hydrogen production plants powered by renewable energy. Delta will contribute critical technology including energy management systems, hydrogen compression and dispensing components, as well as EV charging hardware and software, such as power management, compression, and dispensing technologies), and integrated energy management systems. The two companies will jointly design and implement green hydrogen stations and EV charging hubs across India. Delta shall supply EV chargers, including AC and DC fast chargers, energy management systems, and software platforms for real time monitoring and billing. Additionally, the collaboration will focus on skills, with Delta also training KP Group’s teams for safe and efficient station operations.

Delta brings global experience in high-efficiency power electronics, hydrogen-ready infrastructure, and intelligent controls, while KP Group contributes a strong portfolio of land banks, clean energy infrastructure, and local execution expertise. Together, they aim to develop pilot hydrogen ecosystems that will serve industrial decarbonization, fuel substitution, and sustainable transportation.

All three collaborations are structured as long-term, non-exclusive agreements that allow both companies to maintain operational flexibility while jointly advancing key projects, allowing scope for innovation and customization.

The post Delta Electronics India Signs MOUs with KP Group to Power India’s Green Energy Transition appeared first on ELE Times.

Nearly 10,000 satellites currently circle our planet in low Earth orbit (LEO), delivering internet access, earth observation, communications, weather information, and more data back to Earth. Compared to traditional geostationary Earth orbit (GEO) systems, LEO satellites are launched in larger numbers to achieve sufficient coverage and operate in a less severe radiation environment. As such LEO satellites require different electrical components compared to their traditional GEO counterparts. To support the development of these applications, Infineon Technologies AG is introducing a new portfolio of radiation-tolerant memory products tailored for the rapidly growing NewSpace market.

NewSpace refers to the commercialization of space exploration by private companies and startups, often with less governmental oversight than traditional space programs. Driven by the rising demand for global connectivity (direct-to-cell), NewSpace initiatives aim to combine LEO satellite constellations with the Internet of Things (IoT) to create a more connected and efficient world. These missions typically rely on smaller satellites, ranging from nano-sats to 250 kg Sats, and are shorter in mission duration and less expensive, enabling the deployment of large-scale LEO constellations. With lower launch costs and reduced radiation exposure in LEO, many NewSpace applications can benefit from commercial off-the-shelf (COTS) components that deliver robust performance without requiring traditional military or aerospace qualifications.

Infineon’s NewSpace memory portfolio includes three product families: low-power, radiation-tolerant F-RAMs; QSPI NOR flash memories with 256 Mbit and 512 Mbit densities; and 256 Mbit/512 Mbit pseudo-static RAM (pSRAM). These devices offer an optimal combination of performance and reliability while supporting reduced size, weight, power, and cost benefits (SWaP-c). The F-RAMs operate across a wide MIL temperature range of
-55°C to +125 °C, while the NOR Flash and pSRAM devices support a range of -40°C to +125°C. Radiation tolerance demonstrates a total ionizing dose (TID) rating of 50 krad(Si) for the F-RAMs, 30 krad(Si) for the NOR Flash, and 100 krad(Si) for the pSRAM. Additional benefits include single lot date code and 100 percent electrical testing to ensure reliable mission operation. With these characteristics, Infineon’s memory products are ideal for short-duration, high-redundancy, and large-scale LEO constellations.

Infineon’s pSRAM are the first of their kind for NewSpace, offering a unique memory type, whose memory array is structured like DRAM internally but presents itself like static RAM (SRAM) externally. The pSRAMs are a low-power, high-performance, and low pin-count solution that is ideal for high-throughput data buffering applications.

Radiation-tolerant power solutions from IR HiRel complement memory offering

In addition to the NewSpace memory solutions, Infineon’s IR HiRel group offers a broad portfolio of radiation-tolerant power devices designed for the commercial space market. Combining decades of experience in both aerospace and automotive, the portfolio features highly reliable, cost-effective power MOSFETs optimized for 2-to-5-year LEO missions. Available in 60 V and 150 V N- and P-channel variants, these devices are qualified to AEC-Q101 and come in a rugged plastic package, with options for surface-mount and through-hole mounting. The devices are rated for a TID of 30 krad(Si), supporting radiation requirements of modern LEO missions.

The post Infineon introduces radiation-tolerant memory portfolio for low Earth orbit missions appeared first on ELE Times.

Eleven years ago, my wife and I experienced the aftereffects of our first close-proximity lightning blast here in the Rocky Mountain foothills, clobbering (among other things) both five-port and eight-port Gigabit Ethernet (GbE) switches, both of which ended up going under the teardown knife. The failure mechanism for the first switch ended up being non-obvious, in sharp contrast to the second, whose controller chip ended up with multiple holes blown in its package top:

One year (and a decade ago) later, lightning struck again. No Gigabit Ethernet switches expired this second time, although we still lost some other devices.

Fast forward to 2024, and…yep. This time four GbE switches ended up zapped failed, two of them eight-port and two more five-port (fate was apparently playing catch-up after previously taking a pass on switches). The former two will be showcased today, with the others following soon. Then there’s the three-bay NAS; you will have already have seen that teardown by the time this piece is published. And another CableCard receiver (we’re three for three on those), along with another MoCA transceiver…you’ll get teardowns of those in the near future, too.

Today’s dissection patients are from the same supplier—TRENDnet. They hail from the same product family generation. And, as you’ll soon see, although their outsides are (somewhat) dissimilar, their insides are essentially identical (given the naming and release date similarities, that’s not exactly a surprise). Behold the metal-case TEG-S82g (hardware v2.0r, to be precise):

which, per Amazon’s listing, dates from September 2004, and the plastic-case TEG-S81g (again, hardware v2.0r), also initially available that same month and year:

Let’s start with the metal-case TEG-S82g. Following up on the stock photos shown earlier, here are some views of my specific device, as usual accompanied by a 0.75″ (19.1 mm) diameter U.S. penny for size comparison purposes (the TEG-S82g has dimensions of 150 x 97 x 28 mm/5.9 x 3.8 x 1.1 in. and weighs 364 g/12.8 oz.). Front:

Left side:

This next one, of the device’s backside, begs for a bit more explanation. Port 8, the one originally connected to one of the two spans of shielded Ethernet cable running around the outside of the house, is unsurprisingly the one that failed (therefore the electric tape I applied to identify it).

The other ports actually still work, at least for the first minute or few after I power on the switch, but eventually all the front panel LEDs begin blinking and further functionality ceases:

Onward. Right side:

Top:

and bottom:

Here’s its “wall wart”:

Those screw heads you might have noticed on both device sides? They’re our pathway inside:

Here’s our first view of the PCB inside:

Four screws hold it in place. Let’s get rid of those next:

Let’s see what we’ve got here. At the bottom are the eight Ethernet ports, next to (at the bottom right) the DC input power connector. Thick PCB traces running from there to the circuitry cluster in the upper right quadrant suggest that the latter handles power generation for the remainder of the board. And above, each two-port combo is a Bi-TEK FM-3178LLF dual port magnetic transformer. Here’s the specific one (at far right) associated with failed port 8:

At the top edge are (at far right) the power LED, next to eight activity LEDs, one for each of the ports. And below them is the system’s “brains”, a Realtek RTL8370N 8-port 10/100/1000 switch controller. It may very well be the same as the IC in the 8-port switch teardown from 11 years ago, although I can’t say for sure, as that one had chunks of its packaging (therefore topside markings) blown away! That said, this design does use the same transformers as last time.

Here’s a close-up of the RTL8370N and the aforementioned circuitry to its right:

Now let’s flip the PCB over and have a look at its backside:

No obvious evidence of damage here, either. Here’s another port 8 area closeup (as I was writing this, I paused to revisit the hardware and confirm that those white globs are just dust):

Now for its plastic-case TEG-S81g sibling, with listed dimensions again 150 x 97 x 28 mm/5.9 x 3.8 x 1.1 in. (albeit this time tapered in the front), although the weight is (unsurprisingly, given the shift in case material construction) decreased this time around: 186 g/6.6 oz.:

This time, port 5 failed. The other seven ports remain fully functional to this very day, although for how much longer I can’t say; therefore, I’ve decided to retire it from active service, as well, in the interest of future-hassle avoidance:

The “wall wart” looks different this time, but the specs are the same:

No screws on the case sides this time, as you may have already noticed, but remove the four rubber “feet” on the underside:

and underneath the front two are visible screw heads.

You know what comes next:

And we’re in (with the tape still stuck to the top):

Let’s put that tape back in place so I can keep track of which port (5) is the failing one:

The earlier-shown two screws did double-duty, not only holding the two halves of the chassis together but also helping keep the PCB inside in place. Two more, toward the back, also need to be dealt with before the PCB can be freed from its plastic-case captivity:

That’s better:

Another set of closeups, first of the affected-port region:

and the bulk of the topside circuitry:

And now, flipping the PCB over, another set as before:

I hope you’ll agree with me on the following two points:

• The two PCBs look identical, and
• There’s no visually obvious reason why either one failed.

So then, what happened? Let’s begin with the plastic-case TEG-S81g. Truth be told, the tape on top of port 5 originally existed so that I could remember which port was bad down the road, after I pressed it back into service, and in the same “use it until it completely dies” spirit that prompted my recent UPS repair. That said, long-term sanity aspirations eventually overrode my usual thriftiness. My guess is that, given the remainder of the ports (and therefore the common controller chip that manages them) remain operational, port 8’s associated transformer got zapped.

And the metal-case TEG-S82g? Here, I suspect, the lightning-strike spike effects made it through the port 5 transformer, all the way to the Realtek RTL8370N controller nexus, albeit interestingly only with derogatory effects seemingly after the chip had been operational for a bit and had “warmed up” (note, as previously mentioned in the earlier eight-port GbE switch teardown, the lack of a heatsink in this design). As the block diagram in this RTL8370N datasheet makes clear, the chip is highly integrated, including all the ports’ MAC and PHY circuits (among other things).

~1,300 words in, that’s “all” I’ve got for you today. Please share your thoughts in the comments!

 —Brian Dipert is the Editor-in-Chief of the Edge AI and Vision Alliance, and a Senior Analyst at BDTI and Editor-in-Chief of InsideDSP, the company’s online newsletter.

Related Content

• UPS resurrection: Thriftiness strikes again
• Lightning strikes…thrice???!!!
• Devices fall victim to lightning strike, again
• Lightning strike becomes EMP weapon

The post A teardown tale of two not-so-different switches appeared first on EDN.

Materials, networking and laser technology firm Coherent Corp of Saxonburg, PA, USA has launched the SES18-880A-190-10, a high-power 880nm single-emitter laser diode on sub mount, designed specifically for high-efficiency, high-reliability pumping of diode-pumped solid-state (DPSS) lasers...

Discrete semiconductor and passive electronic component maker Vishay Intertechnology Inc of Malvern, PA, USA has partnered with Wales Tech Week 2025, which is taking place at the International Convention Centre (ICC) Wales in Newport on 24–26 November...

Пошкодження історичної будівлі kpi вт, 06/17/2025 - 12:35

This article is the second in a series from PDF Solutions on why adopting big data platforms will transform the compound semiconductor industry. The first part “Accelerating silicon carbide (SiC) manufacturing with big data platforms” was recently published on EDN.

Compound semiconductors such as SiC are revolutionizing industries with their ability to handle high-power, high-frequency, and high-temperature technologies. However, as they climb in demand across sectors like 5G, electric vehicles, and renewable energy, the manufacturing challenges are stacking up. The semiconductor sector, particularly with SiC, trails behind the mature silicon industry when it comes to adopting advanced analytics and streamlined yield management systems (YMS).

The roadblock is high defectivity levels in raw materials and complex manufacturing processes that stretch across multiple sites. Unlocking the full potential of compound semiconductors requires a unified and robust end-to-end yield management approach to optimize SiC manufacturing.

A variety of advanced tools, industry approaches, and enterprise-wide analytics hold the potential to transform the growing field of compound semiconductor manufacturing.

Addressing challenges in compound semiconductor manufacturing

While traditional silicon IC manufacturing has largely optimized its processes, the unique challenges posed by SiC and other compound semiconductors require targeted solutions.

• Material defectivity at the source

Unlike silicon ICs, where costs are distributed across numerous fabrication steps, SiC manufacturing sees the most significant costs and yield challenges in the early stages of production, such as crystal growth and epitaxy. These stages are prone to producing defects that may only manifest later in the process during electrical testing and assembly, leading to inefficiencies and high costs.

As material defects evolve during manufacturing, traceability is essential to pinpoint their origin and mitigate their impact. Yet, the lack of robust systems for tracking substrates throughout the process remains a significant limitation.

• Siloed data and disparate systems

Compound semiconductor manufacturing often involves multi-site operations where substrates move between fabs and assembly facilities. These operations frequently operate on legacy systems that lack standardization and advanced data integration capabilities.

Data silos created by disconnected manufacturing execution systems (MES) and statistical process control (SPC) tools hinder enterprises from forming a centralized view of their production. Without cross-operational alignment enabled by unified analytics platforms, root cause analysis and yield optimization are nearly impossible.

• Nuisance defects and variability

Wafer inspection in compound semiconductors reveals a high density of “nuisance defects”—spatially dispersed points that do not affect performance but can overwhelm defect maps. Distinguishing between critical and benign defects is critical to minimizing false positives while optimizing resource allocation.

Furthermore, varying IDs for substrates through processes like polishing, epitaxy, and sawing hamper effective wafer-level traceability (WLT). Using unified semantic data models can alleviate confusion stemming from frequent lot splits, wafer reworks, and substrate transformations.

How big data analytics and AI catalyze yield management

Compound semiconductor manufacturers can unlock yield lifelines by deploying comprehensive big data platforms across their enterprises. These platforms go beyond traditional point analytics tools, providing a unified foundation to collect, standardize, and analyze data across the entire manufacturing spectrum.

• Unified data layers

The heart of end-to-end yield management lies in breaking down data silos through an enterprise-wide data layer. By standardizing data inputs from multiple MES systems, YMSs, and SPC tools, manufacturers can achieve a holistic view of product flow, defect origins, and yield drop-off points.

For example, platforms using standard models like SEMI E142 facilitate single device tracking (SDT), enabling precise identification and alignment of defect data from crystal growth to final assembly and testing.

• Root cause analysis tools

Big data platforms offer methodologies like kill ratio (KR) analysis to isolate critical defect contributors, optimize inspection protocols, and rank manufacturing steps by their yield impact. For example, a comparative KR analysis on IC front-end fabs can expose the interplay between substrate supplier quality, epitaxy reactor performance, and defect propagation rates. These insights lead to actionable corrections earlier in production.

By ensuring that defect summaries feed directly into analytics dashboards, enterprises can visualize spatial defect patterns, categorize issues by defect type, and thus rapidly deploy solutions.

• Predictive analytics and simulation

AI-driven predictive tools are vital for anticipating potential yield crashes or equipment wear that can bottleneck production. Using historical defect patterns and combining them with contextual process metadata, yield management systems can simulate “what-if” outcomes for different manufacturing strategies.

For instance, early detection of a batch with high-risk characteristics during epitaxy can prevent costly downstream failures during assembly and final testing. AI-enhanced traceability also enables companies to correlate downstream failure patterns back to specific substrate lots or epitaxy tools.

• SiC manufacturing case study

Consider a global compound semiconductor firm transitioning to 200-mm SiC wafers to expand production capacity. By deploying a big data-centric YMS across multi-site operations, the manufacturer would achieve the following milestones within 18 months:

• Reduction of nuisance defects by 30% post-implementation of advanced defect stacking filters.
• Yield improvement of 20% via optimized inline inspection parameters identified from predictive KR analysis.
• Defect traceability enhancements enabling root cause identification for more than 95% of module-level failures.

These successes underscore the importance of incorporating AI and data-driven approaches to remain competitive in the fast-evolving compound semiconductor space.

Building a smarter compound semiconductor fabrication process

The next frontier for compound semiconductor manufacturing lies in adopting fully integrated smart manufacturing workflows that include scalability in the data architecture, proactive process control, and an iterative improvement culture.

• Scalability in data architecture

Introducing universal semantic models enables tracking device IDs across every transformation from input crystals to final modules. This end-to-end visibility ensures enterprises can scale into higher production volumes seamlessly while maintaining enterprise-wide alignment.

• Proactive process control

Setting an enterprise-wide baseline for defect classification, detection thresholds, and binmap merging algorithms ensures uniformity in manufacturing outcomes while minimizing variability stemming from site-specific inconsistencies.

• Iterative improvement culture

Yield management thrives when driven by continuous learning cycles. The integration of defect analysis insights and predictive modeling into day-to-day decision-making accelerates the feedback loop for manufacturing teams at every touchpoint.

Pioneering the future of yield management

The compound semiconductor industry is at an inflection point. SiC and its analogues will form the backbone of the next generation of technologies, from EV powertrains to renewable energy innovations and next-generation communication.

Investing in end-to-end data analytics with enterprise-scale capabilities bridges the gap between fledgling experimentation and truly scalable operations. Unified yield management platforms are essential to realizing the economic and technical potential of this critical sector.

By focusing on robust data infrastructures, predictive analytics, and AI integrations, compound semiconductor enterprises can maintain a competitive edge, cut manufacturing costs, and ensure the high standards demanded by modern applications.

Steve Zamek, director of product management at PDF Solutions, is responsible for manufacturing gata analytics solutions for fabs and IDMs. Prior to this, he was with KLA (former KLA-Tencor), where he led advanced technologies in imaging systems, image sensors, and advanced packaging.

 

Jonathan Holt, senior director of product management at PDF Solutions, has more than 35 years of experience in the semiconductor industry and has led manufacturing projects in large global fabs.

 

Dave Huntley, a seasoned executive providing automation to the semiconductor manufacturing industry, is responsible for business development for Exensio Assembly Operations at PDF Solutions. This solution enables complete traceability, including individual devices and substrates through the entire assembly and packaging process.

Related Content

• The Road to 200-mm SiC Production
• Silicon carbide (SiC) counterviews at APEC 2024
• Wolfspeed to Build 200-mm SiC Wafer Fab in Germany
• Silicon carbide’s wafer cost conundrum and the way forward
• Reducing Costs, Improving Efficiency in SiC Wafer Production with CMP

The post Unlocking compound semiconductor manufacturing’s potential requires yield management appeared first on EDN.

Акредитація освітніх програм КПІ ім. Ігоря Сікорського 2025/06/10 kpi пн, 06/16/2025 - 22:19

submitted by /u/AdEast7904 [link] [comments]

I don't feel creative today. Its an ancient tube amplifier from 1963, not working yet. First time working on something this old. All seems pretty straightforward, but I've done no research yet :) Got it from a thrift store. Known problems, before measuring anything: Missing knobs Power lightbulb floating inside the case Corroded fuses Power switch doesn't stay in place Rust and corrosion on the case BUT SHE'S SO PRETTY BRO Why didn't I measure anything yet? The 9v battery in my fluke died today [*] submitted by /u/Lovesexdreams420 [link] [comments]

Stephen Woodward, a prolific circuit designer with way more than 100 published Design Ideas (DIs), had his “80 MHz VFC with prescaler and preaccumulator” [1] published on October 17, 2024, as a DI on the EDN website. 

Upon reading his article, I was eager to simulate it and try to push its operation up to 100 MHz, if possible, while maintaining its basic simplicity and accuracy. However, Stephen Woodward got there before I did [2]! For the record, I had almost finished my design before I saw his latest one on the EDN website. 

I won’t discuss the details of the circuit operation because they are so similar to those of the above-referenced DIs. However, there are added features, and the functionality has been tested by simulation.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Features

My voltage-to-frequency converter (VFC) circuit (Figure 1) has a high impedance input stage, it can operate reliably beyond 100 MHz, it can be operated with a single 5.25-V supply (or a single 5-V supply with a few added components), and it has been successfully simulated. Also, adjustments are provided for calibration.

Figure 1 VFC design that operates from 100 kHz to beyond 100 MHz with a single 5.25-V supply, providing square wave outputs at 1/2 and 1/4 the main oscillator frequency.  

This circuit provides square wave outputs at one-half and one-fourth the main oscillator frequency. These signals will, in many cases, be more useful than the very narrow oscillator signal, which will be in the 2 ns to 5 ns range.

The NE555 (U8) provides a 500 kHz signal, which drives both a negative voltage generator for a -2.5-V reference and a voltage doubler used to generate a 5.25-V regulated supply that is used when a single 5-V supply is desired. TLA431As are used as programmable Zener diodes, NOT TL431As. Unlike the TL431A, the TLA431A is stable for all values of capacitance connected from the cathode to the anode.

Two adjustments are provided: Both a positive and a negative offset adjustment are provided by R11, and R9 adjusts the gain of the current-to-voltage converter, U2. I suggest using R11 to set the 100-kHz signal with 5 mV applied to the input and using R9 to set the 100-MHz signal with a 5-V input. Repeat this procedure as required to maximize the accuracy of the circuit.

Possible limitations

This circuit may not give highly accurate operation below 100 kHz because of diode and transistor leakage currents, but I expect it to  operate at the lower frequencies at least as well as Woodward’s circuits. Operation down to 1 Hz or 10 Hz is, in my opinion, mostly for bragging rights, and I am not concerned about that.

I expect this VFC to be useful mostly in the 100 kHz to 100 MHz frequency range: a 1 to 1000 span. Minute diode/transistor leakage currents in the nanoamp range and PCB surface leakage may cause linearity inaccuracies at the lower frequencies. The capacitor charging current provided by transistor Q1 is in the several microamps range at 100 kHz; below that, it is in the nanoamp range. Having had some experience with environmental testing, I think it would be difficult to build this circuit so that it would provide accurate operation below 100 kHz in an environment of humidity/temperature of 75%/50oC.   

Some details

When simulated with LTspice, the Take Back Half circuit [3] with 1N4148 diodes did not provide acceptable results above about 3.5 MHz when driven by a square wave signal with 2-ns rise/fall times, so I used Schottky barrier diodes instead, which worked well beyond 25 MHz, the maximum frequency seen by the Take Back Half circuit [1,3]. The Schottky diodes have somewhat higher leakage current than the 1N4148s, but the 1N4148 diodes would require the highest frequency signal to be divided down to 3.5 MHz to operate well in this application.

I used two 74LVC1G14s to drive C4, the ramp capacitor, because I was not convinced one of them was rated to continuously drive the peak or rms current required to reset the capacitor when operating at or near 100 MHz. And using a 25-pF capacitor instead of just using parasitic and stray capacitance allows better operation at low frequencies because leakage currents are a smaller percentage of the capacitor charging current. (Obviously, more ramp capacitance requires more charging current.)

The op-amp

If you want to use a different op amp, check the specs to be sure the required supply current is not greater than 3 mA worst case. Also, it must accommodate the necessary 7.75 V with some margin. Critically, the so-called rail-to-rail output must swing to within 100 mV of the positive rail with a 1.3-mA load at the maximum operating temperature.

Be advised

Look at renowned Jim Williams’ second version of his 1 Hz to 100 MHz VFC for more information about the effort required to make his circuit operate well over the full frequency range [4][5]. See reference 5 and look at the notes in Figure 1 and Table 1.

Jim McLucas retired from Hewlett-Packard Company after 30 years working in production engineering and on design and test of analog and digital circuits.

References/Related Content

1. 80 MHz VFC with prescaler and preaccumulator
2. 100-MHz VFC with TBH current pump
3. Take-Back-Half precision diode charge pump
4. Designs for High Performance Voltage-to-Frequency Converters
5. 1-Hz to 100-MHz VFC features 160-dB dynamic range

The post A simulated 100-MHz VFC appeared first on EDN.

Electronic identification (eID) documents are seeing growing demand worldwide as governments push ahead with their digitalization efforts. To meet these rapidly evolving requirements more quickly and flexibly, Infineon Technologies AG has introduced two new solutions: SECORA ID V2 and the eID-OS. These solutions offer local security printers and card manufacturers greater flexibility in selecting the right solution for their specific project requirements, while helping to reduce development time and accelerate deployment.

“Our broad range of solutions is a clear commitment to our customers and their individual, local requirements in the field of ID projects,” says Maurizio Skerlj, Senior Vice President and Product Line Manager for Authentication and Identity Solutions at Infineon Connected Secure Systems. “With our all-in-one solutions, including innovative packaging options such as our coil-on-module technology and our antenna design support, we enable our customers to get their products to market faster, develop a flexible solution to their specific requirements, and realize new applications.”

SECORA ID V2: improved security features and faster transaction speeds

SECORA ID V2 is the successor to the SECORA ID V1 Java Card solution for electronic ID and authentication applications in the public sector. The V2 version of SECORA ID increases transaction speed by up to 80 percent compared to its predecessor. It is based on a 40 nm hardware architecture and can transfer data at speeds of up to 6.8 MBit/s. This enables faster personalization and processing of ID documents and allows for quick and smooth identity checks at borders and security checkpoints. SECORA ID V2 is based on the latest Java Card 3.1 standard and supports biometric match-on-card functions to increase user data protection. Customers benefit from Infineon’s broad applet toolset. It also supports payment tools such as Visa, Mastercard, and Calypso as well as the crypto vision ePasslet Suite. This wide range of applets enables developers to easily integrate and quickly deploy highly customized ID solutions. Furthermore, the sandbox enables the integration of native code without compromising security standards. The SECORA ID V2 platform is Common Criteria EAL6+(high) certified and EMVCo approved.

Infineon eID-OS: Ready-to-use and low operating expenses

Infineon eID-OS is the latest addition to the portfolio of native solutions, combining the latest TEGRION security controller with a native operating system. Designed for basic ID application projects, it offers a performance- and cost-optimized solution with fast time-to-market. The standards-compliant solution is targeting CC EAL 5+ eMRTD (Common Criteria Evaluation Assurance Level for electronic Machine-Readable Travel Document) certification and is housed in advanced packaging technology. It optimizes the development process, enables rapid deployment, and reduces maintenance costs. Featuring a powerful 32-bit CPU, advanced cryptography accelerators, and the robust Integrity Guard 32 security architecture, eID-OS enables fast and secured transactions with processing times of less than 0.5 seconds. Thanks to simplified implementation, personalization, and administration, as well as a secured chain of trust and automatic data size detection, customers benefit from low total cost of ownership. In addition, Infineon’s ultra-thin contactless coil-on-module package supports thinner electronic data pages, reducing document costs and the carbon footprint. The space saved can alternatively be used for an additional security layer, making this solution ideal for modern eID projects.

The post Infineon expands government ID portfolio with SECORA ID V2 and eID-OS for enhanced flexibility and faster time-to-market appeared first on ELE Times.

Arrow Electronics has launched a dedicated online hub offering extensive resources for those seeking to understand the future of energy storage systems.

As the global shift towards renewable energy accelerates, battery energy storage systems (BESS) are becoming critical in revolutionising energy storage and management. BESS technology plays a vital role in integrating solar and wind power, enabling the electrification of vehicles, and providing reliable backup power, ultimately enhancing sustainability and resilience across various sectors.

The new energy storage systems resource page provides access to a range of valuable content, including a webinar on ‘Optimising Energy Storage: The Role of Advanced BMS,’ an informative e-book on BESS, essential design resources, insightful articles exploring key energy storage topics, such as photovoltaic integration and recordings of on-demand webinars, including ‘High-Power SiC MOSFETs Designed to Last.’

Arrow, in collaboration with eInfochips, is driving innovation in the BESS sector by offering leading-edge components, expert engineering support, and dependable supply chain solutions.

The post Arrow Electronics Launches Comprehensive Energy Storage Resource Hub appeared first on ELE Times.

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