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Designed to facilitate the continued evolution of high-frequency wireless systems in various market segments, the new DB0402 3dB 90° hybrid couplers provide repeatable high-frequency performance and continuous power handling in miniature, low-profile form factors compatible with automated assembly.

KYOCERA AVX released a new line of integrated thin film (ITF) hybrid couplers designed to facilitate the continued evolution of high-frequency wireless systems in industrial, automotive, telecommunications, and telemetry applications.

Hybrid couplers are special four-port directional couplers that split input signals into two equal-amplitude 3dB outputs whose phases are shifted by 90°. Many also support performance monitoring and inject signals without interrupting the original signal.

The new DB0402 3dB 90° hybrid couplers from KYOCERA AVX feature field-proven multilayer thin-film technology engineered to provide excellent high-frequency performance in microwave and RF bands spanning 3,000 to 4,100MHz and enable the quick adjustment of RF parameters. They also feature compact, rugged constructions that measure just 0.040” x 0.023” x 0.014” ±0.002” (L x W x H), enabling board space savings, and lead-free nickel terminations compatible with reflow, wave, vapor phase, and manual soldering techniques, enabling reliable automated assembly. Additional benefits include high power handling (1W continuous), low insertion loss (-0.5dB typical, -0.8dB max.), high isolation, exceptional amplitude and phase balance (0.6dB typical, 1.2dB max. and 2° typical, 5° max., respectively), temperature stability, linearity improvements, low parasitics, high part-to-part and lot-to-lot repeatability, excellent solderability, self-alignment during reflow, and effective heat dissipation.

The series is currently available in four frequency bands with typical performance of 3,200, 3,500, and 3,700, and 3,800MHz and is rated for 50Ω impedance and operating temperatures extending from -40°C to +85°C. It’s also compliant with International Automotive Task Force (IATF) and RoHS requirements, manufactured in ISO 9001 facilities, and packaged on tape and reel for automated assembly.

Ideal applications for the series extend throughout the industrial, automotive, telecommunications, and telemetry industries and include base stations, wireless LANs, mobile communications systems, 4G, 5G, and 6G LTE infrastructure, satellite TV receivers, global positioning systems (GPS), RF balanced amplifiers, signal distribution, heavy-duty radios, vehicle location systems, and other high-frequency wireless systems.

“The rapid evolution and expansion of 5G, SATCOM, and other high-frequency wireless technologies is fueling the evolution of enabling technologies, including millimeter wave and MIMO (multiple-input, multiple-output) antennas, which are empowered by innovative microwave and RF components, like our new 3dB, 90° hybrid couplers,” said Mohammed Abu-Naim, RF Product Manager, KYOCERA AVX – North America. “Our new hybrid couplers provide customers with space- and cost-saving solutions for maximizing repeatable, high-frequency RF performance in compact and handheld industrial, automotive, telecommunications, and telemetry applications with high power handling and wide operating frequency requirements.”

The post KYOCERA AVX Releases New 3dB Hybrid Couplers appeared first on ELE Times.

Single- and Dual-Core MCUs Combine Arm Cortex-M85 and M33 Cores with Arm Ethos-U55 NPU to Deliver Superior AI Performance up to 256 GOPs

• Unprecedented 7300+ CoreMarks with Dual Arm CPU coresTSMC 22ULL Process Delivers High Performance and Low Power Consumption
• Embedded MRAM with Faster Write Speeds and Higher Endurance and Retention
• Dedicated Peripherals Optimized for Vision and Voice AI plus Real-Time Analytics
• New AI Software Framework Eases Development and Enables Easy Migration with MPUs
• Leading-Edge Security Features Ensure Data Privacy

Renesas Electronics Corporation introduced the RA8P1 microcontroller (MCU) Group targeted at Artificial Intelligence (AI) and Machine Learning (ML) applications, as well as real-time analytics. The new MCUs establish a new performance level for MCUs by combining 1GHz Arm Cortex-M85 and 250MHz Cortex-M33 CPU cores with the Arm Ethos-U55 Neural Processing Unit (NPU). This combination delivers the highest CPU performance of over 7300 CoreMarks and AI performance of 256 GOPS at 500 MHz.

Designed for Edge/Endpoint AI

The RA8P1 is optimized for edge and endpoint AI applications, using the Ethos-U55 NPU to offload the CPU for compute intensive operations in Convolutional and Recurrent Neural Networks (CNNs and RNNs) to deliver up to 256 MACs per cycle that yield 256 GOPS performance at 500 MHz. The new NPU supports most commonly used networks, including DS-CNN, ResNet, Mobilenet TinyYolo and more. Depending on the neural network used, the Ethos-U55 provides up to 35x more inferences per second than the Cortex-M85 processor on its own.

Advanced Technology

The RA8P1 MCUs are manufactured on the 22ULL (22nm ultra-low leakage) process from TSMC, enabling ultra-high performance with very low power consumption. This process also enables the use of embedded Magnetoresistive RAM (MRAM) in the new MCUs. MRAM offers faster write speeds along with higher endurance and retention compared with Flash.

“There is explosive growth in demand for high-performance edge AIoT applications. We are thrilled to introduce what we believe are the best MCUs to address this trend,” said Daryl Khoo, Vice President of Embedded Processing Marketing Division at Renesas. “The RA8P1 devices showcase our technology and market expertise and highlight the strong partnerships we have built across the industry. Customers are eager to employ these new MCUs in multiple AI applications.”

“The pace of innovation in the age of AI is faster than ever, and new edge use cases demand ever-improving performance and machine learning on-device,” said Paul Williamson, senior vice president and general manager, IoT Line of Business at Arm. “By building on the advanced AI capabilities of the Arm compute platform, Renesas’ RA8P1 MCUs meet the demands of next generation voice and vision applications, helping to scale intelligent, context-aware AI experiences.”

“It is gratifying to see Renesas harness the performance and reliability of TSMC 22ULL embedded MRAM technology to deliver outstanding results for its RA8P1 devices,” said Chien-Hsin Lee, Senior Director of Specialty Technology Business Development at TSMC. “As TSMC continues to advance our embedded non-volatile memory (eNVM) technologies, we look forward to strengthening our long-standing collaboration with Renesas to drive innovation in future groundbreaking devices.”

Robust, Optimized Peripheral Set for AI

Renesas has integrated dedicated peripherals, ample memory and advanced security to address Voice and Vision AI and Real-time Analytics applications. For vision AI, a 16-bit camera interface (CEU) is included that supports sensors up to 5 megapixels, enabling camera and demanding Vision AI applications. A separate MIPI CSI-2 interface offers a low pin-count interface with two lanes, each up to 720Mbps. In addition, multiple audio interfaces including I2S and PDM support microphone inputs for voice AI applications.

The RA8P1 offers both on-chip and external memory options for efficient, low latency neural network processing. The MCU includes 2MB SRAM for storing intermediate activations or graphics framebuffers. 1MB of on-chip MRAM is also available for application code and storage of model weights or graphics assets. High-speed external memory interfaces are available for larger models. SIP options with 4 or 8 MB of external flash in a single package are also available for more demanding AI applications.

New RUHMI Framework

Along with the RA8P1 MCUs, Renesas has introduced RUHMI (Renesas Unified Heterogenous Model Integration), a comprehensive framework for MCUs and MPUs. RUHMI offers efficient AI deployment of the latest neural network models in a framework agnostic manner. It enables model optimization, quantization, graph compilation and conversion, and generates efficient source code. RUHMI provides native support for machine-learning AI frameworks such as TensorFlow Lite, Pytorch & ONNX. It also provides the necessary tools, APIs, code-generator, and runtime needed to deploy a pre-trained neural network, including ready-to-use application examples and models optimized for RA8P1. RUHMI is integrated with Renesas’s own e2 Studio IDE to allow seamless AI development. This integration will facilitate a common development platform for MCUs and MPUs.

Advanced Security Features

The RA8P1 MCUs provide leading-edge security for critical applications. The new Renesas Security IP (RSIP-E50D) includes numerous cryptographic accelerators, including CHACHA20, Ed25519, NIST ECC curves up to 521 bits, enhanced RSA up to 4K, SHA2 and SHA3. In concert with Arm TrustZone, this provides a comprehensive and fully integrated secure element-like functionality. The new MCUs also provides strong hardware Root-of-Trust and Secure Boot with First Stage Bootloader (FSBL) in immutable storage. XSPI interfaces with decryption-on-the-fly (DOTF) allow encrypted code images to be stored in external flash and decrypted on the fly as it is securely transferred to the MCU for execution.

Ready to Use Solutions

Renesas provides a wide range of easy-to-use tools and solutions for the RA8P1 MCUs, including the Flexible Software Package (FSP), evaluation kits and development tools. FreeRTOS and Azure RTOS are supported, as is Zephyr. Several Renesas software example projects and application notes are available to enable faster time to market. In addition, numerous partner solutions are available to support development with the RA8P1 MCUs, including a driver monitoring solution from Nota.AI and a traffic/pedestrian monitoring solution from Irida Labs.

Key Features of the RA8P1 MCUs

Processors: 1GHz Arm Cortex-M85, 500MHz Ethos-U55, 250 MHz Arm Cortex-M33 (Optional)Memory: 1MB/512KB On-chip MRAM, 4MB/8MB External Flash SIP Options, 2MB SRAM fully ECC protected, 32KB I/D caches per core

Graphics Peripherals: Graphics LCD controller supporting resolutions up to WXGA (1280×800), parallel RGB and MIPI-DSI display interfaces, powerful 2D Drawing engine, parallel 16bit CEU and MIPI CSI-2 camera interfaces, 32bit external memory bus (SDRAM and CSC) interface

Other Peripherals: Gigabit Ethernet and TSN Switch, XSPI (Octal SPI) with XIP and DOTF, SPI, I2C/I3C, SDHI, USBFS/HS, CAN-FD, PDM and SSI audio interfaces, 16bit ADC with S/H circuits, DAC, comparators, temperature sensor, timers

Packages: 224BGA, 289BGA

Security: Advanced RSIP-E50D cryptographic engine, TrustZone, Immutable storage, secure boot, tamper resistance, DPA/SPA attack protection, secure debug, secure factory programming, Device Lifecycle management

The post Renesas Sets New MCU Performance Bar with 1-GHz RA8P1 Devices with AI Acceleration appeared first on ELE Times.

Built on Proven SuperGaN Technology, 650-V Gen IV Plus Devices Deliver Robust Performance with Superior Thermal Efficiency and Ultra-Low Power Loss

Renesas Electronics Corporation introduced three new high-voltage 650V GaN FETs for AI data centers and server power supply systems including the new 800V HVDC architecture, E-mobility charging, UPS battery backup devices, battery energy storage and solar inverters. Designed for multi-kilowatt-class applications, these 4th-generation plus (Gen IV Plus) devices combine high-efficiency GaN technology with a silicon-compatible gate drive input, significantly reducing switching power loss while retaining the operating simplicity of silicon FETs. Offered in TOLT, TO-247 and TOLL package options, the devices give engineers the flexibility to customize their thermal management and board design for specific power architectures.

The new TP65H030G4PRS, TP65H030G4PWS and TP65H030G4PQS devices leverage the robust SuperGaN platform, a field-proven depletion mode (d-mode) normally-off architecture pioneered by Transphorm, which was acquired by Renesas in June 2024. Based on low-loss d-mode technology, the devices offer superior efficiency over silicon, silicon carbide (SiC), and other GaN offerings. Moreover, they minimize power loss with lower gate charge, output capacitance, crossover loss, and dynamic resistance impact, with a higher 4V threshold voltage, which is not achievable with today’s enhancement mode (e-mode) GaN devices.

Built on a die that is 14 percent smaller than the previous Gen IV platform, the new Gen IV Plus products achieve a lower RDS (on) of 30 milliohms (mΩ), reducing on-resistance by 14 percent and delivering a 20 percent improvement in on-resistance output-capacitance-product figure of merit (FOM). The smaller die size reduces system costs and lowers output capacitance, which results in higher efficiency and power density. These advantages make the Gen IV Plus devices ideal for cost-conscious, thermally demanding applications where high performance, efficiency and small footprint are critical. They are fully compatible with existing designs for easy upgrades, while preserving existing engineering investments.

Available in compact TOLT, TO-247 and TOLL packages, they provide one of the broadest packaging options to accommodate thermal performance and layout optimization for power systems ranging from 1kW to 10kW, and even higher with paralleling. The new surface-mount packages include bottom side (TOLL) and top-side (TOLT) thermal conduction paths for cooler case temperatures, allowing easier device paralleling when higher conduction currents are needed. Further, the commonly used TO-247 package provides customers with higher thermal capability to achieve higher power.

“The rollout of Gen IV Plus GaN devices marks the first major new product milestone since Renesas’ acquisition of Transphorm last year,” said Primit Parikh, Vice President of the GaN Business Division at Renesas. “Future versions will combine the field-proven SuperGaN technology with our drivers and controllers to deliver complete power solutions. Whether used as standalone FETs or integrated into complete system solution designs with Renesas controllers or drivers, these devices will provide a clear path to designing products with higher power density, reduced footprint and better efficiency at a lower total system cost.”

Unique d-mode Normally-off Design for Reliability and Easy Integration

Like previous d-mode GaN products, the new Renesas devices use an integrated low-voltage silicon MOSFET – a unique configuration that achieves seamless normally-off operation while fully capturing the low loss, high efficiency switching benefits of the high- voltage GaN. As they use silicon FETs for the input stage, the SuperGaN FETs are easy to drive with standard off-the-shelf gate drivers rather than specialized drivers that are normally required for e-mode GaN. This compatibility simplifies design and lowers the barrier to GaN adaptation for system developers.

GaN-based switching devices are quickly growing as key technologies for next-generation power semiconductors, fueled by demand from electric vehicles (EVs), inverters, AI data center servers, renewable energy, and industrial power conversion. Compared to SiC and silicon-based semiconductor switching devices, they provide superior efficiency, higher switching frequency and smaller footprints.

Renesas is uniquely positioned in the GaN market with its comprehensive solutions, offering both high- and low-power GaN FETs, unlike many providers whose success in the field has been primarily limited to lower power devices. This diverse portfolio enables Renesas to serve a broader range of applications and customer needs. To date, Renesas has shipped over 20 million GaN devices for high- and low-power applications, representing more than 300 billion hours of field usage.

The post Renesas Strengthens Power Leadership with New GaN FETs for High-Density Power Conversion in AI Data Centers, Industrial and Charging Systems appeared first on ELE Times.

Silvaco Group Inc of Santa Clara, CA, USA — which provides technology computer-aided design (TCAD), electronic design automation (EDA) software and semiconductor intellectual property (SIP) for process and device development — says that its Victory TCAD solution has been adopted by gallium arsenide (GaAs) foundry Wavetek Microelectronics Corp of Hsinchu Science Park, Taiwan for the development of next-generation gallium nitride (GaN) devices targeting high-performance connectivity applications in 5G, Wi-Fi and IoT markets...

NUBURU Inc of Centennial, CO, USA — which was founded in 2015 and develops and manufactures high-power industrial blue lasers — has reported progress in its strategic transformation, including developments within its planned Defense & Security Hub and key acquisitions...

Normally, when I cover the topic of uninterruptible power supplies (UPSs), I’m talking about devices containing rechargeable battery packs based on either sealed lead-acid (SLA) or one of several newer lithium-based charge storage technology alternatives. But what if the backup-power unit’s batteries aren’t rechargeable…and are lowly alkaline D cells (aka, IEC 420s)?

Normally, I’d probably take a pass on the editorial opportunity. But, given that this particular proposal came from my long-time colleague, mentor, and former boss, Bill Schweber —a name with which many of you are already familiar from his ongoing coverage in EDN, EE Times, Planet Analog, and other AspenCore properties —I couldn’t resist. Here are some (lightly edited) excerpts from his original email to me, titled “Teardown product?”:

Would you like to do a teardown on a Verizon-supplied battery holder/power pack? It holds 12 standard D cells; when AC power fails, you manually switch it on and it powers the Fios box (you also have to remember to switch if back off after AC power comes back on – yeah, right, as if that’s going to happen).

It’s a fairly simple device; has some LEDS to indicate battery condition, not much more. Supposedly powers the Fios box for 24-36 hours.

The unit is model DBH36D12V2, made by CyberPower Systems, is NOT listed on their site (I assume it’s custom for Verizon), and looks like this:

but replacements are available from Verizon as a spare part for end users:

 https://www.verizon.com/home/accessories/powerreserve/?&skuParam=sku190001Comes

 It comes with a skimpy manual showing the line crew how to install it, not much else.

So why do I have this? Verizon was here a month ago, replaced our copper drop from the street pole with fiber but left the copper landline in the house. They installed an AC (normally)-powered fiber-copper converter box, which they brought on their truck.

They mailed me its associated battery box, which they also installed, a few days before they came—except they mailed me two. No idea why they didn’t just bring it on the truck, too.

I called and emailed and wasted time trying to return it, but there is seemingly no way to do that. The local Verizon store said, “go away”. I even went over to a Verizon truck that was in the area, but the guys on the truck wouldn’t take it, either.

I enthusiastically accepted Bill’s offer. The note he included inside the shipment box was priceless and resonated with my own longstanding repair-and-reuse-or-donate aspirations:

Thanks for agreeing to take this off my hands. Whether or not you are able to do something with it, at least I won’t feel guilty leaving it in my basement for the next few years, or throwing it out to add to the electronic waste mountain.

Keep doing those great teardowns…

Aww Let’s start with those stock photos from the Verizon product page (the device, with battery compartment door closed, has Dipert-tape-measured approx. dimensions of 10”x6”x2”):

Now, for our specific patient. I won’t bore you with photos of the light brown (save for Verizon logos on two of the sides) cardboard box that it came in, save for sharing a closeup of the product label attached to one of the other sides:

Nokia? Really?

Onward. Flip open the top flaps, remove a piece of retaining cardboard inside:

followed by several pieces of literature as usual, and as with other photos in this piece, accompanied by a 0.75″ (19.1 mm) diameter U.S. penny for size comparison purposes:

And our victim comes into initial view:

Let’s tackle the literature first. I’m also not going to bore you with the original from-factory shipping slip included in the box. But there was also a wall-mounting template in there: 

along with two mounting screws:

Plus the “skimpy manual” that Bill’s initial email to me had mentioned, and which I’ve scanned for your convenience as a PDF: Skimpy UPS Manual

Now let’s get the device out of the box and out of its clear plastic protective baggie. Front view (orientation references that follow assume it’s wall-mounted per the template):

Here’s a close-up of the connector on the end of the cable coming out of the battery box, which ends up plugged into (and powering) the fiber-copper converter box:

Back:

Plus a close-up of that backside label:

Top:

Right side (note the latch, which I’ll be springing shortly):

Bottom, revealing Bill’s aforementioned power switch, plus a battery-test button and remaining-charge indicator LEDs that appropriately illuminate when the button is pressed (or not, if the D cells are drained; see the user manual for specifics):

And left side (note the hinges; I bet you can already tell which way the battery compartment door swings when opened!):

Another label closeup (again…Nokia?):

And finally, open sesame! Were you correct with your earlier door-swing-direction forecast?

Note that the stamped instructions explicitly warn against using rechargeable batteries:

And yep, a dozen will get one-time drained, not to mention irresponsibly discarded (likely, vs responsibly recycled) and added to the electronic waste mountain, each time the device is used:

On that note, by the way, Bill was spot-on (no surprise) that a web search on “CyberPower DBH36D12V2” was fruitless from a results standpoint. The outcome from dropping the “2” on the end wasn’t much better….that said, it did indirectly lead me to the scanned PDF of a user manual for a conceptually similar CyberPower product, the DTC36U12V, which dispenses with the D cells and instead embeds a conventional UPS-reminiscent SLA battery inside it.

Again, onward. At the bottom of the earlier back-view photo, you might have noticed two holes, one in each corner. Embedded within each is, unsurprisingly, a screw head. Removing them:

enables pull-out of the panel at the bottom of the device’s front side:

Underneath it, again unsurprisingly, is the humble-function PCB, intended fundamentally to regulate-then-output the electrons coming from the dozen-battery array that powers it:

All those caps you see are, I suspect, intended (among other things) to augment the batteries’ innate output power to address the fiber-copper converter box’s startup-surge current needs:

The PCB pulls right out of the enclosure without much fuss:

Once removed, and since we’re already at the side of the PCB, let’s do all four perspectives:

Shall I flip it over next? Yes, I shall. My, little PCB, what thick traces have thee!

One more PCB topside view, this time, the enclosure unencumbered. Note the three battery pack charge strength indicator LEDs and, to their right, the test switch:

More views of the front panel underside, this time with the battery spring contacts temporarily detached:

Speaking of which, here’s a close-up of the other (permanently mounted) spring contacts at the top of the battery compartment:

Here are the light pipe structures and the mechanical button that correspond to the LEDs and switch on the PCB:

And now, unlike Humpty Dumpty and all the king’s horses and men, I’ll put the DBH36D12V2 back together again:

That’s all I’ve got for you today! Bill, I hope I once again met (and even, stretch goal, exceeded?) your expectations. Reader thoughts are as-always welcomed in the comments!

p.s…anyone have a need for a disassembled-then-reassembled but functionally unused CyberPower (or is that Verizon? Or Nokia?) DBH36D12V2?

—Brian Dipert is the Editor-in-Chief of the Edge AI and Vision Alliance, and a Senior Analyst at BDTI and Editor-in-Chief of InsideDSP, the company’s online newsletter.

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• 2024: A year’s worth of interconnected themes galore

The post The CyberPower DBH361D12V2: An UPS That Goes Old-School appeared first on EDN.

The 16-bit DACs are a de facto standard for high DC accuracy and precision domain conversion, but surprisingly few are fully 16-bit (0.0015%) precise. Even when described as “high precision,” some have inaccuracy and integral nonlinearity (INL) that significantly exceed 1 LSB. The TBH PWM-based design detailed here, by contrast, has inherent 16-bit DC accuracy and integral linearity limited only by the quality of the voltage reference. And it gets them without fancy, pricey, high-accuracy components (e.g., no 0.0015% resistors need apply).

Wow the engineering world with your unique design: Design Ideas Submission Guide

Figure 1 shows its underlying nonlinearity-correcting Take-Back-Half (TBH) topology, as explained in: “Take back half improves PWM integral linearity and settling time.”

Figure 1 The INL is canceled by the TBH topology.

Figure 1 relies on two differential relationships that effectively subtract out (take back) integral nonlinearity and attenuate ripple.

1. For signal frequencies less than or equal to the reciprocal of settling time = 1/Ts (including DC) Xc >> R and Z = 2(Xavg – Yavg/2).
2. For frequencies greater than or equal to Fpwm, Xc << R and Z = Xripple – Yripple.

Because only one switch drives node Y while two in parallel drive X, INL due to switch loading at Y is twice that at X. Therefore, since Z = 2(Xavg – Yavg/2), A1’s differential RC network actively subtracts (takes back) the INL error component, resulting in (theoretically) zero net INL.

 Figure 2 illustrates how these elements can fit together in a robust 16-bit DAC circuit design. Here’s how it works.

Figure 2 TBH principle sums two 8-bit PWM signals in one 16-bit DAC = Vref(MSBY+LSBY/256)/256. The asterisked resistors are 0.25% precision types. It is assumed that the PWM frequency (Fpwm) is ~10 kHz.

Two 8-bit resolution PWM signals with a rep rate of ~10 kHz serve as inputs, one for the most significant byte (MSBY) of the setting and the other for the least significant byte (LSBY). The MSBY signal drives R2 and R3, while the LSBY drives the R4, R5, and R7 network. The (R4+R5+4R7)/(R2+R3) = 256:1 ratio of the summing network accommodates the relative significance of the PWM signals. It also enables true 16-bit (15 ppm) conversion precision and differential nonlinearity (DNL) from only 8-bit (2500 ppm) resistor matching.

R6C3 suppresses small nanosecond duration ripple spikes on A1’s output caused by the super-fast output transitions of the U1 switches leaking past A1’s 10 MHz gain-bandwidth product.

The ultimate conversion accuracy is limited almost solely by the 5-V voltage reference quality, so this should be a premium component. Its job is made a little bit (pun) easier by the fact that the maximum current drawn by U1 is a modest 640 µA, which allows for true 16-bit INL with reference impedances up to 0.11 Ω. A maximum reference loading occurs at MSBY duty factor = 50%. The loading falls to near zero at Df = 0 and 100%.

The maximum ripple amplitude also occurs at 50%. The output ripple and DAC settling time are illustrated as the red curve in Figure 3.

Figure 3 Settling time to full precision requires ~100 PWM cycles = 10 ms for Fpwm = 10 kHz.

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

Related Content

• Take back half improves PWM integral linearity and settling time
• Minimizing passive PWM ripple filter output impedance: How low can you go?
• Cancel PWM DAC ripple with analog subtraction
• Temperature controller has “take-back-half” convergence algorithm
• 20MHz VFC with take-back-half charge pump
• Take-Back-Half precision diode charge pump 

The post Inherently DC accurate 16-bit PWM TBH DAC appeared first on EDN.

Anritsu Corporation is proud to announce that its receiver test (SINK Test) solution for the latest DisplayPort 2.1 standard has been certified by the Video Electronics Standards Association (VESA), the international standards organization. Combining Anritsu’s Signal Quality Analyzer-R MP1900A with automation software from Granite River Labs (GRL) or Teledyne LeCroy achieves automated verification of data transmission quality and calibration.

DisplayPort 2.1 enables the digital transmission of high-definition and high-refresh-rate video, such as 8K. The standard is still being developed. Recently, the integration of the USB Type-C specifications has led to a significant expansion in the versatility of DisplayPort 2.1 and its adoption across a wide range of applications. However, a challenge facing the development of products that comply with the new standard is that manually verifying transmission signal quality and calibrating are time-consuming due to the complexity of the test equipment settings and the lengthy configuration and test procedures. This solution improves development efficiency and ensures the quality of video data transmission by automating the testing and calibration processes.

The post Anritsu Gains Certification for Latest DisplayPortTM 2.1 Video Interface Standard Testing Solution appeared first on ELE Times.

The post u-blox ZED-X20P all-band GNSS receiver enables affordable global cm-level precision, customer sampling started appeared first on ELE Times.

Wolfspeed Inc of Durham, NC, USA — which makes silicon carbide (SiC) materials and power semiconductor devices — has taken the next step to implement its previously announced restructuring support agreement (RSA) with key lenders, including (i) holders of more than 97% of its senior secured notes, (ii) Renesas Electronics Corp’s US subsidiary and (iii) convertible debtholders holding more than 67% of the outstanding convertible notes...

Ensuring the reliability and performance of complex digital systems has two fundamental aspects: functional verification and digital design. Digital Design predominantly focuses on the architecture of the system that involves logic blocks, control flow units, and data flow units. However, design alone is not enough.

Functional verification plays a critical role in confirming if the design (digital system) behaves as intended in all expected conditions. It involves writing testbenches and running simulations that test the functionality of the design and catch bugs as early as possible. Without proper verification, even the most well-designed system can fail in real world use.

Coverage is a set of metrics/criteria that determines how thoroughly a design has been exercised during a simulation. It identifies and checks if all required input combinations have been exercised in the design.

There are several types of coverage used in modern verification flows, the first one being code coverage, which analyzes the actual executed code and its branches in the design. Functional coverage, on the other hand, is user-defined and tests the functionality of the design based on the specification and the test plan.

Coverage closure is a crucial step in the verification cycle. This step ensures that the design is robust and has been tested thoroughly. With an increase in scale and complexity of modern SoC/IP architectures, the processes required to achieve coverage closure become significantly difficult, time-consuming, and resource intensive.

Traditional verification involves a high degree of manual intervention, especially if the design is constantly evolving. This makes the verification cycle recursive, inefficient, and prone to human errors. Manual intervention in coverage closure remains a persistent challenge when dealing with complex subsystems and large SoCs.

Automation is not just a way to speed up the verification cycle; it gives us the bandwidth to focus on solving strategic design problems rather than repeating the same tasks over and over. This research is based on the same idea; it turns coverage closure from a tedious task to a focused, strategic part of the verification cycle.

This paper focuses on leveraging automation provided by the Cadence Incisive Metric Center (IMC) tool to minimize the need for manual effort in the coverage closure process. With the help of configurable commands in the Coverage Configuration File (CCF), we can exercise fine control in coverage analysis, reducing the chances of manual adjustments and making the flow dynamic.

Overview of Cadence IMC tool

IMC stands for Incisive Metrics Center, which is a coverage analysis tool designed by Cadence to help design and verification engineers evaluate the completeness of verification efforts. It works across the design and testbench during simulation to collect coverage data stored in a database. This database is later analyzed to identify the areas of design that have been tested and those which have not met the desired coverage goals.

IMC uses well defined metrics or commands for both code and functional coverage, which provide a detailed view of coverage results and identify any gaps to improve testing. The application includes the creation of a user-defined file called CCF, which includes these commands to control the type of coverage data that should be collected, excluded, or refined.

This paper offers several commands—such as “select_coverage”, “deselect_coverage”, “set_com”,”set_fsm_arc_scoring” and “set_fsm_reset_scoring”—which handle different genres of coverage aspects. The “select_coverage” and “deselect_coverage” commands automate the inclusion and exclusion activity by selecting specific sections of code as per the requirement, thus eliminating the manual exclusion process.

The “set_com” command provides a simple approach to avoid the manual efforts by automatically excluding coverage for constant variables. Meanwhile, the “set_fsm_arc_scoring” and “set_fsm_reset_scoring” commands focus more on enhancement of finite state machine (FSM) coverage by identifying state and reset transitions for the FSMs present in the design.

By using this precise and command-driven approach, the techniques discussed in this paper improve productivity and coverage accuracy. That plays a crucial role in today’s fast-paced complex chip development cycles.

Selecting/deselecting modules and covergroups for coverage analysis

The RTL design is a hierarchical structure which consists of various design units like modules, packages, instances, interfaces, and program blocks. It can be a mystifying exercise to exclude a specific code coverage section (block, expr, toggle, fsm) for the various design units in IMC tool.

The exercise to select/deselect any design units for code coverage can be implemented in a clean manner by using the commands mentioned below. These commands also provide support to select/deselect any specific covergroups (inside classes).

• deselect_coverage

The command can enable the code coverage type (block, expr, toggle, fsm) for the given design unit and can also enable covergroups which are present in the given class.

Syntax:

select_coverage <-metrics> [-module | -instance | -class] <list_of_module/instance/class>

Figure 1 The above snapshot shows an example of select_coverage command. Source: eInfochips

This command is to be passed in CCF with the appropriate set of switches; <-metrics> defines the type of coverage metric like block, expr, toggle, fsm, and covergroup. According to the coverage metric, -module or -instance or -class is passed and then the list of module/instance/class is to be mentioned.

• deselect_coverage

The command can disable the code coverage type (block, expr, toggle, fsm) for the given design unit or can disable covergroups which are present in the given class.

Syntax:

deselect_coverage <-metrics> [-module | -instance | -class] <list_of_module/instance/class>

Figure 2 This snapshot highlights how deselect_coverage command works. Source: eInfochips

The combination of these two commands can be used to control/manage several types of code coverage metrics scoring throughout the design hierarchy, as shown in Figure 4, and functional coverage (covergroup) scoring throughout the testbench environment, as shown in Figure 7.

The design has hierarchical structure of modules, sub-modules, and instances (Figure 3). Here, no commands in CCF are provided and the code coverage scoring for all the design units is enabled, as shown in the figure below.

Figure 3 Code coverage scoring is shown without CCF Commands. Source: eInfochips

For example, let us assume code coverage (block, expr, toggle) scoring in ‘ctrl_handler’ module is not required and block coverage scoring in ‘memory_2’ instance is also not required; then in CCF, the deselect_coverage commands mentioned in Figure 4 will be used. To deselect all the code coverage metrics (block, expr, fsm, toggle), ‘-all’ option is used. Figure 4 also depicts the outcome of the commands used for disabling the assumed coverage.

Figure 4 Code coverage scoring is shown with deselect_coverage CCF commands. Source: eInfochips

In another scenario, the code coverage scoring is required for the ‘design_top’ module, and the toggle coverage scoring is required for the ‘memory_3’ instance. Code coverage for the rest of the design units is not required. So, the whole design hierarchy will be de-selected and only the two design units in which the code coverage scoring is required are selected, as shown in Figure 5. The code coverage scoring generated as per the CCF commands is also shown in Figure 5.

Figure 5 Code coverage scoring is shown with deselect_coverage/select_coverage CCF commands. Source: eInfochips

The two covergroups (cg1, cg2) in class ‘tb_func_class ’ are scored when no commands in CCF are mentioned, as shown in Figure 6. In case functional coverage scoring of ‘cg2’ covergroup is not required, the CCF command mentioned in Figure 7 is used. For de-selecting any specific covergroup in a class, the ‘-cg_name’ <covergroup name> option is used

Figure 6 Functional verification is conducted without CCF command. Source: eInfochips

Figure 7 Functional verification is conducted with CCF command. Source: eInfochips

It’s important to note that both commands ‘select_coverage/deselect_coverage’ will have a cumulative effect on the coverage analysis. In <metrics> sub-option, ‘-all’ will include all the code coverage metrics (block, expr, toggle, fsm) but will not include -covergroup metric.

In the final analysis, by using the ‘select_coverage/deselect_coverage’ commands, code/functional coverage in the design hierarchy and from the testbench environment can be enabled and disabled from the CCF directly, which makes the coverage flow neat. If these commands are not used, to obtain a similar effect, manual exclusions from design hierarchy and testbench environment need to be performed in the IMC tool.

Smart exclusions of constants in a design

In many projects, there are some signals or codes of a design that are not exercised throughout the simulation. Such signals or codes of design create unnecessary gaps in the coverage database. To manually add the exclusion of such constant objects in all the modules/instances of design is an exhausting job.

Cadence IMC provides a command which smartly identifies the constant objects in the design and ignores them from the coverage database. It’s described below.

set_com

When the set_com command is enabled in the CCF, it identifies the coverage items such as an inactive block, the constant signals, and constant expressions, which remain unexercised throughout the simulation; it omits them from coverage analysis and marks them IGN in the output generated file.

Syntax:

set_com [-on|-off] [<coverages>] [-log | -logreuse] [-nounconnect] [-module | -instance]

To enable the Constant Object Marking (COM) analysis, provide the [- on] option with the set_com command. When the COM analysis is done, the IMC generates an output file named “icc.com” which captures all the objects that are marked as constant.

By providing the [-log] option, it creates the icc.com file and ensures that the icc.com is updated each time for all the simulations. This icc.com file is created in the path “cov_work/scope/test/icc.com.” The COM analysis for specific module/instance is enabled by providing the [-module | -instance] option with the set_com command.

Figure 8 The above image depicts the design hierarchy. Source: eInfochips

Figure 9 The COM analysis command is shown as mentioned in CCF. Source: eInfochips

Consider that the “chip_da” variable of the design remains constant throughout the simulation. By enabling the set_com command as shown in Figure 9, the variable chip_da will be ignored from the coverage database, which is shown in Figure 10 and Figure 11.

Figure 10 The icc.com output file is shown in the coverage database. Source: eInfochips

Figure 11 Constant variable chip_da is ignored with set_com command enabled. Source: eInfochips

COM analysis

In the CCF, the set_com command is enabled for the addr_handler_instance1 instance.

• Here, as the set_com command is enabled, the “chip_da” signal, which remains constant throughout the simulation, will be ignored from coverage analysis for the defined instances. As shown in Figure 10, in every submodule where the chip_da signal is passed, it gets ignored as the chip_da signal is the port signal, and the COM analysis is done based on the connectivity (top-down/bottom-up).
• Along with the port signals, the internal signals which remain constant, are also ignored from the coverage database. In Figure 10, the “wr” signal is an internal signal and it’s ignored from the coverage database (also reflected in Figure 11).
• The signal chip_da is constant for this simulation (which is IGN) while if chip_da is variable for some other simulation (which is covered/uncovered) and these two simulations are merged. Then the signal chip_da will be considered as a variable (covered/uncovered) and not an ignored constant.

It’s worth noting that when the set_com command is enabled for a module/instance, and if the signal is port signal and is marked as IGN, then the port signals of other sub-modules, which are directly connected to this signal, are also IGN irrespective of the command enabled for that module/instance.

Finally, to avoid the unnecessary coverage that is captured for constant objects and to save time in adding exclusion for such constant objects, the set_com command is extremely useful.

Detailed analysis of FSM coverage

A coverage-driven verification approach gives assurance that the design is exercised thoroughly. For the FSM-based design, there are several types of coverage analysis available. FSM state and transition coverage analysis are the two ways that help to perform the coverage-driven verification of FSM designs, but it’s not a complete verification of FSM designs.

FSM arc coverage provides a comprehensive analysis to ensure that the design is exercised thoroughly. To do that, Cadence IMC provides some CCF commands, which are described below.

set_fsm_arc_scoring

The FSM arc coverage is disabled by default in ICC. It can be enabled by using the set_fsm_arc_scoring command in the CCF. The set_fsm_arc_scoring enables the FSM arcs, which are nothing but all the possible input conditions for which transitions take place between the two FSM states.

Syntax:

set_fsm_arc_scoring [-on|-off] [ -module <modules> | -tag <tags>] [-no_delay_check]

To enable the FSM arc coverage, provide the [-on] option in the set_fsm_arc_scoring. The FSM arc coverage can be encompassed for all the FSMs defined in a module by providing the [-module <module_name>] option.

If the FSM arc coverage needs to be captured for specific FSM in the module, it can be achieved by providing the tag name to FSM using the set_fsm_attribute command in the CCF. By providing tag name option with set_fsm_arc_scoring, FSM arc coverage can be captured for the FSM in design.

set_fsm_reset_scoring

A state is considered a reset state if the transition to that state is not dependent on the current state of the FSM; for example, in the code shown below.

Figure 12 Here is an example of a reset state. Source: eInfochips

State “Zero” is a reset state because the transition to this state is independent of the current state (ongoing_state). By default, the FSM reset state and transition coverage are disabled in ICC, as shown in Figure 13. They can be enabled using the set_fsm_reset_scoring command in the CCF. This command enables scoring for all the FSM reset states and transitions leading to reset states that are defined within the design module.

Figure 13 FSM coverage is shown without set_fsm_arc_scoring command. Source: eInfochips

Syntax:

set_fsm_reset_scoring

In the design, there are two FSMs defined—fsm_design_one and fsm_design_two—and we are enabling the FSM arc and reset state and transition coverage for fsm_design_two only. If the set_fsm_arc_scoring and set_fsm_reset_scoring commands are not provided in the CCF, the FSM arc, FSM reset state and transition coverage are not enabled, as shown in Figure 13.

If the set_fsm_arc_scoring and set_fsm_reset_scoring commands are provided in the CCF, as shown in Figure 14, then the FSM arc, the FSM reset state, and the transition coverage are enabled as shown in Figure 15.

Figure 14 The set_fsm_arc_scoring and set_fsm_reset_scoring commands are provided in CCF. Source: eInfochips

Figure 15 FSM coverage is shown with set_fsm_arc_scoring and set_fsm_reset_scoring commands. Source: eInfochips

In case the design consists of FSM(s), and to ensure that the FSM design is exercised thoroughly, and it’s verified based on a coverage-driven approach, one should enable the set_fsm_arc_scoring and set_fsm_reset_scoring commands in the CCF files.

Efficient coverage closure

Efficient coverage closure is essential for ensuring thorough verification of complex SoC/IP designs. This paper builds on prior work by introducing Cadence IMC commands that automate key aspects of coverage management, significantly reducing manual effort.

The use of select_coverage and deselect_coverage enables precise control over module and covergroup coverage, while set_com intelligently excludes constant objects, improving the coverage accuracy. Furthermore, set_fsm_arc_scoring and set_fsm_reset_scoring enhance the FSM verification, ensuring that all state transitions and reset conditions are thoroughly exercised.

By adopting these automation-driven techniques, verification teams can streamline the coverage closure process, enhance efficiency, and maintain high verification quality, improving productivity in modern SoC/IP development.

Rohan Zala, a senior verification engineer at eInfochips, has expertise in in IP/SoC verification for sensor-based chips, sub-system verification for fabric-based design, and NoC systems.

Khushbu Nakum, a senior verification engineer at eInfochips, has expertise in IP/SoC verification for sensor-based chips and sub-system verification for NoC design.

Jaini Patel, a senior verification engineer at eInfochips, has expertise in IP/SoC verification for sensor-based chips and SoC verification for signal processing design.

Dhruvesh Bhingradia, a senior verification engineer at eInfochips, has expertise in IP/SoC verification for sensor-based chips, sub-system verification for fabric-based design, and NoC systems.

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Flexible integrated circuit (FlexIC) designer and manufacturer Pragmatic Semiconductor Ltd of Cambridge, UK has appointed John Quigley as executive VP (EVP) of engineering with responsibility for technology development, IC design and applications engineering...

The South Wales-based compound semiconductor cluster CSconnected, in partnership with Cardiff Capital Region (CCR), has announced the first four successful applicants to its £1m Supply Chain Development Programme, aimed at strengthening and scaling the compound semiconductor supply chain in South Wales...

Зустріч у ДПМ з телеведучою Анастасією Красницькою Інформація КП пн, 06/30/2025 - 16:43

In order to test multiple ICs simultaneously with different test voltages and currents, semiconductor automatic test equipment (ATE) uses multiple source measurement units (SMUs). Each SMU requires its own independent floating voltage tracking power supply to ensure clean measurements.

Figure 1 shows the basic structure of the SMU power supply. The voltage tracking power supplies need to supply the power amplifiers with a wide voltage range (±15 V to ±50 V) and a constant power capability.

Figure 1 A simplified power-supply block diagram in an ATE. Source: Texas Instruments

Figure 2 illustrates the maximum steady-state voltage and current that the SMU requires in red and the pulsed maximums in blue.

Figure 2 An example voltage-current profile for a voltage tracking power supply. Source: Texas Instruments

The ICs under test require a low-noise power supply with minimal power loss. In order to manage the power dissipation in a linear power device and deliver constant power under the conditions shown in Figure 2, it is required that the power supply be able to generate a pulsating output with high instantaneous power.

In addition to power dissipation considerations, it is essential that the power supply has a sufficient efficiency and thermal management to accommodate as many test channels as possible.

Four topologies are studied and compared to see which one best meets the voltage tracking power supply requirements. Table 1 lists the electrical and mechanical specifications for the power supply. The four topologies under consideration are: hard-switching full bridge (HSFB), full-bridge inductor-inductor-capacitor (FB-LLC) resonant converter, dual active half bridge (DAHB), and a two-stage approach composed of a four-switch buck-boost (4sw-BB) plus half-bridge LLC resonant converter (HB-LLC).

Parameter	Minimum	Maximum
Vin	15V	45V
Vout	±15V	±45V
Iout	0A	±2.0A
Pout,pulse	N/A	150W
Height	N/A	4mm
Width	N/A	14mm
Length	N/A	45mm
PCB layers	N/A	18

Table 1 Electrical and mechanical SMU requirements. Source: Texas Instruments

Topology comparison

Figure 3 shows the schematic for each of the four power supplies.

Figure 3 The four topologies evaluated to see which one best meets the voltage tracking power supply requirements listed in Table 1. Source: Texas Instruments

Each topology was evaluated on two essential requirements: small size and minimizing the thermal footprint. Efficiency is only important in as far as heat management is concerned.

Table 2 summarizes the potential benefits and challenges of each topology. In addition to size, the maximum height constraint necessitates a printed circuit board (PCB)-based transformer design.

Topology	Benefits	Challenges
HSFB	Single power conversion stage. Simple well-known control.	Hard switching will limit the operating frequency. A wide input and output range will be difficult for a single stage.
FB-LLC	Single power conversion stage. Capable of high switching frequency because of zero voltage switching (ZVS).	A wide input and output range will be difficult for a single stage. Low Lm may result in low efficiency because of high root-mean-square (RMS) currents.
DAHB	Single power conversion stage. Capable of high switching frequency because of ZVS.	A wide input and output range will be difficult for a single stage. Complex control is required to deliver the required power and maintain ZVS.
Two-stage	Optimized preregulator for power delivery over a wide range. Optimizing the LLC for a single operating frequency makes the resonant tank design straightforward. Heat is spread out over a larger area.	Two stages will increase the required space.

Table 2 The benefits and challenges of the four different SMU power supply topologies. Source: Texas Instruments

In order to understand the size implications for the HSFB, it is necessary to start out by examining the structure of the transformer. Equation 1 calculates the turns ratio for the HSFB as:

Using the requirements listed in Table 1 gives a result of . Because a practical design will require a PCB with no more than 18 layers, the maximum required primary turns on a center-tapped design is 2:8:8. With this information, you can use Equation 2 to estimate the center leg core diameter:

Hard switching losses in the FETs will keep the frequency no higher than 500 kHz, resulting in a 12 mm diameter of the center leg. The resulting core will be at least twice this size. The end result is that the HSFB solution is just too large for any serious practical consideration.

The single-stage FB-LLC enables a higher switching frequency by solving the hard-switching concerns found in the HSFB. However, the broad input and output voltage range will require a small magnetizing inductance. The best design identified used a turns ratio of 4:5, Lm = 2 µH, Lr = 1 µH, and fr = 800 kHz. This design addresses the issues with the HSFB by incorporating more primary turns, achieving a high operating frequency for minimal size, and requiring only 14 layers. However, the design suffers from several operating points that result in ZVS loss and an inability to generate the necessary output voltage under pulsed load conditions.

Figure 4 shows the equation and plots of the maximum gain of the system. Supporting the requirements outlined in Table 1 requires a gain of at least 3. Figure 4 shows that this is only possible by drastically decreasing one or more of Lr, Lm, or fr. Decreasing Lr will result in a loss of ZVS from the rapid change in the inductor current. Reducing fr will drive up the size of the transformer and the required primary turns. Decreasing Lm will significantly increase losses from additional circulating current. Given these factors, the single-stage FB-LLC is also not an option.

Figure 4 Maximum fundamental harmonic approximation (FHA) gain plots. Source: Texas Instruments

DAHB

The DAHB [1] is an interesting option that also attempts to solve the hard-switching concerns. One area of concern is the requirement to have active control of the secondary FETs. This kind of control will require additional circuitry to translate the control across the isolation boundary. Equation 3 predicts the resulting power delivery capability of the DAHB:

Table 3 lists the results for the full requirements outlined in Table 1. Notice that there are several problematic conditions, most notably one condition where the required peak current is 80 A. The FETs used in the design cannot accommodate this current.

Table 3 DAHB operating points with several problematic conditions that cannot be designed. Source: Texas Instruments

The two-stage approach pushes the voltage regulation problem to the 4sw-BB and operates the HB-LLC at a fixed frequency at resonance, which allows the HB-LLC to run at high frequency and more easily achieve ZVS under all conditions. The obvious downside of this approach is that it uses two power stages instead of one. However, the reduced currents in the HB-LLC and its ability to run at higher frequencies enable you to minimize the size of the transformer.

Table 4 summarizes the comparison between the four topologies, highlighting the reasons for selecting the two-stage approach. References [2] and [3] describe some essential control parameters used for the buck-boost and LLC.

Topology	Comparison results
HSFB	Hard switching losses keep the switching frequency low. Large secondary turns and low operating frequency result in a large magnetic core.
FB-LLC	Parasitic capacitance requires a larger resonant inductor. Gain requires a smaller resonant inductor. The design cannot provide the required voltages.
DAHB	Complex multimode control. Active secondary-side FET control. Large RMS currents.
Two stage	Including a preregulator optimizes power delivery over the wide range. The LLC can be optimized for a single operating frequency. Heat is spread out over a larger thermal footprint

 Table 4 Comparison between the four different topologies, highlighting the reasons for selecting the two-stage approach. Source: Texas Instruments

Test results

Based on the comparison results, I built a high-power-density (14 mm by 45 mm) 4sw-BB plus HB-LLC prototype. Figure 5 shows an image of the hardware prototype of the final design that fits in the space outlined by Table 1.

Figure 5 The top-side layout of the high-power density 4sw-BB + HB-LLC test board. Source: Texas Instruments

Figure 6 shows both efficiency and thermal performance of the LLC converter.

Figure 6 The LLC efficiency curve and a thermal scan of the LLC converter. Source: Texas Instruments

Two-stage approach

After considering four topologies to meet ATE SMU requirements, the two-stage approach with the four-switch buck boost and fixed-frequency LLC was the smallest overall solution capable of meeting the system requirements.

Brent McDonald works as a system engineer for the Texas Instruments Power Supply Design Services team, where he creates reference designs for a variety of high-power applications. Brent received a bachelor’s degree in electrical engineering from the University of Wisconsin-Milwaukee, and a master’s degree, also in electrical engineering, from the University of Colorado Boulder.

Related Content

• Power Tips #140: Designing a data center power architecture with supply and processor rail-monitoring solutions
• Power Tips # 141: Tips and tricks for achieving wide operating ranges with LLC resonant converters
• Modular scalable test set comprises source-measure ATE
• ATE system automates power semiconductor tests

References

1. Laturkar, N. Deshmukh and S. Anand. “Dual Active Half Bridge Converter with Integrated Active Power Decoupling for On-Board EV Charger.” 2022 IEEE International Conference on Power Electronics, Smart Grid, and Renewable Energy (PESGRE), Trivandrum, India, 2022, pp. 1-6, doi: 10.1109/PESGRE52268.2022.9715900.
2. McDonald and F. Wang.” LLC performance enhancements with frequency and phase shift modulation control.” 2014 IEEE Applied Power Electronics Conference and Exposition – APEC 2014, Fort Worth, TX, USA, 2014, pp. 2036-2040, doi: 10.1109/APEC.2014.6803586.
3. Sun, B. “Multimode control for a four-switch buck-boost converter.” Texas Instruments Analog Design Journal, literature No. SLYT765, 1Q 2019.

The post Power Tips #142: A comparison study on a floating voltage tracking power supply for ATE appeared first on EDN.

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