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Photonic chips industry accelerator PhotonDelta of Eindhoven, the Netherlands (which connects and collaborates with an ecosystem of photonic chip technology organizations worldwide) and Luminate NY of Rochester, NY, USA (the world’s largest accelerator for startups working on optics, photonics and imaging-enabled technologies) have entered into a strategic collaboration to support the growth of early-stage photonics companies across North America and the Netherlands...

The UK Government says that Compound Semiconductor Applications (CSA) Catapult will mobilize the new UK Semiconductor Centre (UKSC)...

The world we are living in is increasingly becoming software-defined, where artificial intelligence (AI) is adding the next layer of functionality. And it’s driving the need for more compute to enable the software-enabled functionality. However, with this huge progression in compute content, Moore’s Law scaling will be insufficient to support the number of transistors for the needed compute.

Enter 3D ICs, disaggregating the functionality of silicon into a set of chiplets and then heterogeneously integrating them on an advanced integration platform. “Hyperscalers, driving the compute envelope, are particularly pushing the extreme where 3D ICs are needed,” said Michael White, VP of Calibre Design Solutions at Siemens EDA.

White also noted automotive designs where self-driving technology content is driving the need for 3D ICs. At the Design Automation Conference (DAC) held in San Francisco, California, on 22-25 June 2025, Siemens EDA announced two key additions to its EDA portfolio to address and overcome the complexity challenges associated with the design and manufacture of 2.5D and 3D IC devices.

First, the company’s Innovator3D IC suite enables chip designers to efficiently author, simulate, and manage heterogeneously integrated 2.5D and 3D IC designs. Second, its Calibre 3DStress software leverages advanced thermo-mechanical analysis to identify the electrical impact of stress at the transistor level.

Figure 1 The new tools aim to dramatically reduce risk and enhance the design, yield, and reliability of complex, next-generation 2.5D/3D IC designs. Source: Siemens EDA

“These solutions help designers achieve the needed compute performance while increasing yield and reliability and reducing cost,” White added. “They also offer the ability to leverage higher bandwidth between the chiplets placed on an interposer.” He calls this an inflection point in the design process and tools needed for the design flows.

Chiplet integration with Innovator3D IC

Keith Felton, principal technical product manager for 3D IC solutions at Siemens EDA, expanded on 3D IC being an inflection point, marking a transition from single design-centric approach to system-centric approach. “It impacts design flows and tools, necessitating a system-centric approach from early planning through final sign-off in four ways,” he added.

First, chip designers need system floor planning to optimize power, performance, area, and reliability across silicon, package, interposer, and even PCB. Second, they must start using multi-physics modeling to simulate complex thermo-mechanical interactions that impact electrical and structural performance.

Third, IC designers need to have a methodology for scalability to manage and communicate heterogeneous data across enterprise-wide teams and maintain digital continuity because there are hundreds of silicon designs encompassing chiplets. Fourth, designers must have a methodology for multi-die sign-off, enabling 3D verification of connectivity, interfaces, interconnect reliability, and electrostatic discharge (ESD) resiliency.

So, Innovator3D IC suite provides a fast, predictable path for planning and heterogeneous integration, substrate/interposer implementation, interface protocol analysis compliance and data management of designs, and design data IP.

Figure 2 Innovator3D IC suite facilitates design, verification, and data management of 2.5D and 3D IC chiplets. Source: Siemens EDA

Innovator3D IC—comprising four building blocks—offers an AI-infused user experience with extensive multithreading and multicore capabilities to achieve optimal capacity and performance on 5+ million pin designs. First, Innovator3D IC Integrator comes with a consolidated cockpit for constructing a digital twin, using a unified data model for design planning, prototyping, and predictive analysis.

Second, Innovator3D IC Layout facilitates correct-by-construction package interposer and substrate implementation. Third, Innovator3D IC Protocol Analyzer can be used for chiplet-to-chiplet and die-to-die interface compliance analysis. It’ll be critical in ensuring compliance with protocols such as Universal Chiplet Interconnect Express (UCIe). Finally, the Innovator3D IC Data Management part is targeted at the work-in-progress management of designs and design data IP.

“Innovator3D IC is targeting the optimization of 2.5 and 3D IC design performance to eliminate late-stage changes by enabling early prototyping and planning,” Felton said. “It accelerates compliance with protocols for chiplet integration and provides a core workflow that design teams need for 3D IC chiplet integration.”

Calibre 3DStress for package verification

Calibre 3DStress—the second part of Siemens EDA’s solution to streamline the design and analysis of complex, heterogeneously integrated 3D ICs—supports accurate, transistor-level analysis, verification, and debugging of thermo-mechanical stresses and warpage in the context of 3D IC packaging.

It enables IC designers to assess how chip-package interaction will impact the functionality of their designs earlier in the development cycle. Shetha Nolke, principal product manager for Calibre 3DStress at Siemens EDA, told EDN that this tool performs three key tasks for chip-package stress analysis in 3D IC designs.

First, stress simulation ensures accurate die levels under thermal and mechanical conditions. Second, what-if analysis optimizes IP, cell, or chip placement during early design stages. Third, it performs stress-aware circuit analysis using back annotation of device stress to minimize electrical impact.

Figure 3 With the thinner dies and higher package processing temperatures of 2.5D/3D IC architectures, designers often discovered that designs validated and tested at the die level no longer conform to specifications after packaging reflows. Source: Siemens EDA

3D ICs increasingly face stress- and warpage-related packaging challenges. That includes thermal challenges such as non-uniform heat generation and dissipation, which can result in higher temperatures and temperature gradients. Then, there are thermo-mechanical issues, where packaging process stages experience high temperature and fixed constraints.

Finally, thinned dies and ultra-low-k dielectrics increase mechanical stress-induced problems. “As multiple chiplets are integrated into a package, they experience thermal impacts because heat is not able to escape readily,” Nolke said. “While mechanical aspects are coming from incorporating package components, Calibre 3DStress can model it before fabrication.”

Calibre 3DStress delivers accurate die-level stress simulation using finite element analysis at a nano-meter feature scale. It also provides visualization of stress and warpage results while facilitating electrical and mechanical verification.

Related Content

• TSMC, Arm Show 3DIC Made of Chiplets
• One-stop advanced packaging solutions for chiplets
• Cadence to Buy Artisan to Support Chiplet, 3D IC Future
• Cadence enables multi chiplet design with Integrity 3D-IC platform
• Advanced IC Packaging: The Roadmap to 3D IC Semiconductor Scaling

The post New EDA tools arrive for chiplet integration, package verification appeared first on EDN.

Фінансування престижного міжнародного конкурсу Erasmus+ для проекту кафедри ХТФ kpi вт, 06/24/2025 - 15:27

Keysight, Teledyne LeCroy, Tektronix, Rohde & Schwarz (R&S), and others have offered built-in digital oscilloscope Bode analysis for some time, and this feature has trickled down to low-cost DSOs like the Siglent SDS2000X Plus and the new SDS814X HD. These DSOs feature built-in Bode analysis when operating with a companion AWG, or sometimes include the AWG within (SDS2000X Plus), at an affordable price point.

Wow the engineering world with your unique design: Design Ideas Submission Guide

DIY common-mode choke

One of the interesting applications of this Bode capability is investigating the open-loop response of closed-loop systems, such as oscillators. This often requires an expensive isolation transformer, which can be limiting. However, for those with a DIY spirit, a reconfigured common-mode choke serves as a nice isolation transformer for Bode analysis (Figure 1) [1].

Figure 1 A reconfigured common-mode choke isolation transformer used to investigate the open-loop response of closed-loop systems, e.g., oscillators, using the Bode capability of a benchtop oscilloscope.

Creating the isolation transformer is straightforward. Physically larger common-mode “chokes” utilized in AC mains, like the one shown, make good candidates, especially for lower frequencies.

Here, 5 mH and 2 mH Prod Tech PDMCAT221413 types were utilized after unwinding and rewinding. First, after the unwinding, the pair of wires are stretched, and then the pair of wires are twisted together (a hand drill helps). This leaves a long twisted pair which is threaded through the core as many times as possible.

As shown in Figure 2, the wrapped core now has two ends with the twisted pair, and at each end, a pair of wires. The ends of the wire on each side are common with the other pair of wires’ ends (use an ohmmeter), becoming the primary or secondary. Either way, it doesn’t matter since the isolation transformer has a 1:1 turns ratio and is symmetrical. The primary and secondary can be resistively terminated as needed for specific applications.

Figure 2 A side-view of the DIY isolation transformer showing the wrapped core and terminated with four 2-W, 100-Ω resistors.

Figure 3 shows the test setup utilizing the DIY isolation transformer to measure the open-loop response of a Peltz oscillator, as described in another Design Idea (DI): “Simple 5-component oscillator works below 0.8V.”

Figure 3 Test setup using the DIY isolation transformer to measure the open-loop response of a Peltz oscillator.

Peltz oscillator test circuit and results

The isolation transformer secondary is connected between Q2 base and Q1 collector. Q1 and Q2 are 2N3904s, L is 470 µH, C is 0.022 µF, and R is 510 Ω (Figure 4).

Figure 4 The configuration of the Peltz oscillator circuit, where the isolation transformer is connected between Q2 base and Q1 collector to measure open-loop response.

For comparison, an LTspice circuit model was created. The simulated and measured results using the SDS2504X Plus are shown in Figure 5.

Figure 5 Simulated (top) and measured (bottom) results with the circuit under test in Figure 4 operating with the following values: L is 470 µH, C is 0.022 µF, and R is 510 Ω.

Changing the inductor to 100 µH (measured 97.3 µH) which moves the center frequency to 34.4 kHz (Figure 6).

Figure 6 Simulated (top) and measured (bottom) results with the circuit under test in Figure 4 operating with the following values: L is 100 µH, C is 0.022 µF, and R is 510 Ω.

Typically, physically larger common-mode chokes have higher inductance, which can extend the measurement range to lower frequencies. Having a larger core also allows for more turns, which also helps with lower frequencies.

However, larger cores and more turns limit the upper frequency end, and having more cores, smaller and larger, can cover a wider frequency range than a single-core transformer. I’ve had good results with the cores shown from less than 100 Hz to over 1 MHz.

This is just one of the many uses for modern Bode-enabled DSOs with companion AWGs and a few DIY isolation transformers.

Michael A Wyatt is a life member with IEEE and has continued to enjoy electronics ever since his childhood. Mike has a long career spanning Honeywell, Northrop Grumman, Insyte/ITT/Ex-elis/Harris, ViaSat and retiring (semi) with Wyatt Labs. During his career he accumulated 32 US Patents and in the past published a few EDN Articles including Best Idea of the Year in 1989.

Related Content

• Simple 5-component oscillator works below 0.8V
• Injection locking acts as a frequency divider and improves oscillator performance
• Investigating injection locking with DSO Bode function
• DIY custom Tektronix 576 & 577 curve tracer adapters

References

1. https://www.eevblog.com/forum/testgear/diy-transformer-for-use-with-bode-plots/

The post DIY isolation transformer enhances Bode analysis with modern DSOs appeared first on EDN.

Питання інженерії поверхні в авіадвигунобудуванні держава визнає серед найактуальніших Інформація КП вт, 06/24/2025 - 13:00

At the end of this year, research institute TNO (the Netherlands Organization for Applied Scientific Research in Delft) will begin constructing a pilot manufacturing line for photonic chips at the High Tech Campus in Eindhoven. The new factory will enable the industrial-scale production of indium phosphide (InP)-based photonic chips. Additionally, the scaling up from 4-inch to 6-inch wafers will make production more efficient. TNO is collaborating on this with the Photonic Integration Technology Centre (PITC), Eindhoven University of Technology, and the University of Twente...

Efficient Power Conversion Corp (EPC) of El Segundo, CA, USA — which makes enhancement-mode gallium nitride on silicon (eGaN) power field-effect transistors (FETs) and integrated circuits for power management applications — has released the EPC91109, a high-performance evaluation board designed to demonstrate the benefits of eGaN FETs in a compact, thermally efficient, two-phase synchronous buck converter. Targeting USB Power Delivery (USB-PD 3.1) applications up to 180W, the EPC91109 is optimized for space- and power-constrained designs such as laptops, portable devices, and battery-powered systems...

Building a dual rail power supply 0-40v and didn't have any 4700uf or bigger capacitors so a row of 1000x2 + 680x2 + 470x2 + 330x2 + 220x4 + 100x2 for a total of 6 040 will have to do. submitted by /u/Whyjustwhydothat [link] [comments]

In the changing scene of industrial automation and electrification, another part of the PDS systems has found its way into the power drive system of the electrical motors in a large number of applications-ranging from robotics to conveyors, to HVAC systems and various industrial pumps. At the center of power is the semiconductor that determines the efficiency, performance, size and cost of the drive systems.

Two of Infineon’s most widely admitted semiconductor technologies used in this space are:

CoolSiC, a wide bandgap Silicon Carbide (SiC) MOSFET-based technology and TRENCHSTOP IGBT, a mature and cost-effective IGBT technology.

While both serve the same purpose of converting and controlling electrical power, each comes with its strengths and limitations. This article presents a detailed and data-based comparative analysis of these two technologies for real world PDS applications, touching upon efficiency, efficiency, switching performance, thermal characteristics and total system cost.

Technology Overview

CoolSiC (SiC MOSFETs)-

CoolSiC MOSFET capitalize on the physical features of silicon carbide, the wide-bandgap material being known for its high thermal conductivity, high breakdown voltage, and low switching losses.

TRENCHSTOP IGBT-

In the TRENCHSTOP IGBT, trench and field-stop technologies coalesce to enable low conduction losses and fast switching at a reasonable price. In traditional motor drives, this time-tested silicon-based technology still capitalizes on robust operation and hence enjoys very good price-performance in the general-purpose drives.

Benchmark Setup: Simulations and Measurements

To evaluate the performance of the two technologies, Infineon had simulated and experimentally tested them on a typical PDS architecture:

Application: 3-phase, 400 V AC, 7.5 KW motor drive

Topology: 3-level inverter

Modulation Strategy: Sinusoidal PWM

Switching Frequency:

IGBT – 8KHz

CoolSic – 40 KHz

Cooling system: Passive heatsink, same ambient conditions

Load Profile: Constant speed, variable torque

Efficiency Comparison

Energy efficiency of the drives is a pressing concern, directly impacting energy bills and CO₂ emissions.

Technology	Peak Efficiency	Average Efficiency (Load range: 30-100%)
CoolSiC	98.5%	97.8%
TRENCHSTOP IGBT	96.8%	95.1%

 

Peak efficiency of the CoolSiC inverter is around 2 percent higher than that of the TRENCHSTOP solution. The higher switching frequency made for better waveform quality with lower harmonics, thus causing motor heating and system losses.

That means too much saving on energy by about 8 to 12% during the lifetime of a drive, specifically in high-duty applications such as HVAC, pumps and compressors.

Switching Performance and Losses

Being a unipolar device equipped with fast-switching features, CoolSiC turns out to be batter than an IGBT in turn on as well as turn off switching losses.

 

Parameter	CoolSiC	TRENCHSTOP IGBT
Turn-on loss	~0.3 mJ	~2.5 mJ
Turn-off loss	~0.2 mJ	~2.0 mJ
Total switching loss per cycle	~0.5 mJ	~4.5 mJ

 

The losses incurred by IGBT goes by the hour at high switching frequencies (exceeding 20 kHz); meanwhile, CoolSiC has linear loss scaling, giving it an edge in precision motor control applications.

Thermal Behavior and Heatsink Requirements

With less power loss, less is generated in thermal energy. This reduces the heat dissipation of the system, thus affecting the cooling requirement and the size of the system.

Metric	CoolSiC	TRENCHSTOP IGBT
Junction temperature	~80°C	~105°C
Required heatsink size	30% smaller	Baseline
Cooling system complexity	Simple/passive	More advanced

 

The size of the CoolSiC modules is significantly less. Also, this possibility opens the opportunity for fan-less or sealed enclosures, which is perhaps important in a dusty environment.

Impact on Motor Performance

The possibility of CoolSiC switching at higher frequencies brings about better sinusoidal output waveforms benefitting motor performance.

Motor Performance Aspect	CoolSiC	TRENCHSTOP IGBT
Acoustic noise	Lower	Higher
Torque ripple	Reduced	Noticeable
Motor temperature	Rise 8-10°C lower	Baseline

 

Using CoolSiC inverters will certainly increase motor efficiency and longevity, especially in applications involving servo drives or high-speed ones where fast transient response and high precision are required.

System-Level Cost Analysis

Through the true cost of a CoolSiC device is mostly on per unit basis, the story of the system cost is usually quite different.

Cost Element	CoolSiC	TRENCHSTOP
Semiconductor cost	Higher	Lower
Cooling system cost	Lower	Higher
System size and weight	Smaller	Larger
Total Cost of Ownership (TCO, 5 year)	~10–15% lower	Baseline

 

Indeed, CoolSiC’s greater energy efficiency in long duty cycles brings down operating costs and ensures a speedy ROI and better sustainability profile.

When to Use Which Technology?

Application Type	Recommended Technology	Justification
High-speed servo drives	CoolSiC	High frequency precision, low noise
HVAC systems	CoolSiC	Energy efficiency, compact size
Pumps and Compressors	CoolSiC	Lower energy consumption over time
Budget-sensitive drives	TRENCHSTOP IGBT	Cost-effective for <15KW systems
Harsh industrial environments	CoolSIC	High thermal tolerance, robust design

 

Conclusion:

There is no doubt that CoolSiC technology from Infineon sets the benchmark for the next generation of industrial drives in terms of efficiency, compactness and performance. In a high-performance, space-restricted or energy sensitive environment, SiC can make designs which are small, cool, sustainable and future-proof.

However, to TRENCHSTOP IGBT remains the preferred option where cost considerations dominate and the switching-frequency and thermal load requirements on the system are moderate.

With the trend of industrial systems towards smarter, greener and digitalized infrastructures, the usage of wide bandgap semiconductors such as CoolSiC can farther be expected to grow exponentially.

The post CoolSiC and IGBT Face Off in Industrial Power Drive Applications appeared first on ELE Times.

The University of Massachusetts Lowell says that Electrical Engineering assistant professor Anhar Bhuiyan is among 36 recipients of this year’s Ralph E. Powe Junior Faculty Enhancement Awards, nationally competitive seed grants for faculty in the first two years of their academic careers. The award supports Bhuiyan’s research into next-generation materials and components for powering satellites and unmanned spacecraft...

The power module equipped with Japan-based ROHM Co Ltd’s fourth-generation silicon carbide (SiC) MOSFET bare chip has been adopted in the traction inverter of Toyota Motor Corp’s new bZ5 crossover-type battery electric vehicle (BEV) for the Chinese market...

Technical University of Eindhoven (TU/e) in The Netherlands is establishing a new research institute dedicated to semiconductors, quantum, photonics, and the development of high-tech systems and chips of the future...

Just a heads-up: be very careful when installing software that asks you to disable or bypass your system's security features. I came across this in the official documentation for the offline EasyEDA app — they explicitly instruct users to bypass built-in protections: https://oshwlab.com/forum/post/3695f3a2f9694de4b1b4cfa839a9a03e Am I the only one who finds this not just unprofessional, but a serious security risk. Especially for users who might not fully understand the implications. Curious to hear what others think. submitted by /u/djooker [link] [comments]

Юрій Коренюк з ВПІ: "Незаконно привласнені росією пам'ятки мають повернутися в Україну" Інформація КП пн, 06/23/2025 - 20:05

Студенти КПІ відвідали офіс компанії ProfInstall kpi пн, 06/23/2025 - 18:31

A look at AI glasses

I’ve been following smart glasses for a while now (and the more embryonic camera-augmented eyewear category a “bit” longer than that). As with smart watches and more recent smart rings, they’re intriguing to me because they take already-familiar, mature and high volume consumer products and make them…umm…smart. Plus, there’s the oft-touted potential for smart glasses to augment if not supplant the equally now-pervasive smartphone (for the record: I’m dubious at best on that latter replacement-potential premise).

With all due respect to Google, with Glass, introduced in 2013 and near-immediately thereafter spawning “glassholes” terminology:

and other technology trendsetters—Snap’s multiple generations of Spectacles, for example:

I’d suggest that the smart glasses category really didn’t “get legs” until Meta and partner Ray-Ban’s second-generation AI Glasses, released in October 2023. Stories, the first-generation product introduced in September 2020 by EssilorLuxottica (Ray-Ban’s parent company) and then-Facebook (rebranded as Meta Platforms a year later) had adopted the iconic Ray-Ban style:

but it was fundamentally a content capture and playback device (plus a fancy Bluetooth headset to a wirelessly tethered smartphone), containing an integrated still and video camera, stereo speakers, and a three-microphone (for ambient noise suppression purposes) array.

The second-gen AI Glasses first and foremost make advancements on these fundamental fronts:

• A still image capture resolution upgrade from 5 Mpixels to 12 Mpixels
• Video capture up-resolution from 720p to 1080p (plus added livestreaming support)
• 8x the integrated content storage capacity (from 4 GBytes to 32 GBytes)
• An enhanced integrated speaker array with two ports per transducer and virtual surround sound playback support, and
• A now-five-microphone array for enhanced ambient noise reduction, also capable of “immersive audio capture”

Ray-Ban Meta AI glasses

They’re also now moisture (albeit not dust) resistant, with an IPX4 rating, for example. But the key advancement, at least to this “tech-head”, is their revolutionary AI-powered “smarts” (therefore the product name), enabled by the combo of Qualcomm’s Snapdragon AR1 Gen 1, Meta’s deep learning models running both resident and in the “cloud”, and speedy bidirectional glasses/cloud connectivity. AI features include real-time language Live Translation plus AI View, which visually identifies and audibly provides additional information about objects around the wearer (next-gen glasses due later this year will supposedly also integrate diminutive displays).

The broad market seems to agree; in mid-February, EssilorLuxottica announced that it’d already sold 2 million pairs of Ray-Ban Meta AI Glasses in their first year-plus and aspired to hit a 10 million-per-year run rate by the end of 2026. As I noted in my 2025 CES coverage:

Ray-Ban and Meta’s jointly developed second-generation smart glasses were one of the breakout consumer electronics hits of 2024, with good (initial experience, at least) reason. Their constantly evolving AI-driven capabilities are truly remarkable, on top of the first-generation’s foundational still and video image capture and audio playback support.

That said, within that same coverage, I also wrote:

I actually almost bought a pair of Ray-Ban Meta glasses during Amazon’s Black Friday…err…week-plus promotion to play around with for myself (and subsequently cover here at EDN, of course). But I decided to hold off for the inevitable barely-used (if at all) eBay-posting markdowns to come.

As it turns out, though, and as any of you who read my recent Mercari diatribe may have already noticed, I didn’t end up waiting very long. Turns out, at Meta Connect in September 2024, EssilorLuxottica had unveiled a limited edition (only 7,500 pairs worldwide) transparent version of the AI Glasses (versus the more recent translucent limited edition ones), priced at $429, and which sold out near-immediately. I didn’t snag a pair at the time—admittedly, I didn’t even know they existed at the time. But I ended up buying someone else’s barely used pair a few months ago, at a “bit” of a markup from the original MSRP (but to be clear, nowhere near the five-digit price tags I usually see them for-sale posted for on eBay, etc.). Some stock images to start:

(no, there will not be any pictures of them on my head. Trust me, it’s for the best for all of us.).

So, why’d I buy them? Part of the motivation, admittedly, combines my earlier noted belief that they’re the first truly impactful entrant in this embryonic product category, therefore destined to be a historical classic, with the added limited-edition cachet of this particular variant. Plus:

• Nobody’s going to confuse these with a normal pair of Ray-Ban sunglasses, such as might be the case with the ones below. I don’t want anyone belatedly noticing the camera and pseudo-camera in the corners of the frame and then go all paranoid on me, worried that I might have been surreptitiously snapping pictures or shooting video of them.

• They’ve got transition lenses, as the stock photos show. Candidly, it creeps me out when I see someone wearing conventional always-tinted sunglasses indoors. But I still want them to be sunglasses when I’m outdoors (versus also-available always-clear lens variants). And I’d like to use them both places.
• And, because they’re transparent—no, I’m not going to take mine apart—I can still do a semblance of a teardown on them for you today, in combo with a video I found of someone who did take theirs apart…for science…and viewer traffic revenue, of course.

(in-advance warning; some of the dissection sequences in this teardown video are quite brutal on the eyes and ears, IMHO at least!)

The AI glasses teardown

Follow along as I showcase my AI glasses, periodically referencing specific timestamps in the above video for added visual data point evidence. I’ll start out with some (already opened by the previous owner, obviously) outer box shots, as usual accompanied by a 0.75″ (19.1 mm) diameter U.S. penny for size comparison purposes. This particular AI Glasses variant comes in only one style—Wayfarer—and size option—M (50-22) —and they weigh 48.6 grams/1.71 ounces, with the charging case coming in at an incremental 133 grams/4.69 ounces:

Open sesame:

Before continuing, this shot shows one of the uniqueness aspects of these limited-edition glasses. Standard ones’ cases have a tan-color patina instead:

Onward:

I like black better. Don’t you? Totally worth the incremental price tag all by itself (I jest):

The front LED communicates the charge status of both the case and the glasses inside it:

The USB-C connector on the bottom:

is…drum roll…for charging purposes (surprising absolutely no one by saying that, I realize):

Open sesame, redux:

I’m sure that the cleaning cloth was more neatly packaged when the glasses were brand new; this is how it was presented to me upon my reception of gently-used it:

Look closely and you’ll be able to already see the “3301/7500” limited-edition custom mark on the inside of the right temple (or, if you prefer, “arm”…“temple” is apparently the official name) of mine (#3,301 of 7,500 total, if the verbiage is unclear).

It matches another custom mark on the inside of the case flap (with the “3301” hand-“drawn”, if not already obvious):

And here are a few shots of the charging “dock” built into the case. Per the earlier teardown video (starting at ~6:00), the case’s embedded battery has a capacity of 3,034 mAh (he says “milliamps” in the video, but I’d guessed that my alternative measurement-unit version was what he actually meant, and the markings at the center of the cell shown in the closeup at ~6:20 concur…although the markings on the left end of the cell seem to say 2,940 mAh?).

Now, for our patient, beginning with what the glasses look like immediately post-case removal:

The circular structure in the corner of the left endpiece (upper right corner from this head-on vantage point…I received research validation of my initial suspicion that glasses’ parts are traditionally location-referenced from the wearer’s perspective) is indeed the camera:

In the opposite (upper right from the wearer’s perspective) corner is what looks like another camera, although it’s not:

It’s instead (first and foremost, at least) the capture LED, brighter than the one on the Stories precursor, which alerts those around you when you’re shooting photos or video. For still images, it blinks (along with making a shutter-activation sound in the speakers, for wearer benefit):

while for video, it remains illuminated the entire time you’re recording. That said, it also has sensing capabilities, specifically to ensure others’ privacy. If you attempt to cover the capture LED with a piece of tape, etc., the camera won’t work. By the way, in the first image of this latest series, you may have also noticed other circuitry embedded in the rim on both sides of the right lens, but not around the left lens. Hold that thought for a revisit shortly.

Here’s what they look like from above, both with the temples still folded:

and fully unfolded:

and from below, with the temples now partially unfolded:

Next, let’s dive in for a closer view, beginning with the outsides of the temples. The left one, as the video shows in more detail beginning at ~1:40, contains one of the speakers (with upper and lower ports), two of the microphones (one pointed downward toward the wearer’s mouth, the other outward for ambient noise capture and subtraction purposes) and the main system PCB, comprising 32 GBytes of flash memory (along with, I suspect, an unknown amount of DRAM in a multi-die “sandwich”) and the aforementioned Qualcomm’s Snapdragon AR1 Gen 1 SoC. The packaged memory and application processor are individually covered by Faraday cages (which the video narrator refers to as “cans”), and EMC shielding (plus thermal spreading, I suspect) material spans the entirety of the PCB. Here’s an overview of the outer left temple:

along with a closer look at the front half:

and the back half of it:

Within the right temple, conversely (see the video beginning at ~4:00), although you’ll again unsurprisingly find a matching speaker (and ports) and two-microphone set, the remainder of the “guts” is quite different. First off is the battery, in this case 154 mAh (again misspoken as mA, and mentioned at ~8:30). The narrator also believes that he’s found the Bluetooth and Wi-Fi antenna structure in the right temple, leading to a reasonable assumption that the wireless transceiver chip is there, too. And there’s also a large capacitive touch sensor structure on the outside, used for glasses control via both taps of and pressed-finger movement along it.

Here’s an overview photo of the outer right temple:

Now, a close-up of the front half:

and the back half of it:

Remember those outward-facing mics I mentioned earlier? Haven’t seen them yet, have you? I finally found them while writing thanks to an illuminated loupe, even though I’d already known their general location within (or nearby) the Ray-Ban logos on both sides. Post your specific-location guesses in the comments, and I’ll put the answer there a few weeks post-publication!

Before examining both temples’ insides, let’s first cover their upper and lower regions. Back to the left temple; here’s an overview of the top edge first:

and a close-up of the upper speaker port.

Now, the underside of the left temple:

with another speaker port along with, ahead of it, the aperture for the down-facing microphone.

The right temple is similar, with one exception: a topside switch near the hinge. But you’ve seen it in action before; it’s the camera shutter button. Topside first:

and underside.

Now for the temples’ inner sides. Left first, beginning with an overview shot:

The front half:

A closeup of the power switch (Pro tip: Don’t forget, as I did, to turn the glasses on prior to attempting to pair them with your smartphone. Simply ensuring they’re in the case is insufficient!):

Now the back half:

Moving over to the right side now:

Front half:

There’s that limited-edition notation (numerically matching the other one, thankfully) again!

And the back half:

There’s one area of the glasses left to explore, with many more interesting bits encompassed to showcase than you might initially expect. Behold the backside of the front frame:

Not much of note in the left half, aside from that dark area running horizontally through the bridge and over the lens, which I’ll discuss in detail next:

The right half, on the other hand, is hardware-rich (as alluded to earlier in this writeup):

That embedded structure at far right is the wearer-viewable notification LED, with varying colors (and steady or blinking states) dependent on the glasses’ mode and what’s being communicated:

And the assemblage on the left side of the lens, running along the right portion of the nose piece? It has dual (at least) purposes. Those who remember the charging contacts inside the case may be unsurprised to learn that there’s a matching set here. And those with really good memories may also recall that I earlier mentioned a five-microphone array, although we’ve so far only seen four of ‘em. Where’s the fifth? It’s here, too:

Regarding the mysterious dark region spanning the entirety of the top of the front frame, notably including the bridge, you may have already caught that the camera shutter button is on the opposite side of the glasses from the actual camera. More generally, as already noted, there’s no shortage of bidirectional interaction between the power, communications, and touch electronics on the right and the processing electronics on the left, not to mention the bilateral audio input and output facilities. Turns out there’s a whole mess of wiring in the front frame, as a particularly brutal segment of the teardown video starting at ~4:35 reveals. Fair warning: the use of hand tools, bare hands, and (ultimately) a Dremel to chop the front frame into pieces isn’t for the squeamish. That said, I did learn a new term: insert injection molding. From Wikipedia:

Pre-moulded or machined components can be inserted into the cavity while the mould is open, allowing the material injected in the next cycle to form and solidify around them. This process is known as insert moulding and allows single parts to contain multiple materials.

One feature implementation remains a mystery, although I have a theory. There’s a Wear Detection sensor somewhere that detects whether you’ve put the glasses on your face. I’ve read lots of theories online as to how this function might be implemented, although nobody has seemingly yet definitively determined how it is implemented. One thing that I can say with certainty from my experimentation is that the sensor’s not anywhere on either/both temple(s), since I’ve experimented by covering them with paper “sleeves” (which they protectively come with from the factory) and Wear Detection still works.

My guess is that there’s actually no special sensor at all; that the glasses instead detect the slight current flow caused by skin conduction (also known as galvanic skin response and electrodermal activity, among other terminology) between the two charging contacts when pressed up against the wearer’s nose. Part of the rationale for my theory is that it incurs no additional bill-of-materials cost, assuming that the power management controller between the charging contacts and the battery is sufficiently intelligent to handle this additional discernment task. And part of it is that the function can be user-disabled if found to be unreliable, which inconsistent electrodermal activity certainly is, both person-to-person and moment-to-moment. Not to mention that if you’ve got a wide nose, it may never touch the bridge underside at all.

And with that, nearing 3,000 words and as-always mindful of Aalyia’s wrath (more accurately: her precious, not-unlimited time and energy), I’ll wrap up for today with one more photo, taken using my AI Glasses of the view looking west from my back deck toward the Rocky Mountains:

I’m not terribly fond of the 3024×4032 pixel portrait orientation (which can’t be helped unless I took pictures with my head at an awkward 90° to the usual vertical instead, I suppose). But otherwise, not bad, eh? More on-head AI Glasses usage observations to come in future posts. Until then, let me know what you think so far in the comments!

—Brian Dipert is the Editor-in-Chief of the Edge AI and Vision Alliance, and a Senior Analyst at BDTI and Editor-in-Chief of InsideDSP, the company’s online newsletter.

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Can't get most chips in DIP anymore... submitted by /u/Separate-Choice [link] [comments]

god damn those LGA packages submitted by /u/brotoro [link] [comments]

Renesas Electronics Corp of Tokyo, Japan says that, as a resuts of entering into a restructuring support agreement with Wolfspeed Inc of Durham, NC, USA and its principal creditors for the financial restructuring of Wolfspeed, it hence expects to record a financial loss...