Feed aggregator

Firmware over-the-air updates and remote cryptographic key management provide scalable solutions for addressing IoT security challenges

International cybersecurity regulations continue to adapt to meet the evolving threat landscape. One major focus is on outdated firmware in IoT devices, which can present significant security vulnerabilities. To address these challenges, Microchip Technology is enhancing its TrustMANAGER platform to include secure code signing and Firmware Over-the-Air (FOTA) update delivery as well as remote management of firmware images, cryptographic keys and digital certificates. These advancements support compliance with the European Cyber Resilience Act (CRA) which mandates strong cybersecurity measures for digital products sold in the European Union (EU). Aligned with standards like the European Telecommunications Standards Institute (ETSI) EN 303 645 baseline requirements of cybersecurity for consumer IoT and the International Society of Automation (ISA)/International Electrotechnical Commission (IEC) 62443 security of industrial automation and control systems standards, the CRA sets a precedent that is expected to influence regulations worldwide.

Microchip’s ECC608 TrustMANAGER leverages Kudelski IoT’s keySTREAM Software as a Service (SaaS) to deliver a secure authentication Integrated Circuit (IC) that is designed to store, protect and manage cryptographic keys and certificates.  With the addition of FOTA services, the platform helps customers securely deploy real-time firmware updates to remotely patch vulnerabilities and comply with cybersecurity regulations.

“As evolving cybersecurity regulations require connected device manufacturers to prioritize the implementation of mechanisms for secure firmware updates, lifecycle credential management and effective fleet deployment,” said Nuri Dagdeviren, corporate vice president of Microchip’s security products business unit. “The addition of FOTA services to Microchip’s TrustMANAGER platform offers a scalable solution that removes the need for manual, and expensive, static infrastructure security updates. FOTA updates allow customers to save resources while fulfilling compliance requirements and helping to future-proof their products against emerging threats and evolving regulations.”

Further enhancing cybersecurity compliance, the Microchip WINCS02PC Wi-Fi network controller module used in the TrustMANAGER development kit is now certified against the Radio Equipment Directive (RED) for secure and reliable cloud connectivity. RED establishes strict standards for radio devices in the EU, focusing on network security, data protection and fraud prevention. Beginning August 1, 2025, all wireless devices sold in the EU market must adhere to RED cybersecurity provisions.

By incorporating these additional services, TrustMANAGER—governed by keySTREAM—tackles key challenges with IoT security, regulatory compliance, device lifecycle management and fleet management. This solution is designed to serve IoT device manufacturers and industrial automation providers.

Development Tools

The ECC608 TrustMANAGER is compatible with the MPLAB X Integrated Development Environment (IDE) and supported by Microchip’s CryptoAuth PRO development board (EV89U05A) and the CryptoAuthLib software library. The Trust Platform Design Suite (TPDS) contains a use case example including onboarding educational steps and a firmware code example to enable the keySTREAM service to AWS with the ECC608 secure element running on a 32-bit Arm Cortex-M4-based PIC32CX SG41MCU and a WINCS02PC Wi-Fi module.

The post Microchip Enhances TrustMANAGER Platform to Support CRA Compliance and Cybersecurity Regulations appeared first on ELE Times.

submitted by /u/Linker3000 [link] [comments]

PWM is a simple, cool, cheap, cheerful, and (therefore) popular DAC technology. Excellent differential nonlinearity (DNL) and monotonicity are virtually guaranteed by PWM. Also guaranteed are a stable zero and a full-scale accuracy that’s generally limited only by the quality of the voltage reference. However, PWM’s integral nonlinearity (INL) isn’t always terrific, and the necessity for low-pass filtering-out of ripple means its speed isn’t too swift either. These messy topics are covered in…

1. A common cause of, and a software cure for, PWM INL is discussed here in “Minimizing passive PWM ripple filter output impedance: How low can you go?”
2. The slow PWM settling times (Ts) that can be problematic, together with a way to reduce them, are addressed here in “Cancel PWM DAC ripple with analog subtraction.”

Figure 1 offers a tricky, totally analog strategy for both. The ploy in play is Take Back Half (TBH). It relies on two differential relationships that effectively subtract (take back) the error terms.

1. For signal frequencies less than or equal to 1/Ts (including DC) Xc >> R and Z = 2(Xavg – Yavg/2).
2. For frequencies greater than or equal to Fpwm, Xc << R and Z = Xripple – Yripple.

Figure 1 All Rs and Cs are nominally equal. The circuit relies on two differential relationships that effectively subtract the error terms for the TBH methodology.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Because only one switch drives load R at node Y while two in parallel drive X, INL due to switch loading at Y is exactly twice that at X. Therefore, Z = 2(Xavg – Yavg/2) takes back, cancels the error, and has (theoretically) zero INL.

Xripple = Yripple, so Z = Xripple – Yripple = 0 nulls it out, has likewise (theoretically) zero ripple, and ripple filter RC time constants can be made faster and settling times shorter.

The DC conversion component at Z = -PWM_duty_factor * Vref. Conversion accuracy is precisely unity, independent of resistance and capacitance tolerances. However, they ideally should be accurately equal for best ripple and nonlinearity cancellation.

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

 Related Content

• Minimizing passive PWM ripple filter output impedance: How low can you go?
• Cancel PWM DAC ripple with analog subtraction
• Temperature controller has “take-back-half” convergence algorithm
• 20MHz VFC with take-back-half charge pump
• Take-Back-Half precision diode charge pump

The post Take back half improves PWM integral linearity and settling time appeared first on EDN.

Funded by the European Commission under the Horizon 2020 program as a collaborative research and innovation initiative (grant agreement n°101016138), the recently concluded 42-month project ELENA (‘European electro-optic and nonlinear PIC platform based on lithium niobate’) has developed the first European-made lithium niobate on insulator (LNOI) substrates for photonic integrated circuits (PICs), establishing a complete European supply chain for thin-film lithium niobate (TFLN) technology...

Засідання Наглядової ради проєкту «Коаліція укриттів цивільного захисту» kpi ср, 06/25/2025 - 12:43

EPC Space LLC of Haverhill, MA, USA (which provides high-reliability radiation-hardened enhancement-mode gallium nitride-on-silicon transistors and ICs for power management in space and other harsh environments) has launched the EPC7030MSH, a rad-hard (RH) 300V GaN FET that delivers what is claimed to be unmatched performance for high-voltage, high-power space applications, including next-generation satellite power plants and electric propulsion systems...

Silvaco Group Inc of Santa Clara, CA, USA — which provides technology computer-aided design (TCAD), electronic design automation (EDA) software and semiconductor intellectual property (SIP) for process and device development — has announced a strategic R&D collaboration with Fraunhofer Institute for Silicon Technology (ISIT) of Itzehoe, Germany, which develops and manufactures customer-specific components for power electronics and microsystems technology...

XVI Міжнародна конференція "Інновації молоді в машинобудуванні" Інформація КП ср, 06/25/2025 - 00:00

Gallium nitride (GaN) will likely be key for the next generation of high-speed communication systems and the power electronics needed for state-of-the-art data centers, but its high cost and the specialization required to incorporate it into conventional electronics have limited its use in commercial applications, notes the USA’s Massachusetts Institute of Technology (MIT)...

Features Has many gpio pins Does the job Custom 3D-printed Case Based on STM32F103C8 microcontroller USB-C interface RTC (Real-Time Clock) capabilities Embedded microcontroller; low power consumption Check the REPO pcb and gerber files As always Thank you for reading this <3 submitted by /u/PTSSSINZOFF [link] [comments]

Photonic chips industry accelerator PhotonDelta of Eindhoven, the Netherlands (which connects and collaborates with an ecosystem of photonic chip technology organizations worldwide) and Luminate NY of Rochester, NY, USA (the world’s largest accelerator for startups working on optics, photonics and imaging-enabled technologies) have entered into a strategic collaboration to support the growth of early-stage photonics companies across North America and the Netherlands...

The UK Government says that Compound Semiconductor Applications (CSA) Catapult will mobilize the new UK Semiconductor Centre (UKSC)...

The world we are living in is increasingly becoming software-defined, where artificial intelligence (AI) is adding the next layer of functionality. And it’s driving the need for more compute to enable the software-enabled functionality. However, with this huge progression in compute content, Moore’s Law scaling will be insufficient to support the number of transistors for the needed compute.

Enter 3D ICs, disaggregating the functionality of silicon into a set of chiplets and then heterogeneously integrating them on an advanced integration platform. “Hyperscalers, driving the compute envelope, are particularly pushing the extreme where 3D ICs are needed,” said Michael White, VP of Calibre Design Solutions at Siemens EDA.

White also noted automotive designs where self-driving technology content is driving the need for 3D ICs. At the Design Automation Conference (DAC) held in San Francisco, California, on 22-25 June 2025, Siemens EDA announced two key additions to its EDA portfolio to address and overcome the complexity challenges associated with the design and manufacture of 2.5D and 3D IC devices.

First, the company’s Innovator3D IC suite enables chip designers to efficiently author, simulate, and manage heterogeneously integrated 2.5D and 3D IC designs. Second, its Calibre 3DStress software leverages advanced thermo-mechanical analysis to identify the electrical impact of stress at the transistor level.

Figure 1 The new tools aim to dramatically reduce risk and enhance the design, yield, and reliability of complex, next-generation 2.5D/3D IC designs. Source: Siemens EDA

“These solutions help designers achieve the needed compute performance while increasing yield and reliability and reducing cost,” White added. “They also offer the ability to leverage higher bandwidth between the chiplets placed on an interposer.” He calls this an inflection point in the design process and tools needed for the design flows.

Chiplet integration with Innovator3D IC

Keith Felton, principal technical product manager for 3D IC solutions at Siemens EDA, expanded on 3D IC being an inflection point, marking a transition from single design-centric approach to system-centric approach. “It impacts design flows and tools, necessitating a system-centric approach from early planning through final sign-off in four ways,” he added.

First, chip designers need system floor planning to optimize power, performance, area, and reliability across silicon, package, interposer, and even PCB. Second, they must start using multi-physics modeling to simulate complex thermo-mechanical interactions that impact electrical and structural performance.

Third, IC designers need to have a methodology for scalability to manage and communicate heterogeneous data across enterprise-wide teams and maintain digital continuity because there are hundreds of silicon designs encompassing chiplets. Fourth, designers must have a methodology for multi-die sign-off, enabling 3D verification of connectivity, interfaces, interconnect reliability, and electrostatic discharge (ESD) resiliency.

So, Innovator3D IC suite provides a fast, predictable path for planning and heterogeneous integration, substrate/interposer implementation, interface protocol analysis compliance and data management of designs, and design data IP.

Figure 2 Innovator3D IC suite facilitates design, verification, and data management of 2.5D and 3D IC chiplets. Source: Siemens EDA

Innovator3D IC—comprising four building blocks—offers an AI-infused user experience with extensive multithreading and multicore capabilities to achieve optimal capacity and performance on 5+ million pin designs. First, Innovator3D IC Integrator comes with a consolidated cockpit for constructing a digital twin, using a unified data model for design planning, prototyping, and predictive analysis.

Second, Innovator3D IC Layout facilitates correct-by-construction package interposer and substrate implementation. Third, Innovator3D IC Protocol Analyzer can be used for chiplet-to-chiplet and die-to-die interface compliance analysis. It’ll be critical in ensuring compliance with protocols such as Universal Chiplet Interconnect Express (UCIe). Finally, the Innovator3D IC Data Management part is targeted at the work-in-progress management of designs and design data IP.

“Innovator3D IC is targeting the optimization of 2.5 and 3D IC design performance to eliminate late-stage changes by enabling early prototyping and planning,” Felton said. “It accelerates compliance with protocols for chiplet integration and provides a core workflow that design teams need for 3D IC chiplet integration.”

Calibre 3DStress for package verification

Calibre 3DStress—the second part of Siemens EDA’s solution to streamline the design and analysis of complex, heterogeneously integrated 3D ICs—supports accurate, transistor-level analysis, verification, and debugging of thermo-mechanical stresses and warpage in the context of 3D IC packaging.

It enables IC designers to assess how chip-package interaction will impact the functionality of their designs earlier in the development cycle. Shetha Nolke, principal product manager for Calibre 3DStress at Siemens EDA, told EDN that this tool performs three key tasks for chip-package stress analysis in 3D IC designs.

First, stress simulation ensures accurate die levels under thermal and mechanical conditions. Second, what-if analysis optimizes IP, cell, or chip placement during early design stages. Third, it performs stress-aware circuit analysis using back annotation of device stress to minimize electrical impact.

Figure 3 With the thinner dies and higher package processing temperatures of 2.5D/3D IC architectures, designers often discovered that designs validated and tested at the die level no longer conform to specifications after packaging reflows. Source: Siemens EDA

3D ICs increasingly face stress- and warpage-related packaging challenges. That includes thermal challenges such as non-uniform heat generation and dissipation, which can result in higher temperatures and temperature gradients. Then, there are thermo-mechanical issues, where packaging process stages experience high temperature and fixed constraints.

Finally, thinned dies and ultra-low-k dielectrics increase mechanical stress-induced problems. “As multiple chiplets are integrated into a package, they experience thermal impacts because heat is not able to escape readily,” Nolke said. “While mechanical aspects are coming from incorporating package components, Calibre 3DStress can model it before fabrication.”

Calibre 3DStress delivers accurate die-level stress simulation using finite element analysis at a nano-meter feature scale. It also provides visualization of stress and warpage results while facilitating electrical and mechanical verification.

Related Content

• TSMC, Arm Show 3DIC Made of Chiplets
• One-stop advanced packaging solutions for chiplets
• Cadence to Buy Artisan to Support Chiplet, 3D IC Future
• Cadence enables multi chiplet design with Integrity 3D-IC platform
• Advanced IC Packaging: The Roadmap to 3D IC Semiconductor Scaling

The post New EDA tools arrive for chiplet integration, package verification appeared first on EDN.

Фінансування престижного міжнародного конкурсу Erasmus+ для проекту кафедри ХТФ kpi вт, 06/24/2025 - 15:27

Keysight, Teledyne LeCroy, Tektronix, Rohde & Schwarz (R&S), and others have offered built-in digital oscilloscope Bode analysis for some time, and this feature has trickled down to low-cost DSOs like the Siglent SDS2000X Plus and the new SDS814X HD. These DSOs feature built-in Bode analysis when operating with a companion AWG, or sometimes include the AWG within (SDS2000X Plus), at an affordable price point.

Wow the engineering world with your unique design: Design Ideas Submission Guide

DIY common-mode choke

One of the interesting applications of this Bode capability is investigating the open-loop response of closed-loop systems, such as oscillators. This often requires an expensive isolation transformer, which can be limiting. However, for those with a DIY spirit, a reconfigured common-mode choke serves as a nice isolation transformer for Bode analysis (Figure 1) [1].

Figure 1 A reconfigured common-mode choke isolation transformer used to investigate the open-loop response of closed-loop systems, e.g., oscillators, using the Bode capability of a benchtop oscilloscope.

Creating the isolation transformer is straightforward. Physically larger common-mode “chokes” utilized in AC mains, like the one shown, make good candidates, especially for lower frequencies.

Here, 5 mH and 2 mH Prod Tech PDMCAT221413 types were utilized after unwinding and rewinding. First, after the unwinding, the pair of wires are stretched, and then the pair of wires are twisted together (a hand drill helps). This leaves a long twisted pair which is threaded through the core as many times as possible.

As shown in Figure 2, the wrapped core now has two ends with the twisted pair, and at each end, a pair of wires. The ends of the wire on each side are common with the other pair of wires’ ends (use an ohmmeter), becoming the primary or secondary. Either way, it doesn’t matter since the isolation transformer has a 1:1 turns ratio and is symmetrical. The primary and secondary can be resistively terminated as needed for specific applications.

Figure 2 A side-view of the DIY isolation transformer showing the wrapped core and terminated with four 2-W, 100-Ω resistors.

Figure 3 shows the test setup utilizing the DIY isolation transformer to measure the open-loop response of a Peltz oscillator, as described in another Design Idea (DI): “Simple 5-component oscillator works below 0.8V.”

Figure 3 Test setup using the DIY isolation transformer to measure the open-loop response of a Peltz oscillator.

Peltz oscillator test circuit and results

The isolation transformer secondary is connected between Q2 base and Q1 collector. Q1 and Q2 are 2N3904s, L is 470 µH, C is 0.022 µF, and R is 510 Ω (Figure 4).

Figure 4 The configuration of the Peltz oscillator circuit, where the isolation transformer is connected between Q2 base and Q1 collector to measure open-loop response.

For comparison, an LTspice circuit model was created. The simulated and measured results using the SDS2504X Plus are shown in Figure 5.

Figure 5 Simulated (top) and measured (bottom) results with the circuit under test in Figure 4 operating with the following values: L is 470 µH, C is 0.022 µF, and R is 510 Ω.

Changing the inductor to 100 µH (measured 97.3 µH) which moves the center frequency to 34.4 kHz (Figure 6).

Figure 6 Simulated (top) and measured (bottom) results with the circuit under test in Figure 4 operating with the following values: L is 100 µH, C is 0.022 µF, and R is 510 Ω.

Typically, physically larger common-mode chokes have higher inductance, which can extend the measurement range to lower frequencies. Having a larger core also allows for more turns, which also helps with lower frequencies.

However, larger cores and more turns limit the upper frequency end, and having more cores, smaller and larger, can cover a wider frequency range than a single-core transformer. I’ve had good results with the cores shown from less than 100 Hz to over 1 MHz.

This is just one of the many uses for modern Bode-enabled DSOs with companion AWGs and a few DIY isolation transformers.

Michael A Wyatt is a life member with IEEE and has continued to enjoy electronics ever since his childhood. Mike has a long career spanning Honeywell, Northrop Grumman, Insyte/ITT/Ex-elis/Harris, ViaSat and retiring (semi) with Wyatt Labs. During his career he accumulated 32 US Patents and in the past published a few EDN Articles including Best Idea of the Year in 1989.

Related Content

• Simple 5-component oscillator works below 0.8V
• Injection locking acts as a frequency divider and improves oscillator performance
• Investigating injection locking with DSO Bode function
• DIY custom Tektronix 576 & 577 curve tracer adapters

References

1. https://www.eevblog.com/forum/testgear/diy-transformer-for-use-with-bode-plots/

The post DIY isolation transformer enhances Bode analysis with modern DSOs appeared first on EDN.

Питання інженерії поверхні в авіадвигунобудуванні держава визнає серед найактуальніших Інформація КП вт, 06/24/2025 - 13:00

At the end of this year, research institute TNO (the Netherlands Organization for Applied Scientific Research in Delft) will begin constructing a pilot manufacturing line for photonic chips at the High Tech Campus in Eindhoven. The new factory will enable the industrial-scale production of indium phosphide (InP)-based photonic chips. Additionally, the scaling up from 4-inch to 6-inch wafers will make production more efficient. TNO is collaborating on this with the Photonic Integration Technology Centre (PITC), Eindhoven University of Technology, and the University of Twente...

Efficient Power Conversion Corp (EPC) of El Segundo, CA, USA — which makes enhancement-mode gallium nitride on silicon (eGaN) power field-effect transistors (FETs) and integrated circuits for power management applications — has released the EPC91109, a high-performance evaluation board designed to demonstrate the benefits of eGaN FETs in a compact, thermally efficient, two-phase synchronous buck converter. Targeting USB Power Delivery (USB-PD 3.1) applications up to 180W, the EPC91109 is optimized for space- and power-constrained designs such as laptops, portable devices, and battery-powered systems...

Building a dual rail power supply 0-40v and didn't have any 4700uf or bigger capacitors so a row of 1000x2 + 680x2 + 470x2 + 330x2 + 220x4 + 100x2 for a total of 6 040 will have to do. submitted by /u/Whyjustwhydothat [link] [comments]