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As technology advances, most everyday devices depend on short-range communication to exchange or gather data. Although wireless technologies such as Wi-Fi and Bluetooth dominate the market, they are not always the ideal option especially for low-power applications where efficiency, simplicity, and cost management are most important. In these instances, infrared (IR) communication is still an efficient option that energizes applications such as smart meters, wearable electronics, medical devices, and remote controls.

But using an infrared link is not always easy. An IR diode cannot just be attached to a microcontroller pin and be efficient. In order to avoid saturating the diode and to provide a robust signal, a low-frequency carrier is often employed, which then must be modulated by the data stream. Historically, this has involved using more modem chips, timers, and mixers increasing cost, complexity, and additional board space to the design.

The Inefficient Signal Generation Challenge

Fundamentally, infrared communication relies on two key signals:

1. Carrier Frequency – a square wave that paces the IR diode at a suitable frequency.
2. Data Stream – the content of the communication, which must modulate the carrier.

In most implementations, these signals are from various peripherals on a microcontroller and must be merged externally. This adds more components and uses multiple I/O pins, which is not conducive to small, battery-powered devices.

A Smarter Way Forward

Since recent microcontrollers started meeting this challenge, they now provide easier mechanisms for IR signal generation. Instead of needing a separate modem chip, some of these devices combine the timer output (carrier frequency) with the communication output (data) internally. The result is a ready modulation that can directly drive an infrared diode.

An example that offers such capability is RA4C1. Being an 80 MHz device with low-power operating modes down to 1.6 V, it offers an SCI/AGT mask function that combines a UART or IrDA interface output with a timer signal and thus makes it possible to generate the required modulated IR output without any external hardware.

Design Flexibility

The reason this method is efficient is because it is flexible:

• Developers have the option of utilizing a basic UART output that is modulated by a timer-generated carrier.
• Or they can implement an integrated IrDA interface, with provisions for direct modulation or phase-inverted output based on the application requirement.

Both schemes present a clean, stable signal while minimizing the amount of external components and I/O pins needed.

For designers of small electronics like handheld meters, fitness monitors, or household appliances space and power efficiency are key considerations. An IR communication solution with minimal IR circuitry saves cost and enhances reliability by eliminating outside circuitry. It also aids in speeding up product development as engineers no longer need to spend extra time connecting individual modem chips or modulation hardware.

Conclusion:

Infrared communication remains to provide a reliable, low-cost solution for short-range connectivity, particularly in environments where the inclusion of a full radio system is not warranted. With newer microcontrollers embracing built-in modulation capabilities, establishing an IR connection has never been simpler. This change makes it possible for developers to provide smarter, power-sensing products while maintaining simplicity and low cost.

(This article has been adapted and modified from content on Renesas.)

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Power over Ethernet (PoE) is not rocket science, but it’s not plug-and-play magic either. This short primer walks through the basics with a few practical nudges for those curious to try it out.

It’s a technology that delivers electrical power alongside data over standard twisted-pair Ethernet cables. It enables a single RJ45 cable to supply both network connectivity and power to powered devices (PDs) such as wireless access points, IP cameras, and VoIP phones, eliminating the need for separate power cables and simplifying installation.

PoE essentials: From devices to injectors

Any network device powered via PoE is known as a powered device or PD, with common examples including wireless access points, IP security cameras, and VoIP phones. These devices receive both data and electrical power through Ethernet cables from power sourcing equipment (PSE), which is classified as either “endspan” or “midspan.”

An endspan—also called an endpoint—is typically a PoE-enabled network switch that directly supplies power and data to connected PDs, eliminating the need for a separate power source. In contrast, when using a non-PoE network switch, an intermediary device is required to inject power into the connection. This midspan device, often referred to as a PoE injector, sits between the switch and the PD, enabling PoE functionality without replacing existing network infrastructure. A PoE injector sends data and power together through one Ethernet cable, simplifying network setups.

Figure 1 A PoE injector is shown with auto negotiation that manages power delivery safely and efficiently. Source: http://poe-world.com

The above figure shows a PoE injector with auto negotiation, a safety and compatibility feature that ensures power is delivered only when the connected device can accept it. Before supplying power, the injector initiates a handshake with the PD to detect its PoE capability and determine the appropriate power level. This prevents accidental damage to non-PoE devices and allows precise power delivery—whether it’s 15.4 W for Type 1, 25.5 W for Type 2, or up to 90 W for newer Type 4 devices.

Note at this point that the original IEEE 802.3af-2003 PoE standard provides up to 15.4 watts of DC power per port. This was later enhanced by the IEEE 802.3at-2009 standard—commonly referred to as PoE+ or PoE Plus—which supports up to 25.5 watts for Type 2 devices, making it suitable for powering VoIP phones, wireless access points, and security cameras.

To meet growing demands for higher power delivery, the IEEE introduced a new standard in 2018: IEEE 802.3bt. This advancement significantly increased capacity, enabling up to 60 watts (Type 3) and circa 100 watts (Type 4) of power at the source by utilizing all four pairs of wires in Ethernet cabling compared to earlier standards that used only two pairs.

As indicated previously, VoIP phones were among the earliest applications of PoE. Wireless access points (WAPs) and IP cameras are also ideal use cases, as all these devices require both data connectivity and power.

Figure 2 This PoE system is powering a fixed wireless access (FWA) device.

As a sidenote, an injector delivers power over the network cable, while a splitter extracts both data and power—providing an Ethernet output and a DC plug.

A practical intro to PoE for engineers and DIYers

So, PoE simplifies device deployment by delivering both power and data over a single cable. For engineers and DIYers looking to streamline installations or reduce cable clutter, PoE offers a clean, scalable solution.

This brief session outlines foundational use cases and practical considerations for first-time PoE users. No deep dives: just clear, actionable insights to help you get started with smarter, more efficient connectivity.

Up next is the tried-and-true schematic of a passive PoE injector I put together some time ago for an older IP security camera (24 VDC/12 W).

Figure 3 Schematic demonstrates how a passive PoE injector powers an IP camera. Source: Author

In this setup, the LAN port links the camera to the network, and the PoE port delivers power while completing the data path. As a cautionary note, use a passive PoE injector only when you are certain of the device’s power requirements. If you are unsure, take time to review the device specifications. Then, either configure a passive injector to match your setup or choose an active PoE solution with integrated negotiation and protection.

Fundamentally, most passive PoE installations operate across a range of voltages, with 24 V often serving as practical middle ground. Even lower voltages, such as 12 V, can be viable depending on cable length and power requirements. However, passive PoE should never be applied to devices not explicitly designed to accept it; doing so risks damaging the Ethernet port’s magnetics.

Unlike active PoE standards, passive PoE delivers power continuously without any form of negotiation. In its earliest and simplest form, it leveraged unused pairs in Fast Ethernet to transmit DC voltage—typically using pins 4–5 for positive and 7–8 for negative, echoing the layout of 802.3af Mode B. As Gigabit Ethernet became common, passive PoE evolved to use transformers that enabled both power and data to coexist on the same pins, though implementations vary.

Seen from another angle, PoE technology typically utilizes the two unused twisted pairs in standard Ethernet cables—but this applies only to 10BASE-T and 100BASE-TX networks, which use two pairs for data transmission.

In contrast, 1000BASE-T (Gigabit Ethernet) employs all four twisted pairs for data, so PoE is delivered differently—by superimposing power onto the data lines using a method known as phantom power. This technique allows power to be transmitted without interfering with data, leveraging the center tap of Ethernet transformers to extract the common-mode voltage.

PoE primer: Surface touched, more to come

Though we have only skimmed the surface, it’s time for a brief wrap-up.

Fortunately, even beginners exploring PoE projects can get started quickly, thanks to off-the-shelf controller chips and evaluation boards designed for immediate use. For instance, the EV8020-QV-00A evaluation board—shown below—demonstrates the capabilities of the MP8020, an IEEE 802.3af/at/bt-compliant PoE-powered device.

Figure 4 MPS showcases the EV8020-QV-00A evaluation board, configured to evaluate the MP8020’s IEEE 802.3af/at/bt-compliant PoE PD functionality. Source: MPS

Here are my quick picks for reliable, currently supported PoE PD interface ICs—the brains behind PoE:

• TI TPS23730 – IEEE 802.3bt Type 3 PD with integrated DC-DC controller
• TI TPS23731 – No-opto flyback controller; compact and efficient
• TI TPS23734 – Type 3 PD with robust thermal performance and DC-DC control
• onsemi NCP1081 – Integrated PoE-PD and DC-DC converter controller; 802.3at compliant
• onsemi NCP1083 – Similar to NCP1081, with auxiliary supply support for added flexibility
• TI TPS2372 – IEEE 802.3bt Type 4 high-power PD interface with automatic MPS (maintain power signature) and autoclass

Similarly, leading semiconductor manufacturers offer a broad spectrum of PSE controller ICs for PoE applications—ranging from basic single-port controllers to sophisticated multi-port managers that support the latest IEEE standards.

As a notable example, TI’s TPS23861 is a feature-rich, 4-channel IEEE 802.3at PSE controller that supports auto mode, external FET architecture, and four-point detection for enhanced reliability, with optional I²C control and efficient thermal design for compact, cost-effective PoE systems.

In short, fantastic ICs make today’s PoE designs smarter and more efficient, especially in dynamic or power-sensitive environments. Whether you are refining an existing layout or venturing into high-power applications, now is the time to explore, prototype, and push your PoE designs further. I will be here.

T. K. Hareendran is a self-taught electronics enthusiast with a strong passion for innovative circuit design and hands-on technology. He develops both experimental and practical electronic projects, documenting and sharing his work to support fellow tinkerers and learners. Beyond the workbench, he dedicates time to technical writing and hardware evaluations to contribute meaningfully to the maker community.

Related Content

• More opportunities for PoE
• A PoE injector with a “virtual” usage precursor
• Simple circuit design tutorial for PoE applications
• Power over Ethernet (PoE) grows up: it’s now PoE+
• Power over Ethernet (PoE) to Power Home Security & Health Care Devices

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Fusion energy company Blue Laser Fusion Inc (BLF) of Santa Barbara, CA, USA (founded in 2022 by CEO professor Shuji Nakamura, winner of the Nobel Prize in Physics in 2014 and member of the RSE Scientific Committee) has won a US Department of Energy (DOE) INFUSE project award to further develop its novel high-energy pulsed laser for inertial fusion energy applications in collaboration with Colorado State University (CSU)...

Quintauris and Everspin Technologies, Inc. announced a strategic collaboration to bring advanced memory solutions into the Quintauris ecosystem.

The collaboration aims to strengthen the reliability and safety of RISC-V–based platforms, particularly for automotive, industrial and edge applications where data persistence, integrity, low latency and security are critical.

By integrating Everspin’s proven MRAM technologies with Quintauris’ reference architectures and real-time platforms, the partnership works to ensure memory subsystems meet the highest standards for performance and functional safety – one of the most pressing challenges in safety-driven markets.

Everspin’s strong commitment to the automotive market extends beyond technology to include proper certifications, manufacturing excellence, long-term supply and continuous quality improvement, values that align closely with Quintauris’ mission to make RISC-V commercially ready for automotive programs.

“Everspin’s leadership in MRAM and their track record of over 200 million products deployed make them a strong addition to our ecosystem,” said Pedro Lopez, Market Strategy Officer at Quintauris. “Together, we are closing the gap between innovation and dependability, enabling RISC-V to be confidently adopted in next-generation automotive programs.”

“RISC-V is opening new doors in safety-critical computing, but it also demands memory that can match its performance and reliability,” said David Schrenk, VP Business Development at Everspin Technologies. “By integrating our MRAM into the Quintauris platform, we’re helping developers build systems that retain data integrity under power loss, radiation or extreme temperatures, without compromising speed or security. This partnership strengthens the foundation for scalable, dependable platforms that will shape the future of automotive electronics.”

The post Quintauris and Everspin Technologies Partner to Advance Dependable RISC-V Solutions for Automotive appeared first on ELE Times.

Siemens claims the new software allows users to test analog circuitry in integrated circuits up to 100 times faster than traditional methods.

With over 8.9 million micromirrors, TI’s DLP991UUV digital micromirror device (DMD) enables maskless digital lithography for advanced packaging. Its 4096×2176 micromirror array, 5.4-µm pitch, and 110-Gpixel/s data rate remove the need for costly mask technology while providing scalability and precision for increasingly complex designs.

The DMD is a spatial light modulator that controls the amplitude, direction, and phase of incoming light. Paired with the DLPC964 controller, the DLP991UUV DMD supports high-speed continuous data streaming for laser direct imaging. Its resolution enables large 3D-print build sizes, fine feature detail, and scanning of larger objects in 3D machine vision applications.

Offering the highest resolution and smallest mirror pitch in TI’s Digital Light Processing (DLP) portfolio, the DLP991UUV provides precise light control for industrial, medical, and consumer applications. It steers UV wavelengths from 343 nm to 410 nm and delivers up to 22.5 W/cm² at 405 nm.

Preproduction quantities of the DLP991UUV are available now on TI.com.

DLP991UUV product page 

Texas Instruments 

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AIchip Technologies and Ayar Labs unveiled a co-packaged optics (CPO) solution for multi-rack AI clusters, providing extended reach, low latency, and high radix. The joint development tackles AI infrastructure data-movement bottlenecks by replacing copper interconnects with CPO in large-scale accelerator deployments.

The offering integrates Ayar’s TeraPHY optical engines with AIchip’s advanced packaging on a common substrate, bringing optical I/O directly to the AI accelerator interface. This enables over 100 Tbps of scale-up bandwidth per accelerator and supports more than 256 optical scale-up ports per device. TeraPHY is also protocol agnostic, allowing flexible integration with customer-designed chiplets and fabrics.

The co-packaged solution scales multi-rack networks without the power and latency penalties of pluggable optics by shortening electrical traces and placing optical I/O close to the compute core. With UCIe support and flexible protocol endpoints at the package boundary, it integrates alongside compute tiles, memory, and accelerators while maintaining performance, signal integrity, and thermal requirements.

Both companies are working with select customers to integrate co-packaged optics into next-generation AI accelerators and scale-up switches. They will provide collateral, reference architectures, and build options to qualified design teams.

Ayar Labs 

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Purpose-built for Lantronix Open-Q system-on-modules (SOMs), EdgeFabric.ai is a no-code development platform for designing and deploying edge AI applications. According to Lantronix, it helps customers move AI from prototype to production in minutes instead of months, without needing a team of AI experts.

The visual orchestration platform integrates with Open-Q hardware and leading AI model ecosystems, automatically configuring performance across Qualcomm GPUs, DSPs, and NPUs. It streamlines data pipelines with drag-and-drop workflows for AI, video, and sensors, while delivering real-time visualization. Prebuilt templates support common use cases such as surveillance, anomaly detection, and safety monitoring.

EdgeFabric.ai auto-generates production-ready code in Python and C++, making it easy to build and adjust pipelines, fine-tune parameters, and adapt workflows quickly.

Learn more about the EdgeFabric.ai platform here. For details on Open-Q SOMs, visit SOM solutions. Lantronix also offers engineering services for development support.

Lantronix

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RA8T2 MCUs from Renesas integrate dual processors for real-time motor control in advanced factory automation and robotics. They pair a 1-GHz Arm Cortex-M85 core with an optional 250-MHz Cortex-M33 core, combining high-speed operation, large memory, timers, and analog functions on a single chip.

The Cortex-M85 with Helium technology accelerates DSP and machine-learning workloads, enabling AI functions that predict motor maintenance needs. In dual-core variants, the embedded Cortex-M33 separates real-time control from general-purpose tasks to further enhance system performance.

RA8T2 devices integrate up to 1 MB of MRAM and 2 MB of SRAM, including 256 KB of TCM for the Cortex-M85 and 128 KB of TCM for the Cortex-M33. For high-speed networking in factory automation, they offer multiple interfaces, such as two Gigabit Ethernet MACs with DMA and a two-port EtherCAT slave. A 32-bit, 14-channel timer delivers PWM functionality up to 300 MHz.

The RA8T2 series of MCUs is available now through Renesas and its distributors.

RA8T2 product page

Renesas Electronics 

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Omnivision’s OV50R40 50-Mpixel CMOS image sensor delivers single-exposure HDR up to 110 dB with second-generation TheiaCel technology. It also reduces power consumption by ~20% compared with the previous-generation OV50K40, enabling longer HDR video capture.

Aimed at high-end smartphones and action cameras, the OV50R40 achieves ultra-high dynamic range in any lighting. Built on PureCel Plus‑S stacked die technology, the color sensor supports 100% coverage quad phase detection for improved autofocus. It features an active array of 8192×6144 with 1.2‑µm pixels in a 1/1.3‑in. format and supports premium 8K video with dual analog gain (DAG) HDR and on-sensor crop zoom.

The sensor also supports 4-cell binning, producing 12.5‑Mpixel resolution at 120 fps. For 4K video at 60 fps, it provides 3-channel HDR with 4× sensitivity, ensuring enhanced low-light performance.

The OV50R40 is now sampling, with mass production planned for Q1 2026.

OV50R40 product page 

Omnivision

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Прийнято Положення про систему запобігання плагіату, фабрикації та фальсифікації kpi чт, 10/02/2025 - 21:03

💥 ІІ Міжнародна підсумкова науково-практична онлайн конференція та ІІ Міжнародний конкурс студентських наукових робіт з англійської мови “Advances in Science and Technology” kpi чт, 10/02/2025 - 20:41

TI designed the new devices to provide cost-effective, high-speed sensorless control to household and industrial systems.

The relentless pursuit of performance in sectors such as AI, cloud computing, and autonomous driving is creating a heat crisis. As the next generation of processors demand more power in smaller spaces, the switched-mode power supply (SMPS) is being pushed to its thermal limit. SMPS’s integrated circuit (IC) packages have traditionally used a large thermal pad on the bottom side of the package, known as a die attach paddle (DAP), to dissipate the majority of the heat through the printed circuit board (PCB). But as power density increases, relying on only one side of the package to dissipate heat quickly becomes a serious constraint.

A thermally enhanced package is a type of IC package designed to dissipate heat from both the top and bottom surfaces. In this article, we’ll explore the standard thermal metrics of IC packages, along with the composition, top-side cooling methods, and thermal benefits of a thermally enhanced package.

Thermal metrics of IC packages

In order to understand what a thermally-enhanced package is and why it is beneficial, it’s important to first understand the terminology for describing the thermal performance of an IC package. Three foundational metrics of thermal resistance are the junction-to-ambient thermal resistance (RθJA), the junction-to-case (top) thermal resistance (RθJC(top)), and the junction-to-board thermal resistance (RθJB).

Thermal resistance measures the opposition to the flow of heat in a medium. In IC packages, thermal resistance is usually measured in Celsius rise per watt dissipated (°C/W), or how much the temperature rises when the IC dissipates a certain amount of power.

RθJA measures the thermal resistance between the junction (J) (the silicon die itself), and the ambient air (A) around the IC. RθJC(top) measures the thermal resistance specifically between (J) and the top (t) of the case (C) or package mold. RθJB measures the thermal resistance specifically between (J) and the PCB on which the package is mounted.

RθJA significantly depends on its subcomponents—both RθJC(top) and RθJB. The lower the RθJA, the better, because it clearly indicates that there will be a lower temperature rise per unit of power dissipated. Power IC designers spend a lot of time and resources to come up with new ways to lower RθJA. A thermally enhanced package is one such way.

Thermally enhanced package composition

A thermally enhanced package is a quad flat no-lead (QFN) package that has both a bottom-side DAP and a top-side cutout of the molding to directly expose the back of the silicon die to the environment. Figure 1 shows the gray backside of the die for the Texas Instruments (TI) LM61495T-Q1 buck converter.

Figure 1 The LM61495T-Q1 buck converter in a thermally enhanced package. Source: Texas Instruments

Exposing the die on the top side of the package does two things: it lowers the RθJC(top) compared to an IC package that completely molds over the die, and enables a direct connection between the die and an external heat sink, which can significantly reduce RθJA.

RθJC(top) in a thermally enhanced package

RθJC(top) allows heat to escape more effectively from the top of the device. Typically, heat escapes through the package mold and then to the air, but in a thermally enhanced package, it escapes directly to the air. This helps reduce the device temperature and reduces the risk of thermal shutdown and long-term heat stress issues. The thermally enhanced package also has a lower RθJA, which makes it possible for a converter to handle more current and operate in hotter environments.

Figure 2 shows a series of IC junction temperature measurements taken across output current for both the LM61495T-Q1 in the thermally enhanced package and TI’s LM61495-Q1 buck converter in the standard QFN package under two common operating conditions.

VOUT = 5V

FSW = 400kHz

TA = 25°C

Figure 2 Output current vs. junction temperature for the LM61495-Q1 and LM61495T-Q1 with no heat sink. Source: Texas Instruments

Clearly, even with no heat sink attached, the thermally enhanced package runs slightly cooler, simply because more heat is dissipating out of the top of the package and into the air. The RθJA for a thermally enhanced package is slightly lower, demonstrating with certainty that, even if only marginally, this package type will provide better thermals compared to the standard QFN with top-side molding, even without any additional thermal management techniques. Table 1 lists the official thermal metrics found in both devices’ data sheets.

Part number	Package type	RθJA (evaluation module)(°C/W)	RθJC(top) (°C/W)	RθJB (°C/W)
LM61495-Q1	Standard QFN	21.6	19.2	12.2
LM61495T-Q1	Thermally enhanced package QFN	21	0.64	11.5

Table 1 Comparing data sheet-derived thermal metrics for the LM61495-Q1 and LM61495T-Q1. Source: Texas Instruments

Top-side cooling vs QFN

Combining its near-zero RθJC(Top) top side with an effective heat sink significantly reduces the RθJA of an IC in a thermally enhanced package. There are three significant improvements when compared to the same IC in a standard QFN package under otherwise similar operating conditions:

• Higher switching-frequency operation.
• Higher output-current capability.
• Operation at higher ambient temperatures.

For any SMPS under a given input voltage (VIN), output voltage (VOUT) condition and supplying a given output current, the maximum switching frequency will be thermally limited. Within every switching period, there are switching losses and conduction losses that dissipate as heat. Switching more frequently dissipates more power in the IC, leading to an increased IC junction temperature. This can be frustrating for engineers because switching at higher frequencies enables the use of a smaller buck inductor, and therefore a smaller overall solution size and lower cost.

Under the same operating conditions, using the thermally enhanced package and a heat sink, the heat dissipated in each switching period is now more easily channeled out of the IC, leading to a lower junction temperature and enabling a higher switching frequency without hitting the IC’s junction temperature limit. Just don’t exceed the maximum switching frequency recommendation of the device as outlined in the data sheet.

The benefits of using a smaller inductor are especially pronounced in higher-current multiphase designs that require an inductor for every phase. Figure 3 shows a simplified four-phase design capable of supplying 24 A at 3.3 VOUT at 2.2 MHz using the TI LM64AA2-Q1 step-down converter. If the design were to overheat and the switching frequency had to be reduced to 400 kHz, you would have to replace all four inductors with larger inductors (in terms of both inductance and size), inflating the overall solution cost and size substantially.

Figure 3 Simplified schematic of a single-output, four-phase step-down converter design using the LM644A2-Q1 step-down converter in the thermally enhanced package. Source: Texas Instruments

Conversely, for any SMPS under a given VIN, VOUT condition, and operating at a specific switching frequency, the maximum output current will be thermally limited. When discussing the current limit of an IC, it’s important to clarify that for all high-side FET integrated SMPSs, there is a data sheet-specified high-side current limit that bounds the possible output current.

Upon reaching the current-limit setpoint, the high-side FET turns off, and the IC may enter a hiccup interval to reduce the operating temperature until the overcurrent condition goes away. But even before reaching the current limit, it is very possible for an IC to overheat from a high output-current requirement. This is especially true, again, at higher frequencies. As long as you don’t exceed the high-side current limit, using an IC in the thermally enhanced package with a heat sink can extend the maximum possible output current to a level at which the standard QFN IC alone would overheat.

There is another constant to make the thermally enhanced package versus the standard QFN package comparison valid, and that is the ambient temperature (TA). TA is a significant factor when considering how much power an SMPS can deliver before it starts to overheat.

For example, a buck converter may be able to easily do a 12VIN-to-5VOUT conversion and support a continuous 6 A of current while switching at 2.2 MHz when the TA is 25°C, but not at 105°C. So, there is yet a third way to look at the benefit that a thermally enhanced package can provide. Assuming the VIN, VOUT, output current, and maximum switching frequency are constant, a thermally enhanced package used with a heat sink can enable an SMPS to operate at a meaningfully higher TA compared to a standard QFN package with no heat sink.

Figure 4 uses a current derating curve to demonstrate both the higher output current capability and operation at a higher TA. In an experiment using the LM61495-Q1 and LM61495T-Q1 buck converters, we measured the output current against the TA in a standard QFN package without a heat sink and in a thermally enhanced package QFN connected to an off-the-shelf 45 x 45 x 15 mm stand-alone fin-type heat sink. Other than the package and the heat sink, all other conditions are constant: operating conditions, PCB, and measurement instrumentation.

VIN = 12V

VOUT = 3.3V

FSW = 2.2MHz

Figure 4 Output current vs. ambient temperature of the LM61495-Q1 with no heat sink and the LM61495T-Q1 with an off-the-shelf 45 x 45 x 15 mm stand-alone fin-type heat sink. Source: Texas Instruments

When TA reaches about 83˚C, the standard QFN package hits its thermal shutdown threshold, and the output current begins to collapse. As TA increases further, the device cycles into and out of thermal shutdown, and the maximum achievable output current that the device can deliver is necessarily reduced until TA reaches a steady 125˚C. At this point, the converter may not be able to sustain even 5 A without overheating.

Compare this to the thermally enhanced package QFN connected to a heat sink. The first instance of thermal shutdown now doesn’t occur until about 117˚C. That’s an increase in TA before hitting a thermal shutdown of 34˚C, or 40%. The LM61495-Q1 is a 10-A buck converter, meaning that its recommended maximum output current is 10 A. But in this case, with a thermally enhanced package and effective heat sinking, a continuous 11 A output was clearly achievable up to 117˚C – in other words, a 10% increase in maximum continuous output current even at a high TA.

Methods of top-side cooling

Figure 5, Figure 6, and Figure 7 show some of the most common methods of top-side cooling. Stand-alone heat sinks are simple and readily available in many different forms, materials, and sizes, but are sometimes impractical in small-form-factor designs.

Figure 5 Stand-alone fin-type heat sink, these are simple and readily available but sometimes impractical in small form factor designs. Source: Texas Instruments

Cold plates are very effective in dissipating heat but are more complex and costlier to implement (Figure 6).

Figure 6 Cold plate-type heat sink, these are very effective in dissipating heat but are more complex and costlier to implement. Source: Texas Instruments

Using the metal housing containing the power supply and the surrounding electronics as a heat sink is compact, effective, and relatively inexpensive if the housing already exists. As shown in Figure 7, this is done by creating a pillar or dimple that connects the IC to the housing to enable efficient heat transfer. For power supplies powering processors, it’s likely that this method is already helping dissipate heat on the processor. Adding an additional dimple or pillar that now gives heat-sink access to the power supply is often a simple change, making it a very popular method, especially for processor power.

Figure 7 Contact-with-housing heat sink where a pillar or dimple connects the IC to the housing to enable efficient heat transfer. Source: Texas Instruments

There are many ways to implement heat sinking, but that doesn’t mean that they are all equally effective. The size, material, and form of the heat sink matter. The type and amount of thermal interface material used between the IC and the heat sink matter, as does its placement. It is important to optimize all of these factors for the design at hand.

Comparing heat sinks

Figure 8 shows another current derating curve. It compares two different types of heat sinks, each mounted on the LM61495T-Q1. For reference, the figure includes the performance of the standard QFN package with no heat sink.

VIN = 24V

VOUT = 3.3V

FSW = 2.2MHz

Figure 8 Output current versus the ambient temperature of the LM61495-Q1 with no heat sink, the LM61495T-Q1 with an off-the-shelf 45 x 45 x 15 mm stand-alone fin-type heat sink, and with an aluminum plate heat sink. Source: Texas Instruments

For a visualization of these heat sinks, see Figure 9 and Figure 10, which show a top-down view of the PCB and a clear view of how the heat sinks are mounted to the IC and PCB. The heat sink shown in Figure 9 is a commercially available, off-the-shelf product. To reiterate, it is a 45 mm by 45 mm aluminum alloy heat sink with a base that is 3mm thick and pin-type fins that extend the surface area and allow omnidirectional airflow.

Figure 9 The LM61495T-Q1 evaluation board with the off-the-shelf 45 x 45 x 15 mm stand-alone fin-type heat sink. Source: Texas Instruments

Figure 10 shows a custom heat sink that is essentially just a 50 mm by 50 mm aluminum plate with a 2 mm thickness and a small pillar that directly touches the IC. This heat sink was designed to mimic the contact-with-housing method, as it is very similar in size and material to the types of housing seen in real applications.

Figure 10 The LM61495T-Q1 evaluation board with a custom aluminum plate heat sink to mimic the contact-with-housing method. Source: Texas Instruments

Under the same conditions, the stand-alone heat sink provides a major benefit compared to the standard QFN package with no heat sink. The standard QFN package hits thermal shutdown around 67°C TA. For the stand-alone heat-sink setup, thermal shutdown isn’t triggered until the TA reaches about 111°C, which is a major improvement. However, the aluminum plate heat-sink setup doesn’t hit thermal shutdown at all. With the aluminum plate setup, the converter is still able to supply a continuous 10-A current at the highest TA tested (125˚C), demonstrating both the importance of choosing the correct heat sink for the system requirements as well as the popularity of the contact-with-housing method.

Addressing modern thermal challenges

Power supply designers increasingly deal with thermal challenges as modern applications demand more power and smaller form factors in hotter spaces. Standard QFN packaging has long relied on dissipating the majority of generated heat through the bottom side of the package to the PCB. A thermally enhanced package QFN uses both the top and bottom sides of the package to improve heat flow out of the IC, essentially paralleling the thermal impedance paths and reducing the effective thermal impedance.

Combining a thermally enhanced package with effective heat sinking results in significant thermal benefits and enables higher-power-density designs. Because these benefits are derived from reducing the effective RθJA, designers can realize just one or all of these benefits in varying degrees. Increase the maximum switching frequency and reduce solution size and cost. Enabling a higher maximum output current for higher power conversion. Enable operation at a higher TA.

Jonathan Riley is a Senior Product Marketing Engineer for Texas Instruments’ Switching Regulators organization. He holds a BS in Electrical Engineering from the University of California Santa Cruz. At TI, Jonathan works in the crossroads of marketing and engineering to ensure TI’s Switching Regulator product line continues to evolve ahead of the market and enable customers to power the technologies of tomorrow.

 Related Content

• Power Tips #101: Use a thermal camera to assess temperatures in automotive environments
• IC packages and thermal design
• Keeping space chips cool and reliable
• QFN? QFP? QFWHAT?

Additional resources

• Read the TI application note, “Semiconductor and IC Package Thermal Metrics.”
• Check out these TI application reports:
  • “AN-2020 Thermal Design by Insight, Not Hindsight.”
  • “AN-1520 A Guide to Board Layout for Best Thermal Resistance for Exposed Packages.”
• See the TI application brief, “PowerPAD Made Easy.”
• Watch the TI video resource, “Improve thermal performance using thermally enhanced packaging (TEP).”

The post Thermally enhanced packages—hot or not? appeared first on EDN.

Where do HDDs stand after the advent of SDDs? Are they a thing of the past now, or do they still have a life? While HDDs store digital data, what’s their relation to analog technology? Here is a fascinating look at HDD’s past, present, and future, accompanied by data from the industry. The author also raises a very valid point: while their trajectory is very similar to the world of semiconductors, why don’t HDDs have their own version of Moore’s Law?

Read the full article at EDN’s sister publication, Planet Analog.

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The post Past, present, and future of hard disk drives (HDDs) appeared first on EDN.

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