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There’s currently a significant buzz within the semiconductor industry around chiplets, bare silicon dies intended to be combined with others into a single packaged device. Companies are beginning to plan for chiplet-based designs, also known as multi-die systems. Yet, there is still uncertainty about what designing chiplet architecture entails, which technologies are ready for use, and what innovations are on the horizon.

Understanding the technology and supporting ecosystem is necessary before chiplets begin to see widespread adoption. As technology continues to emerge, chiplets are a promising solution for many applications, including high-performance computing, AI acceleration, mobile devices, and automotive systems.

Figure 1 Understanding the technology is necessary before chiplets begin to see widespread adoption. Source: Arteris

The rise of chiplets

Until recently, integrated circuits (ICs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), and system-on-chip (SoC) devices were monolithic. These devices are built on a single piece of silicon, which is then enclosed in its dedicated package. Depending on its usage, the term chip can refer to either the bare die itself or the final packaged component.

Designing monolithic devices is becoming increasingly cost-prohibitive and harder to scale. The solution is to break the design into several smaller chips, known as chiplets, which are mounted onto a shared base called a substrate. All of this is then enclosed within a single package. This final assembly is a multi-die system.

Building on this foundation, the following use cases illustrate how chiplet architectures are being implemented. Split I/O and logic is a chiplet use case in which the core digital logic is implemented on a leading-edge process node. Meanwhile, I/O functions such as transceivers and memory interfaces are offloaded to chiplets built on older, more cost-effective nodes. This approach, used by some high-end SoC and FPGA manufacturers, helps optimize performance and cost by leveraging the best technology for each function.

A reticle limit partitioning use case implements a design that exceeds the current reticle limit of approximately 850 mm2 and partitions it into multiple dies. For example, Nvidia’s Blackwell B200 graphics processing unit (GPU) utilizes a dual-chiplet design, where each die is approximately 800 mm² in size. A 10 terabytes-per-second link enables them to function as a single GPU.

Homogeneous multi-die architecture integrates multiple identical or functionally similar dies, such as CPUs, GPUs, or NPUs, on a single package or via an ‘interposer’, a connecting layer similar to a PCB but of much higher density and typically made of silicon using lithographic techniques. Each die performs the same or similar tasks and is often fabricated using the same process technology.

This approach enables designers to scale performance and throughput beyond monolithic die designs’ physical and economic limits, mainly as reticle limits of approximately 850 mm² constrain single-die sizes or decreasing yield with increasing die size makes the solution cost-prohibitive.

Functional disaggregation is the approach most people think of when they hear the word chiplets. This architecture disaggregates a design into multiple heterogeneous dies, where each die is realized at the best node in terms of cost, power, and performance for its specific function.

For example, a radio frequency (RF) die might be implemented using a 28 nm process, analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) could be realized in a 16 nm process, and the core digital logic might be fabricated using a 3 nm process. Large SRAMs may be implemented in 7 nm or 5 nm, as RAM has not scaled significantly in finer geometries.

The good news

There are multiple reasons why companies are planning to transition or have transitioned to chiplet-based architectures. These include the following:

• Chiplets can build larger designs than are possible on a single die.
• Higher yields from smaller dies reduce overall manufacturing costs.
• Chiplets can mix and match best-in-class processing elements, such as CPUs, GPUs, NPUs, and other hardware accelerators, along with in-package memories and external interface and memory controllers.
• Multi-die systems may feature arrays of homogeneous processing elements to provide scalability, or collections of heterogeneous elements to implement each function using the most advantageous process.
• Modular chiplet-based architectures facilitate platform-based design coupled with design reuse.

Figure 2 There are multiple drivers pushing semiconductor companies toward chiplet architectures. Source: Arteris

The ecosystem still needs to evolve

While the benefits are clear, several challenges must be addressed before chiplet-based architectures can achieve widespread adoption. While standards like PCIe are established, die-to-die (D2D) communication standards like UCIe and CXL continue to emerge, and ecosystem adoption remains uneven. Meanwhile, integrating different chiplets under a common set of standards is still a developing process, complicating efforts to build interoperable systems.

Effective D2D communication must also deliver low latency and high bandwidth across varied physical interfaces. Register maps and address spaces, once confined to a single die, now need to extend across all chiplets forming the design. Coherency protocols such as AMBA CHI must also span multiple dies, making system-level integration and verification a significant hurdle.

To understand the long-term vision for chiplet-based systems, it helps first to consider how today’s board-level designs are typically implemented. This usually involves the design team selecting off-the-shelf components from distributors like Avnet, Arrow, DigiKey, Mouser, and others. These components all support well-defined industry-standard interfaces, including I2C, SPI, and MIPI, allowing them to be easily connected and integrated.

In today’s SoC design approach, a monolithic IC is typically developed by licensing soft intellectual property (IP) functional blocks from multiple trusted third-party vendors. The team will also create one or more proprietary IPs to distinguish and differentiate their device from competitive offerings. All these soft IPs are subsequently integrated, verified, and implemented onto the semiconductor die.

The long-term goal for chiplet-based designs is an entire chiplet ecosystem. In this case, the design team would select a collection of off-the-shelf chiplets created by trusted third-party vendors and acquired via chiplet distributors rather as board-level designers do today. The chiplets will have been pre-verified with ‘golden’ verification IP that’s trusted industry-wide, enabling seamless integration of pre-designed chiplets without the requirement for them to be verified together prior to tape-out.

The team may also develop one or more proprietary chiplets of their own, utilizing the same verification IP. Unfortunately, this chiplet-based ecosystem and industry-standard specification levels are not expected to become reality for several years. Even with standards such as UCIe, there are many options and variants within the specification, meaning there is no guarantee of interoperability between two different UCIe implementations, even before considering higher-level protocols.

The current state-of-play

Although the chiplet ecosystem is evolving, some companies are already creating multi-die systems. In some cases, this involves large enterprises such as AMD, Intel, and Nvidia, who control all aspects of the development process. Smaller companies may collaborate with two or three others to form their own mini ecosystem. These companies typically leverage the current state-of-play of D2D interconnect standards like UCIe but often implement their own protocols on top and verify all chiplets together prior to tape-out.

Many electronic design automation (EDA) and IP vendors are collaborating to develop standards, tool flows, and crucially VIP. These include companies like Arteris, Cadence, Synopsys, and Arm, as well as RISC-V leaders such as SiFive and Tenstorrent.

Everyone is jumping on the chiplet bandwagon these days. Many are making extravagant claims about the wonders to come, but most are over-promising and under-delivering. While a truly functional chiplet-based ecosystem may still be five to 10 years away, both large and small companies are already creating chiplet-based designs.

Ashley Stevens, director of product management and marketing at Arteris, is responsible for coherent NoCs and die-to-die interconnects. He has over 35 years of industry experience and previously held roles at Arm, SiFive, and Acorn Computers.

Related Content

• A closer look at Arm’s chiplet game plan
• TSMC, Arm Show 3DIC Made of Chiplets
• Chiplets Get a Formal Standard with UCIe 1.0
• How the Worlds of Chiplets and Packaging Intertwine
• Imec’s Van den hove: Moving to Chiplets to Extend Moore’s Law

The post Chiplet basics: Separating hype from reality appeared first on EDN.

Author: STMicroelectronics

From cloud-first to edge-ready: why AI needs to evolve

Artificial Intelligence (AI) has come a long way in the last decade. While cloud-based infrastructure enabled massive leaps in AI capabilities, it also introduced new challenges, such as latency, energy consumption, and privacy concerns. In response, companies and researchers started focusing on edge AI, where data is processed locally on embedded systems such as sensors and microcontrollers. The Edge AI Foundation (formerly known as TinyML) has been a driver in this transition since its creation in 2018 by bringing together industry leaders and innovators to make AI smarter, faster, and more pervasive at scale.

The evolution of AI development

Artificial Intelligence started to attract mainstream attention around 2012, when deep learning models achieved remarkable success in areas like image recognition, speech processing, and translation. The emergence of cloud computing drove these advancements, offering the computational resources required to train complex models on large datasets.

Over the next several years, companies invested heavily in cloud-based AI infrastructure, using high-performance GPUs to develop ever-larger models, including the early versions of generative AI. By 2017, AI was firmly embedded in cloud services offered by major tech providers.

However, as adoption grew, so did concerns about latency, bandwidth, privacy, and the high energy costs of transmitting and processing data remotely. These limitations became more pronounced as AI moved into latency-critical applications like autonomous systems, wearable tech, and industrial automation. The result was a gradual understanding that not all AI needs to live in the cloud and that many use cases could benefit from performing AI computations locally, closer to the data source. This awareness laid the foundation for the next significant shift: AI at the edge.

Why edge AI is the next big step

As AI becomes more integrated into everyday life, the need for fast, private, and energy-efficient processing is growing. Traditional cloud-based AI requires data to be sent to remote servers for analysis and decision-making, introducing latency, increasing energy use, and raising privacy concerns. Edge AI solves these challenges by enabling intelligent processing directly on local devices, such as sensors, microcontrollers, and other embedded processing solutions.  This eliminates or reduces the need to constantly connect to the cloud.

Thanks to key advancements like the STM32 microcontroller family and ST’s intelligent MEMS sensors portfolio, from inertial measurements units to biosensors, edge AI is no longer experimental; it’s a pervasive solution. Edge AI technologies empower devices to execute neural network inference locally, facilitating tasks such as anomaly detection, pose estimation, gesture recognition, environmental monitoring, and more. These functions are crucial in fields like industrial automation, healthcare, and innovative consumer products, where low latency, robust security, and minimal energy use are essential.

Among these innovations it is worth mentioning the STM32N6 series, ST’s first microcontroller family to integrate the Neural-ART Accelerator, a proprietary Neural Processing Unit (NPU). This NPU accelerates AI inference workloads directly on the MCU, drastically reducing latency, power consumption and off-loading the CPU for AI computing. Designed for demanding edge applications, the STM32N6 combines advanced performance, a unique video acquisition pipeline, and unprecedented energy efficiency with the flexibility of the STM32 programming ecosystem.

The Edge AI Foundation: a community driving change

The Edge AI Foundation is a strategic think tank committed to advancing edge AI across sectors. It hosts global conferences, such as annual events in Europe, the U.S., and Asia, connecting academia and industry. As a non-profit, the Foundation doesn’t promote specific products; instead, it fosters knowledge exchange, networking, joint research, and alignment on frameworks and tools.

Knowledge exchange at TinyML EMEA 2024

The journey of the Edge AI Foundation began in 2018 with the establishment of the TinyML Foundation, a collaborative community initiated by industry leaders such as Google, ARM, and STMicroelectronics.

The Foundation’s goal was to create a community of experts who could prove that machine learning could be executed even on ultralow-power devices (under 1mW), unlocking a new class of applications that operate independently of cloud infrastructure. This first step addressed the growing demand for real-time, energy-efficient, and privacy-preserving AI applications in areas like wearables, smart homes, and industrial IoT. And it was relatively quick to achieve.

As the field matured, the scope of applications expanded beyond simple models to encompass more complex tasks, such as generative and agentic AI, computer vision, and natural language processing, all executed at the edge. Following this evolution, in 2024 the TinyML Foundation rebranded itself as the Edge AI Foundation, reconfirming its commitment to advancing AI technologies that operate at the network’s edge.

Participants at TinyML EMEA 2024

Today, the Edge AI Foundation brings together a diverse community of researchers, developers, business leaders, and policymakers to address the challenges and opportunities in deploying AI at the edge. The foundation aims to make edge AI technology accessible and impactful for all. To achieve this mission, the Foundation has launched several initiatives:

• Edge AI Working Groups: focus groups on Generative AI, Blueprints, Dataset and Benchmarking, Neuromorphic and Marketing.
• Edge AI Labs: a platform providing access to high-quality datasets, models, and code to accelerate edge AI research and development.
• Edge AIP (Academia & Industry Partnership): a program promoting collaboration between industry partners and academic institutions to develop educational materials, certification programs, and scholarship opportunities.

STMicroelectronics as Strategic Leader Sponsor of the Edge AI Foundation Alessandro Cremonesi (ST Chief Innovation Officer & Executive Vice President General Manager System Research and Applications) at TinyML EMEA 2024

STMicroelectronics began collaborating with the Edge AI Foundation in 2018. This relationship started after ST demonstrated its STM32Cube.AI pre-production tool version at the CES event in Las Vegas. This seminal project led to an invitation by Pete Warden (past TensorFlow Lite tech lead at Google) to the first TinyML US Forum in early 2019. ST showcased live AI demonstrations of its standard STM32 microcontrollers on that occasion.

ST demo owners (Yanis Hamiti, Nicolas Gaude and He Huang) at TinyML EMEA 2024

Nowadays, as a Strategic Leader Sponsor, ST participates in and lead working groups, contributes to event programming, and engages in the Foundation’s governance.

For example, Danilo Pau (Technical Director, IEEE, AAIA and ST Fellow in System Research) chairs the Foundation’s Gen EDGE AI working group, organizing forums, producing white papers and initiating research projects leveraging existing ST AI products. Additionally, Giuseppe Desoli (ST’s Company Fellow, SRA Chief architect, Senior Director of Artificial Intelligence & Embedded Architectures) was appointed a Board member in 2025.

This participation supports the promotion of ST’s edge AI solutions, including its portfolio of AI-enabled microcontrollers, such as STM32 general-purpose MCUs and Stellar automotive MCUs, along with sensors and the comprehensive software tools ecosystem that make up the ST Edge AI Suite, while also building a network of authorized partners.

From smart devices to autonomous agents

Edge AI is expected to power the next generation of intelligent agents and systems capable of reasoning, planning, adapting and acting. We are already starting to see early use cases: AI-powered thermostats that learn user behavior, voice assistants that operate offline, intelligent voice transcriptors and humanoid robots that help with manufacturing tasks. In the future, these autonomous systems could help manage entire smart buildings, improve energy efficiency, or support industrial automation, all without needing a constant connection to the cloud.

To support this shift, edge AI platforms need to be highly efficient in both energy and performance. ST is enabling customers to implement edge AI daily thanks to innovations that facilitate edge AI on a broad range of STM32 microcontroller family, Microcontrollers integrating an NPU, and intelligent MEMS sensors with two technologies: the intelligent Sensor Processing Unit (ISPU) and machine learning core (MLC).

As an active contributor to the Edge AI Foundation, ST will continue to influence this community, enabling faster innovation and more sustainable technology at the edge.

The post Edge AI Foundation: powering the next wave of intelligence at the edge appeared first on ELE Times.

While there are lots of nice solutions out there for accessible circuit building (Tronic boards, Little Bits, Snap Circuits, etc) most of these are kind of closed ecosystems, with components permanently mounted in modules. What I needed was a way for her to be able to use bog standard components, but not have to deal with fiddly connections. I'll add some more pictures of the individual boards in the comments. Feedback and suggestions are very welcome. submitted by /u/hey_hey_you_you [link] [comments]

This is just a prototype. in future it will be better for example we can get rid of square thing, polish metal so it looks like actual metal. and reduce the height. final one I also want to use a stm32u5 I spent a lot of months doing this submitted by /u/coolkid4232 [link] [comments]

submitted by /u/AutoModerator
[link] [comments]

Theres well over 6k resistors in this drawer, think that it's enough? submitted by /u/Whyjustwhydothat [link] [comments]

What is a TDC?

A time-to-digital converter (TDC) is like a stopwatch measuring the elapsed interval between two events with picosecond precision, converting this into a digital value for post-processing. Many space applications require time-of-flight measurements to calculate distance, delay, or velocity. For example, an in-space servicing, assembly, and manufacturing (ISAM) spacecraft needs to determine precisely the relative location of debris before initiating rendezvous and retrieval operations. Similarly, space-domain awareness must understand the proximity and trajectory of other orbiting objects to assess any potential threat.

A TDC receives two inputs: a start signal (or edge) to mark the beginning of the time interval to be measured, and a stop pulse. The delay between these is converted to a digital number for post-processing. Different architectures are typically used to implement the logic, e.g., counters, delay lines, or a time amplifier.

Time-to-digital conversion is a technique used in space-based LiDAR systems to measure the time taken for a light pulse to travel to and from an object to calculate its distance. A LiDAR emits a laser pulse towards a target, which reflects off the latter’s surface, returning to the sensor. The TDC starts counting when the pulse is transmitted, stops when it is detected by the receiver, and using the speed of light, the distance is calculated as:

where c is the speed of light and t is the time-of-flight.

TDC in LiDAR

For example, LiDAR is used by some Earth-Observation operators to measure altitude and surface changes over time, to, for example, monitor vegetation height, ice sheet or glacier thickness and melt, sea-ice elevation or relative sea level. Spaceborne LiDAR altimetry is capable of centimetre-level vertical precision and is illustrated in Figure 1.

Figure 1 The use of TDC in space-based LiDAR applications. Source: Rajan Bedi

Similarly, a TDC is used in mass spectroscopy to measure how long it takes ions to travel from a source to a detector. This time-of-flight information is used to calculate the mass-to-charge ratio (m/z) of ions, and since the kinetic energy given to all ions is the same, time-of-flight is directly related to their mass as follows:

where t is the time of flight, k a calibration constant, m the ion mass and z the ion charge.

TDC in mass spectroscopy

Space-based mass spectroscopy has many applications to identify and quantify chemical composition by measuring the mass-to-charge ratio of ions. For example, Earth Observation and space weather monitor the make-up of the Earth’s ionosphere and magnetosphere, including solar wind particles. Space science analyses the chemical structure of planetary atmospheres, lunar and asteroid surface composition, as well as soil or ice samples to detect organic molecules and potential signs of life. Time-of-flight mass spectroscopy is illustrated in Figure 2.

Figure 2 The use of TDC in time-of-flight mass spectroscopy. Source: Rajan Bedi

TDC in optical communications

Optical communication is increasingly being used to transmit data wirelessly between orbiting satellites, such as intersatellite links, or links from the ground to a spacecraft. High-throughput payloads are now using fibre to send data within sub-systems to overcome the bandwidth, loss, mass ,and EMI limitations of traditional copper communications.

TDCs are used to detect when photons arrive, for timing-jitter analysis to prevent degradation of system performance, clock recovery, and synchronization for aligning and decoding incoming data streams, as shown in Figure 3.

Figure 3 The use of TDC and fibre-based optical communications within a payload. Source: Rajan Bedi

TDC to calculate absolute time

TDC is also used to calculate absolute time with the help of satellite navigation for applications such as quantum key distribution over long distances. Both the transmitter and the receiver use GNSS-disciplined oscillators to synchronize their local system clocks to a global time reference such as UTC or GPS time. A precise timestamp (Tevent) can be calculated as:

where TGNSSepoch is the absolute time of the last GNSS PPS signal, e.g., 14:23:08 UTC, N is the number of clock cycles since the PPS, Tclk is the clock period, and tfine is the sub-nanosecond fine time from interpolation.

For example, if the TDC counts 8,700 clock cycles with a period of 1 ns and tfine = 0.217 ns, the resulting timestamp can be calculated as:

The system concept based on optical communications is illustrated in Figure 4.

Figure 4 The use of TDC to calculate absolute time for quantum key distribution. Source: Rajan Bedi

MAG-TDC00002-Sx TDC

Magics Technologies NV has just released a rad-hard TDC for space applications: the MAG-TDC00002-Sx is shown in Figure 5 and can measure time delays with picosecond precision, converting this to a digital value for post processing. The device offers an SPI slave interface to connect to FPGAs/MCUs for configuration and read-out of the elapsed time. 

Figure 5 Magics’ TDC00002-Sx, Rad-Hard TDC that can measure time delays with picosecond precision. Source: Magics Technologies NV

The MAG-TDC00002-Sx operates from a core voltage of 1.2 V, and its I/O can be powered from 1V8 to 3V3. The device consumes 20 mW (typical) and has a specified operating temperature from -40°C to 125°C. The MAG-TDC00002-Sx comes in a 17.9 x 10.8 mm, 28-pin, hermetic, ceramic COIC package.

The architecture of the MAG-TDC00002-Sx and an application drawing are shown in Figure 6: following power-up and initialization (lock) of the internal PLL, the TDC enters an IDLE state. When the device is configured, a pulse is generated on the TRIGGER output, and the TDC changes to a LISTEN mode. In this state, the internal 1.25-GHz counter is running and will be sampled on receipt of external start and stop signals. The values are saved to their corresponding registers, and both coarse and fine measurements can be read out via SPI to calculate time-of-flight.

The MAG-TDC00002-Sx has automatic, internal self-calibration, which corrects for drifts due to process, voltage, temperature, and radiation degradation.

Figure 6 The architecture and application drawing of MAG-TDC00002-Sx. Source: Magics Technologies NV

As an example, a time-of-flight measurement between a single start and stop event resulted in the following MAG-TDC00002-Sx register data:

START BIN DEL = 121 STOP BIN DEL0 = 28 START BIN CAL PERIOD = 110 STOP BIN CAL PERIOD0 = 110 START BIN CAL OFFSET = 8 STOP BIN CAL OFFSET = 9 START CNT VAL L = 4 START CNT VAL H = 0 STOP CNT VAL L0 = 14 STOP CNT VAL H0 = 0

The calculation of time-of-flight is:

In terms of radiation hardness, the MAG-TDC00002-Sx has a specified SET/SEU tolerance of 60 MeV·cm2/mg and a total-dose immunity > 100 kRad (Si) / 1 kGy (Si). Radiation reports and ESCC9000 qualification are expected in Q3 of this year, and EM and EQM parts can be ordered today. The device is European and ITAR-free, which is advantageous if you have import/export concerns!

MAG-TDC00002-Sx evaluation kit

To prototype and de-risk the MAG-TDC00002-Sx, an evaluation kit is available comprising a base board and a TDC PCB as shown below. The latter fits on top of the former using the socket headers, and the base board connects to a PC using a USB Type-C cable as shown in Figure 7.

Figure 7 MAG-TDC00002-Sx evaluation kit with a base board and TDC PCB. Source: Magics Technologies NV

The evaluation kit comes with software that communicates with the base board using SCPI commands to configure and use the MAG-TDC00002-Sx as shown in Figure 8.

Figure 8 A screenshot of MAG-TDC00002-Sx evaluation kit software using SCPI commands to configure the device. Source: Magics Technologies NV

The rad-hard TDC is well-suited for manufacturers of Earth-Observation LiDAR instruments, space-science mass spectrometers, ISAM/space-domain awareness proximity detectors or high-throughput optical communications transceivers for calculating time-of-flight. The MAG-TDC00002-Sx can also be used to calculate absolute time for applications such as secure quantum key exchange via satellite.

Further information about Magics’ MAG-TDC00002-Sx will be shared in a webinar to be broadcast on 22nd May, and you can register using this link.

Dr. Rajan Bedi is the CEO and founder of Spacechips, which designs and builds a range of advanced, AI-enabled, re-configurable, L to K-band, ultra high-throughput transponders, SDRs, Edge-based on-board processors and Mass-Memory Units for telecommunication, Earth-Observation, ISAM, SIGINT, navigation, 5G, internet and M2M/IoT satellites. The company also offers Space-Electronics Design-Consultancy, Avionics Testing, Technical-Marketing, Business-Intelligence and Training Services. (www.spacechips.co.uk).

Related Content

• Clock architectures and their impact on system performance and reliability
• Oscilloscope special acquisition modes
• Resolve picoseconds using FPGA techniques
• Oscilloscope probing your satellite

The post Time-to-digital conversion for space applications appeared first on EDN.

Rohde & Schwarz presents the new R&S UDS digital multimeter series. The compact instruments can display three measurements simultaneously and offer versatile measurement functions and various interfaces for remote control. Models are available with a digit resolution of 5 ½ as well as 6 ½, the latter providing a basic DC accuracy of 0.0075 percent. The R&S UDS series replaces the established R&S HMC8012 digital multimeter, offering more accuracy and an updated intuitive user interface for smooth and efficient testing.

The new R&S UDS digital multimeters from Rohde & Schwarz offer a versatile range of testing capabilities, making them ideal for troubleshooting, component testing, and system validation applications, as well as for teaching labs in education. Additionally, they are well-suited for production environments, where reliability and accuracy are paramount. With voltage ranges extending up to 1000 V DC and 750 V AC and a current capacity of 10 A, these multimeters provide a comprehensive solution for a wide range of measurement tasks. They come with an easy-to-use interface and a 3.5” OVGA color display for excellent readability. The large screen can simultaneously display up to three measurement values, streamlining test workflows and enhancing productivity.

Advanced Measurement Capabilities

In addition to twelve standard measurement functions, the multimeters feature built-in statistical and mathematical functions, making them suitable for a wide range of applications, including two-wire and four-wire measurements, as well as limit testing.

For remote control, the new multimeters offer a variety of interfaces, including USB, IEEE-488 (GPIB) for SCPI-based commands, and LAN (Ethernet). This enables seamless integration of the R&S UDS digital multimeter into any test setup or production line, providing unparalleled flexibility and convenience.

As the well-established R&S HMC8012 digital multimeter is being phased out, the new R&S UDS series will take its place.

The post Built for accuracy, designed for ease: Introducing the new R&S UDS digital multimeter series appeared first on ELE Times.

Quectel Wireless Solutions, a global IoT solutions provider, has launched the Quectel KCM0A5S, a high-performance Wi-SUN module designed for smart applications such as street lighting, precision agriculture, industrial IoT, smart meters and smart cities. Based on Silicon Labs EFR32FG25, a sub-GHz low power wireless System on Chip, and featuring an ARM Cortex-M33 processor with a frequency of up to 97.5MHz, the module includes built-in 256KB RAM and 2MB Flash memory, ensuring efficient performance.

The Quectel KCM0A5S supports the Wi-SUN Field Area Network (FAN) 1.1 protocol and operates across the 470–928 MHz frequency range. The module utilizes IPv6-based wireless mesh networking technology, intrinsic to the Wi-SUN communication standard, to deliver long-range transmission, stable network connectivity and reliable data transmission. Furthermore, the KCM0A5S offers flexible deployment capabilities, supporting both router and leaf node configurations in standalone SoC mode, as well as acting as a border router when paired with a Linux host in RCP (Radio Co-Processor) mode. This versatility makes it an ideal solution for a wide range of mesh networking applications in smart city, utility, and industrial IoT deployments. In addition, the KCM0A5S features strong anti-interference capabilities and delivers excellent signal penetration which is of specific value for use cases in hard-to-reach locations. With a minimum of ten years product lifecycle and cross-version compatibility, the solution ensures long-term interoperability within Wi-SUN FAN networks.

We’re delighted to launch the Quectel KCM0A5S Wi-SUN module,” said Delbert Sun, Vice General Manager, Product Department, Quectel Wireless Solutions. “Wi-SUN is a versatile LPWA connectivity technology that is applicable globally to a wide range of use cases. Its security, scalability and robustness provide compelling advantages to developers and device designers and the KCM0A5S adds to this with its ultra-compact form factor, high speed bandwidth and low latency. We look forward to helping customers to build a smarter world with the KCM0A5S as they bring the latest Wi-SUN enabled devices to market.

Flexibility for developers and designers is assured thanks to the KCM0A5S’s ultra-compact LCC form factor. Dimensions of 28.0mm x 22.0mm x 3.15mm enable the size and cost of end products to be optimized, allowing for maximized design options. The module is also ideal for industrial-grade use cases with an operating temperature range of -40 °C to +85 °C. The module is available in variants that support a peak transmit power of 30 dBm—currently permitted in select regions such as North America, Latin Ameria and some APAC countries —and offers both OFDM and FSK modulation schemes, subject to regional regulatory allowances.

Wi-SUN has been gaining traction for connecting IoT devices as a low power wide area (LPWA) connectivity solution because of its blend of scalability, security, interoperability and performance. It offers high speed bandwidth at up to 2.4Mbp with OFDM modulation. The technology is easily expandable and can support thousands of nodes. WI-SUN’s self-forming and self-healing mesh eliminates single point of failure networks and simplifies deployment.

The combination of wide coverage, long distance of several kilometers and the ability to serve urban scenarios, covered by multi-hop mode is seeing Wi-SUN adopted for smart metering and smart city applications. For example, a control management system for street lighting, utilities and parking has been deployed in London that utilizes 15,000 Wi-SUN devices and 12 Wi-SUN border routers to enable real-time remote management and provide a future-proof system that can scale up as the city transitions to new infrastructure.

The post Quectel introduces KCM0A5S Wi-SUN module for smart city and smart utility devices appeared first on ELE Times.

Університет 2030: освіта майбутнього kpi пт, 06/13/2025 - 12:13

Rohde & Schwarz is set to revolutionize the field of signal and spectrum analysis with the launch of the FSWX signal and spectrum analyzer, an innovative instrument designed to overcome the limitations of current measurement methods.

Rohde & Schwarz introduced the brand-new FSWX signal and spectrum analyzer, the first multichannel signal and spectrum analyzer with multiple input ports, unlocking new possibilities in signal analysis. It is also the first instrument of its kind with a cutting-edge internal multi-path architecture enabling a novel cross-correlation feature. Combined with its low phase noise for high signal purity, its spurious-free dynamic range and its outstanding residual EVM, the FSWX delivers an RF performance like no other signal and spectrum analyzer in the market.

The instrument’s wide internal bandwidth of 8 GHz allows for comprehensive analysis even of complex waveforms and modulation schemes. Combined with a high measurement speed and analysis tools tailored to the user’s needs, the FSWX brings new levels of performance and precision to signal analysis for modern RF applications – from active RF components testing to state-of-the-art automotive radar testing to complex airborne radar scenarios and satellite test in A&D applications to the latest test challenges in WLAN and cellular technologies like 5G and beyond.

Michael Fischlein, Vice President Spectrum & Network Analyzers, EMC & Antenna Test at Rohde & Schwarz, is thrilled to introduce the new FSWX: “Our team has truly re-imagined signal and spectrum analysis technology with our new FSWX. They have come up with an innovative architecture and design to empower our customers to tackle complex measurement scenarios in the evolving landscape of wireless communications and radar technology that were previously unattainable. In other words, the FSWX makes measuring the impossible, possible.” The instrument’s innovative design features include multiple input ports, cross-correlation capabilities, advanced filter banks and broadband ADCs.

Multiple input ports

The multichannel FSWX offers the ability to measure multiple signal sources simultaneously, regardless of whether they operate at the same or different frequencies. With synchronous input ports, each featuring 4 GHz analysis bandwidth, users can seamlessly analyze the interactions between diverse signals. This opens up a multitude of new measurement scenarios, for instance, phase-coherent measurements of antenna arrays used in beamforming for wireless communications as well as in airborne and automotive radar sensors.

Multi-path architecture and cross-correlation

Its advanced internal multi-path architecture allows for the cross-correlation mode, a novel feature of the FSWX. A single signal input is internally split into two independent signal paths, each equipped with its own local oscillator and ADC. With this innovative design, advanced cross-correlation algorithms can be applied in the digital backend, effectively removing the inherent noise of the measurement instrument. This feature reveals spurs not easily seen without cross-correlation. It is especially helpful when, for instance, measuring Error Vector Magnitude (EVM), a critical factor in mobile communications. The added wideband noise of traditional signal and spectrum analyzers limits the accuracy and dynamic of EVM measurements. With the cross-correlation feature, however, the FSWX provides an unobstructed view of the DUT for precise EVM analysis.

The internal multi-path architecture also offers advanced triggering options. For example, users can apply an IF or RF power trigger at distinct frequencies, as the multi-path design allows for independent frequency settings for each receive path behind the splitter. This way, the FSWX can easily reveal effects between two RF signals.

Advanced filter banks and broadband ADCs

Traditionally, for preselection in the microwave range, spectrum analyzers rely on YIG filters. Since they are known for their challenging frequency response, YIG filters need to be bypassed for wideband signal analysis. The FSWX, however, employs broadband ADCs in conjunction with filter banks that span the entire operating frequency range, allowing for pre-selected signal analysis while eliminating the need for YIG filters. The filter banks provide high precision, optimizing instrument settings for specific applications and significantly reducing the risk of unwanted signal images contaminating results. For users requiring narrowband applications, a YIG filter can still be added optionally.

Innovative firmware applications

The FSWX also provides innovative firmware applications such as the CrossACT (Cross Application Control and Triggering) firmware feature. It synchronizes various measurements across different input channels, allowing for simultaneous analysis with multiple tools. This capability simplifies comparisons, such as determining whether the higher harmonics of a radar signal directly impact the EVM performance of a 5G signal.

The Linux-based operating system of the FSWX provides a high level of security and long-term support, essential features for users in security-sensitive environments. This robust operating system ensures reliability and stability, making the FSWX an ideal choice for demanding applications.

The post New FSWX signal and spectrum analyzer with novel architecture overcomes limits of today’s analysis methods appeared first on ELE Times.

Author: Mr. Saleem Ahmed, Officiating Head, ESSCI

In the next ten years, India will witness a tectonic shift in its technological landscape, one that will decisively shape the nation’s economic destiny and global standing. At the heart of this transformation lies the semiconductor industry, often referred to as the “new oil” in the global economy. For Indian engineers, the semiconductor revolution isn’t just a story of factories and chips—it’s a gateway to high-value, future-ready careers that promise innovation, growth, and national impact.

With multiple large-scale semiconductor fabrication and assembly projects underway, and policy support at an all-time high, semiconductor jobs are rapidly becoming the next big thing for engineering talent in India. And at the forefront of this workforce transformation stands the Electronics Sector Skills Council of India (ESSCI)—tasked with equipping the Indian workforce for this high-tech future.

A Nation on the Verge of a Chip Revolution

India’s dependence on imported chips—used in everything from mobile phones to fighter jets—has long been a strategic vulnerability. But that reality is now changing. Recently Union Cabinet’s approved  approved a new semiconductor plant in Uttar Pradesh’s Jewar to be jointly set up by HCL Group and Foxconn. The newly approved facility will come up at an investment of Rs 3,700 crore.

This is the sixth unit approved under the India Semiconductor Mission, with five semiconductor facilities in advanced stages of construction. Three of these units—by Micron Technologies, Kaynes Technologies and a combination of CG Power-Renesas Electronics and Star Microelectronics—are based in Sanand, Gujarat. The Tata Group is building one semiconductor facility in Dholera, Gujarat and another in Assam.

These developments are backed by the Government of India’s India Semiconductor Mission (ISM), a ₹76,000 crore policy initiative that provides incentives for design, manufacturing, and packaging of semiconductor chips.

This growing ecosystem will need a massive talent pool—and that’s where India’s engineers come in.

Why Semiconductors Are a Game-Changer for Engineers

Semiconductors power almost every modern device—from smartphones and laptops to electric vehicles, smart appliances, 5G infrastructure, defense systems, and even satellites. As the world shifts toward AI, IoT, and smart mobility, the demand for chips is set to explode. According to recent estimates, India’s semiconductor market will triple in size—from US$22.7 billion in 2019 to over US$80 billion by 2028.

This explosion is not just about demand—it’s about job creation.

According to ESSCI’s analysis, the semiconductor industry is set to witness a dramatic rise in employment demand. The sector, which is projected to employ 1.70 lakh individuals by 2025, is expected to rise to 1.87 lakh in 2026, and add a total of 1.03 lakh new jobs by 2030. This includes roles in chip design, fabrication, testing, quality control, equipment maintenance, and advanced manufacturing processes.

The rapid expansion of this sector has created an urgent need for a highly skilled workforce. ESSCI is committed to bridging the skill gap through targeted training programs, collaborating with industry and academia to equip young professionals with expertise in chip design, fabrication, and advanced packaging. These initiatives will empower the next generation to drive India’s semiconductor revolution.

Such roles are not only high-paying but also globally portable, offering Indian engineers access to both domestic and international job markets.

The Many Doors Semiconductor Jobs Open

The semiconductor industry is uniquely interdisciplinary, requiring expertise in electronics, mechanical, chemical, computer science, materials engineering, and more. Here’s a breakdown of the top career tracks Indian engineers can pursue:

1. Design Engineers

Design engineers work on creating the architecture and layout of chips. They use Electronic Design Automation (EDA) tools to ensure chips are efficient, reliable, and ready for fabrication.

2. Process Engineers

These engineers fine-tune the manufacturing process, often working in cleanroom environments. They handle wafer processing, lithography, etching, doping, and deposition.

3. Packaging and Testing Experts

Once chips are fabricated, they need to be tested, assembled, and packaged. Engineers in this field ensure performance and durability under various operating conditions.

4. R&D Scientists

Research roles offer cutting-edge work in developing new semiconductor materials like gallium nitride or silicon carbide, and technologies like FinFET or EUV lithography.

5. Equipment and Maintenance Technicians

Fabrication units run on precision equipment that needs constant monitoring and maintenance—critical work for mechanical and electronics engineers.

6. Quality and Safety Officers

Given the strict standards in chip manufacturing, QA engineers ensure compliance, while safety experts handle protocols in chemical and electrical hazards.

Enter ESSCI: Building the Backbone of India’s Semiconductor Workforce

With this exponential growth comes the challenge of creating a skilled and job-ready workforce. The Electronics Sector Skills Council of India (ESSCI), under the aegis of the Ministry of Skill Development and Entrepreneurship, plays a crucial role in bridging this gap.

ESSCI has already developed 25 NSQF-aligned qualifications for semiconductor design, packaging, and manufacturing. These qualifications are designed to cater to:

• Engineering graduates seeking specialization
• Diploma and ITI students entering the job market
• Working professionals seeking upskilling or domain switch

ESSCI offers focused a range of qualifications covering the complete value chain of the semiconductor industry. Short Term courses such as VLSI Design Engineer, concentrating on designing SOC-module functions using software, Embedded Full Stack Engineer, IoT Hardware Analyst are some of the top courses offered for pursuing engineering graduates to gain the knowledge of EDA Tools and system design. ESSCI also provides qualifications for Wafer Back Grinding Engineer and Wafer Dicing Engineer, specialising in wafer manufacturing tasks which can be taught to ITI / Diploma students. ESSCI also has foundation / upskilling courses in the field of Nano Science & Advance Nano Science which is also in great demand. Also, there are some basic courses on the Industrial Safety – Electrical & Hazchem which are very crucial & important for the industrial safety requirements.

Career Opportunities in Semiconductor Technology:

As the semiconductor industry evolves in response to these mega trends, it creates exciting career opportunities for professionals across the value chain – designing, fabrication and packaging. From semiconductor design and manufacturing to research and development, there is a growing demand for skilled professionals who can innovate and drive technological advancements in the industry.

The sector is expected to see more than 800,000 to 1 million job openings over the next five years, says staffing company Randstad. The government recently approved $15 billion worth of investments into the sector including from the Tata group. India’s burgeoning semiconductor sector is facing a surge in demand for talent, fuelled by new investments and the government’s ambitious plan to transform the country into a chip manufacturing hub.

1. Semiconductor Design Engineer:Semiconductor design engineers play a crucial role in developing the architecture and circuitry of semiconductor chips. They utilize tools like Electronic Design Automation (EDA) software and simulation tools to design and optimize chip layouts for performance, power efficiency, and manufacturability.
2. Process Engineer:Process engineers are responsible for developing and optimizing semiconductor manufacturing processes. They work closely with equipment vendors and manufacturing teams to ensure the smooth operation of semiconductor fabrication facilities, improve yield rates, and reduce production costs.
3. Research Scientist:Research scientists in the semiconductor industry focus on exploring new materials, devices, and technologies to push the boundaries of semiconductor innovation. They conduct experiments, analyze data, and collaborate with cross-functional teams to develop next-generation semiconductor solutions.
4. Material Engineers:Material engineers in the semiconductor industry are pivotal in researching, selecting, and optimizing the materials used in semiconductor device fabrication. Their expertise spans a wide range of materials, including silicon, gallium arsenide, and various compound semiconductors. Material engineers work closely with semiconductor design teams to ensure that the chosen materials meet the performance requirements of the intended applications while also considering factors such as cost, scalability, and reliability. Additionally, they play a crucial role in developing new materials and processes to push the boundaries of semiconductor technology, enabling advancements in areas such as miniaturization, power efficiency, and functionality.
5. Product Marketing Manager:Product marketing managers play a vital role in bringing semiconductor products to market. They conduct market research, develop marketing strategies, and collaborate with sales teams to promote semiconductor products and drive revenue growth.
6. Quality Assurance Engineer:Quality assurance engineers ensure that semiconductor products meet the highest standards of quality and reliability. They develop and implement test plans, conduct performance testing, and analyze data to identify and address any issues or defects in semiconductor products.
7. Packaging experts:Packaging experts in the semiconductor industry are instrumental in developing and implementing packaging solutions that safeguard semiconductor chips. Their role entails meticulous selection of packaging materials, designing efficient packaging structures to ensure protection against environmental factors and mechanical stresses, and optimizing designs for thermal management and electrical performance. They collaborate closely with design and manufacturing teams to ensure that packaging solutions meet stringent industry standards while balancing factors such as cost-effectiveness and manufacturability.
8. Clean room specialists:They play a pivotal role in maintaining the pristine conditions necessary for semiconductor fabrication processes. They are responsible for meticulously managing and monitoring cleanroom environments to prevent contamination that could compromise the quality and reliability of semiconductor devices. Clean room specialists enforce strict cleanliness protocols, perform regular inspections, and oversee cleaning procedures to ensure compliance with industry standards and regulations. Their expertise ensures that semiconductor manufacturing facilities operate in controlled environments conducive to high-quality production.
9. Machine maintenance technicians:They are essential for sustaining the operational efficiency and reliability of semiconductor manufacturing equipment. Their responsibilities include conducting routine maintenance tasks, performing diagnostics, troubleshooting equipment issues, and executing repairs as needed to minimize downtime and optimize production throughput. Machine maintenance technicians also play a crucial role in implementing preventive maintenance schedules, identifying opportunities for equipment upgrades or optimizations, and ensuring compliance with safety regulations and operational standards. Their expertise contributes to the overall efficiency and longevity of semiconductor manufacturing operations.
10. Safety protocol checkers:These people are integral to maintaining a safe and secure work environment within semiconductor manufacturing facilities. They are responsible for enforcing safety regulations, conducting regular inspections to identify potential hazards, and implementing corrective measures to mitigate risks and prevent accidents. Safety protocol checkers also play a vital role in developing and implementing safety training programs, conducting safety audits, and promoting a culture of safety awareness among employees. Their diligence and vigilance help to safeguard the well-being of personnel, protect semiconductor manufacturing equipment, and maintain the integrity of semiconductor processes.

Career Opportunities Across the Ecosystem

• Global Semiconductor Giants: Intel, Micron, AMD, Qualcomm, NXP
• Indian Startups & Design Houses: Saankhya Labs, Steradian Semiconductors, Signalchip
• Manufacturing Units: Tata Group, Vedanta-Foxconn, ISMC
• Government & Defense: DRDO, ISRO, SCL (Semiconductor Lab)
• Academia & R&D: IITs, IIITs, National Labs

India’s Policy Ecosystem: Creating the Right Conditions

India’s semiconductor journey isn’t just market-driven—it’s backed by clear, consistent policy action:

• Production Linked Incentive (PLI) Scheme to support manufacturers.
• Design Linked Incentive (DLI) Scheme for fabless startups and institutions.
• Modernization of the Semiconductor Laboratory (SCL) in Mohali into a full-fledged fab.
• State-level incentives, like Odisha’s offer of 25% subsidy on capex for fabs and 20% for fabless companies.

Moreover, global giants like Applied Materials, Lam Research, and Samsung Semiconductor India Research (SSIR) are expanding operations in India—indicating long-term confidence in India’s talent and policy framework.

A Strategic Moment for Indian Youth

The rise of India’s semiconductor sector presents a rare, perhaps once-in-a-generation, opportunity. Engineers who upskill today can become:

• The designers of India’s next chip
• The technicians behind India’s first fab line
• The entrepreneurs launching fabless startups
• The leaders driving India’s tech sovereignty

At a time when countries are scrambling to secure chip supply chains, India is carving a unique place for itself—not just as a consumer but as a creator. But this vision hinges on talent.

That’s why engineers—especially young graduates and final-year students—must look seriously at semiconductors. With government support, ESSCI’s training programs, and private sector momentum, the time to act is now.

Conclusion: From Potential to Powerhouse

India is no longer at the sidelines of the global chip race. With strong policy, infrastructure investment, and a strategic location, it is emerging as a serious contender. But no chip factory can run without engineers. The success of India’s semiconductor mission will ultimately depend on its people—its skilled, driven, and future-ready engineers.

The post Why Semiconductor Jobs Are the Next Big Thing for Indian Engineers appeared first on ELE Times.

Power semiconductor technology firm ROHM says that it is one of the key silicon providers supporting NVIDIA’s new 800V High-Voltage Direct Current (HVDC) architecture. This marks a pivotal shift in data-center design, enabling megawatt-scale AI factories that are more efficient, scalable, and sustainable...

So I am working on my first ee project for a school competition which is a custom macro pad keyboard. I am also going after the building in public trend and making videos on it to keep me honest. I kinda messed up and didn’t order the stencil plate and had to pay more to order it. Looking forward to building this out ! I am planning to use a hot plate for the chips on this. submitted by /u/noamankhalil [link] [comments]

Altum RF’s MMIC amplifiers are now part of Quantic’s plug-and-play X-MWblocks, enabling seamless integration into RF designs. The modular format streamlines design, evaluation, prototyping, and production for rapid RF and microwave system assembly.

The initial offering includes five of Altum RF’s low-noise and driver amplifiers: ARF1200Q2, ARF1201Q2, ARF1202Q2, ARF1203Q2, and ARF1205Q2. These devices cover frequency bands from 13 GHz to 43.5 GHz, with noise figures as low as 1.6 dB. Additional Altum RF MMICs will join the X-MWblocks platform in the coming months.

Quantic X-Microwave offers a catalog of over 6000 RF components for configuring modules, assemblies, and subassemblies. Find Altum RF products here.

Quantic X-Microwave 

Altum RF

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Expanding Qorvo’s GaN-on-SiC SATCOM portfolio, the QPA1722 K-band power amplifier improves Low Earth Orbit (LEO) satellite performance. Qorvo reports the amplifier delivers three times the instantaneous bandwidth and 10% higher efficiency than comparable devices, all within a 38% smaller footprint. These enhancements enable higher data throughput and support more compact, efficient satellite payload designs.

The QPA1722 operates from 17.7 GHz to 20.2 GHz, delivering up to 10 W (40 dBm) saturated and 6 W (37 dBm) linear output power. It provides more than 1 GHz of instantaneous bandwidth to support high data-rate applications, with 36% efficiency for improved power handling and thermal performance. Additional specifications include 26 dB small-signal gain, 35% power-added efficiency, and –25 dBc third-order intermodulation distortion.

Housed in a 6.0×5.0×1.64-mm surface-mount package, the QPA1722 is fully matched to 50 Ω with DC-grounded input and output ports. On-chip blocking capacitors follow the DC grounds at both ports.

The QPA1722 power amplifier is sampling now, with volume production planned for fall 2025. Evaluation kits are available upon request.

QPA1722 product page 

Qorvo

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Anritsu has added a simultaneous sweep feature to its ShockLine MS46131A 1-port vector network analyzer (VNA), which operates up to 43.5 GHz. The capability supports parallel 1-port S-parameter measurements across up to four MS46131A units.

Simultaneous sweep enables coordinated triggering through an external signal, aligning the start of sweeps across multiple VNAs. Each unit can be configured independently with different start and stop frequencies, IF bandwidths, and point counts while performing synchronized sweeps.

Well-suited for multi-band, multi-configuration test environments, the MS46131A supports synchronized antenna characterization for LTE and Wi-Fi 7, sub-6 GHz and mmWave 5G (FR2 and FR3), and phased array validation. Remote operation is enabled via SCPI commands over uniquely assigned TCP port numbers, allowing full automation and integration into distributed test systems.

The simultaneous sweep feature is available with software version 2025.4.1 and supported on all MS46131A VNAs.

MS46131A product page 

Anritsu

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Powered by an eGaN FET, EPC’s EPC9196 is a 25-A RMS, 3-phase BLDC inverter optimized for 96-V to 150-V battery systems. The reference design targets medium-voltage motor drives, including steering in AGVs, traction in compact autonomous vehicles, and robotic joints.

The EPC9196 is built around the EPC2304, a 200-V, 3.5- mΩ (typical) eGaN FET in a thermally enhanced QFN package. This device enables high-efficiency operation with a peak phase current of 35 A and switching frequencies up to 150 kHz. GaN technology reduces switching losses and dead time, enabling smoother, quieter motor operation even at high PWM frequencies.

Featuring a wide input voltage range from 30 V to 170 V, the EPC9196 integrates gate drivers, housekeeping power, current and voltage sensing, overcurrent protection, and thermal monitoring. The reference design provides dv/dt control below 10 V/ns and supports both sensor-less and encoder-based control configurations. It is compatible with motor drive controller platforms from Microchip, ST, TI, and Renesas.

EPC9196 reference design boards cost $812.50 each and are available from DigiKey. The EPC2304 eGaN FET sells for $3.68 each in reels of 3,000 units.

EPC9196 product page

Efficient Power Conversion 

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