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Фантастична реальність на конференціях "ПТ-2025" і "ПРІТС-2025" kpi ср, 05/21/2025 - 23:12

Нагородження Президентом України Володимиром Зеленським державними нагородами політехників kpi ср, 05/21/2025 - 22:45

Ми пам'ятатимемо про подвиг та жертовність героїв kpi ср, 05/21/2025 - 22:20

🔔 Запрошуємо реєструватися на онлайн-лекторій «Вартові доброчесності: як працює антикорупційна система України» kpi ср, 05/21/2025 - 18:12

Хто може бути викривачем корупції у сфері освіти та науки? kpi ср, 05/21/2025 - 18:07

Відкриття Інноваційного комплексу kpi ср, 05/21/2025 - 17:39

One classic set you’ll see in most vintage mystery movies is an interrogation room with a “two-way” mirror on one wall. This cool gadget lets the witnesses see the suspects from another room while the suspects can see only themselves. Which direction the two-way mirror works in is determined by which side has more light. The bright side is the suspect’s mirror. The dim side is the witness’s window.

So, what does that have to do with electronics?

This simple design idea describes a two-way current mirror that, in dubious analogy to the optical kind, can mirror or transmit according to whether the input or output side is more positive. It comprises just two BJTs and one diode and is highlighted yellow in Figure 1’s 555 triangle wave VCO.

Figure 1 D1, Q3, and Q4 comprise the two-way current mirror. It passively conducts Q2’s collector current to C1 via Q3’s base-collector when OUT versus C1 is negative, but becomes an active inverting unity-gain current source when OUT goes positive and reverses the polarity.

Wow the engineering world with your unique design: Design Ideas Submission Guide

 Here’s how it works.

Let’s call the D1 node the input, and the C1 node the output. When U1’s OUT pin is low, D1 and the mirror are reversed biased. Now, Q2’s collector current I has nowhere to go except to forward-bias Q3’s base-collector junction, as shown in Figure 2. This connects Q2 to C1 so current I linearly ramps C1 negative.

Figure 2 When OUT goes low, Q4 is off while Q3 saturates and transmits negative current I to C1. Keep Vin < 1 V so Q2 won’t saturate.

When C1 descends to U1’s trigger voltage (1.33 V), OUT transitions positive. This swaps polarity across the mirror, forward biasing it, pulling the emitters of Q3 and Q4 positive relative to C1. Q3 and Q4 then assume the role of a normal active unity-gain current mirror. They now mirror an inverted positive version of I to C1, making it ramp positive, as shown in Figure 3. 

Figure 3 With OUT high, the mirror goes active and inverts I into a positive current to charge C1.

When C1 charges up to U1’s threshold (3.67 V), OUT snaps negative again and a new oscillation cycle begins, finishing output of a (theoretically) symmetrical isosceles triangle waveshape. Keep Vin < 1 V.

Details, including strengths and weaknesses, of the classic two-transistor current mirror can be found in numerous electronics design references.

Of course, a complementary version of the two-way mirror could also be made with NPN transistors. If a current source replaces Q2’s current sink, it will work equally well.

You might be wondering what’s D1 for? When OUT goes low, both transistor emitters are reverse-biased, so no current should flow through the input node anyway. Therefore, D1 is superfluous, right?

Well, no, it isn’t. The reason is summed up in the term “reverse beta.” It turns out that when you reverse-bias a BJT’s base-emitter junction and forward-bias its base-collector, significant current flow is possible—even likely—from collector to emitter. The associated current gain of this upside-down configuration is always way lower than normal beta, but it’s still more than leakage and definitely too significant to ignore. We need D1.

That wraps up the whodunit of the two-way current mirror. Thanks for reading. Sorry if it’s old news to you. It was new news to me when I thought of it, and I hope to show more applications for it in the near future.

 Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

 

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The post A two-way mirror—current mirror that is appeared first on EDN.

Mining exploration company Nimy Resources Ltd of Perth, Western Australia says it has received firm commitments for $2.75m in a share placement from professional and otherwise exempt investors...

According to data from the SiC Patent Monitor of technology intelligence and IP strategy consulting company KnowMade, power silicon carbide (SiC) technology saw robust patenting activity in first-quarter 2025, with over 840 new patent families filed globally...

India’s smartphone market is among the most vibrant and competitive markets globally, with users constantly in search of the perfect balance of performance, innovation, and affordability. In 2025, top players such as Xiaomi, Samsung, Vivo, Oppo and Realme keep raising the tech bar with devices featuring new-generation processors, world class cameras, and fast charging technology. This article discusses the top 10 models that have drawn the attention of the Indian consumers, creating new standards for the mobile technology.

1. Xiaomi 15 Ultra

Headquarter in Beijing, China, Xiaomi is best-known for high-performance smartphones that are competitively priced. The company emphasizes state-of-the-art camera technology, AI-based features, and quick-charging innovations. Xiaomi 15 Ultra is a power-packed flagship phone that is optimized for top-level performance and camera perfection.

Features:

Display: 6.73-inch LTPO AMOLED, 1440×3200 pixels, 120Hz

Processor: Snapdragon 8 Elite (3nm)

RAM & Storage: 12 GB/16GB RAM, 256GB/512GB/1TB storage

Camera: Quad setup (50 MP wide, 50MP telephoto, 200 MP periscope, 50MP ultrawide)

Battery: 5410mAh, 90W wired, 80W wireless charging

OS: Android 15 with HyperOS 2

2. Samsung Galaxy S25 Ultra

Established in 1938, Samsung is a South Korean multinational corporation with headquarters in Suwon, South Korea. Samsung has grown to become one of the global technology giants, manufacturing state-of-the-art electronics, home appliances and smartphones. The Ultra variant from Samsung features a 6.9-inch Dynamic LTPO AMOLED 2 X screen, 200MP main camera, and One UI 7. It’s an expensive option for those seeking world-class performance.

Features:

Display: 6.9-inch Dynamic LTPO AMOLED 2X,1440×3120 pixels, 120Hz

Processor: Snapdragon 8 Elite (3nm)

RAM & Storage: 12GB/16GB RAM, 256GB/512GB/1TB storage

Camera: Quad configuration (200MP wide, 10MP telephoto, 50MP periscope, 50MP ultrawide)

Battery: 5000mAh, 45W wired, 15W wireless charging

OS: Android 15 with One UI 7

3. Samsung Galaxy S25+

Just a bit less pricey than the Ultra, the S25+ maintains high-end specs, such as Snapdragon 8 Elite, 120Hz AMOLED screen, and speedy charging.

Features:

Display: 6.7-inch Dynamic AMOLED 2X, 1440×3120 pixels,120Hz

Processor: Snapdragon 8 Elite

RAM & Storage: 12GB RAM, 256/512GB storage

Camera: Triple setup (50MP wide, 10MP telephoto, 12MP ultrawide)

Battery: 4900mAh, 25Wwired, 15W wireless charging

OS: Android 15 with One UI 7

4. Vivo X200 Pro

Established ijn 2009, Vivo is a Chinese technology brand that operates from its headquarters in Dongguan, China. The brand has become popular worldwide for its style-consious designs, high-end camera features, The Vivo X200 Pro is a professional-grade smartphone made for professional-level photography.

Features:

Display: 6.78-inch LTPO AMOLED, 1260×2800 pixels,120Hz

Processor: MediaTek Dimensity 9400 (3nm)

RAM & Storage: 16GB RAM, 256GB/512GB/1TB storage

Camera: Triple setup (50MP wide, 200 MP periscope, 50MP ultrawide)

Battery: 600mAh, 90W wired, 30W  wireless charging

OS: Andriod with Funtouch OS 15

5. Realme GT 6 Pro

Realme, with its headquarters in Shenzhen, China, is famous for budget-friendly yet high- performance smartphones with fast charging, AI-powered cameras, and gaming-centric features. Realme is famous for aggressive designs, top-notch performance, and flagship-grade features without the premium price. The Realme GT 6 Pro model is a high-end flagship phone built for speed, gaming.

Features:

Display: 6.78-inch LTPO AMOLED, 1264×2780 pixels, 120Hz

Processor: Snapdragon 8s Gen 3 (4nm)

Camera: Triple setup

Battery: 5500mAh, 120W wired charging

OS: Android 14 with Realme UI 5.0

6. OnePlus 13

OnePlus, established in Shenzhen, China, is renowned for high-end flagship phones with seamless OxygenOS, Hasselblad-optimized cameras and rapid charging. OnePlus 13 is a high-end flagship smartphone filled with high-end feature and performance.

Features:

Display: 6.82-inch LTPO AMOLED, 1440×3168 pixels, 120 Hz

Processor: Snapdragon 8 Elite(3nm)

RAM & Storage: 12GB to 1 TB storage

Battery: 6000mAh, 100W wired, 50W wireless charging

7. Oppo Find X7 Ultra

Oppo, headquartered in Dongguan, China, is a leader in camera technology, providing high-resolution photography, AI-driven photography. With emphasis on design, camera technology, and rapid charging, Oppo is a company that keeps innovating, resonating with consumers who desire beautiful yet powerful devices.

Features:

Processor: Snapdragon 8 Gen 3 (4nm)

RAM & Storage: 12GB to 512GB storage

Battery: 5000mAh,100W wired, 50W wireless charging

OS: Android 14 with ColorOS 14

8. Google Pixel 9 Pro

Google, with its headquarters in Mountain View, California, USA, manufactures Pixel phones with stock Android experience, AI-driven photography, and proprietary software features. Google’s Pixel series is renowned for its stock Android experience, unparalleled camera software and AI-driven optimizations, so users can experience, AI-driven photography, and proprietary software features.

Features:

Display: 6.3-inch LTPO OLED

Processor: Google Tensor G4

RAM & Storage: 16GB RAM to 1 TB storage

Camera: Triple arrangement (50MP wide,48MP periscope, 48MP ultrawide)

Battery: 4700mAh, wired 27W, wireless 21W charging

9. Motorola Edge 50 Ultra

Motorola, which was initially established in Chicago, USA, is currently owned by Lenovo (China). It specializes in rugged smartphones, pure Android experience, and AI-powered security features. Motorola Edge 50 Ultra comes with premium design, Snapdragon 8 Elite, and AI-powered security features.

Features:

Display: 6.7-inch P-OLED, pixels 1220×2712, 144Hz

Processor: Snapdragon 8s Gen(4nm)

Battery: 4500mAh, 125W wired, 50W wireless charging

10. iQOO  

Owned by Vivo, iQOO goes after performance-driven users who requires speed, gaming performance, and the latest hardware at a price that’s aggressively priced. iQOO deals in gaming smartphones with high-refresh-rate screens, high-performance chipsets and advanced cooling. iQOO, a gaming monster has a Snapdragon 8 Elite, 144Hz AMOLED screen and 6000mAh battery.

Features:

Display: 6.78-inch AMOLED

Camera: Dual setup (50MP wide, 8MP ultrawide)

Battery: 6400mAh, 80W wired charging

OS: Android 15 with Funtouch OS 15

Smartphone	Market Price	Trend
Xiaomi 15 Ultra	₹1,09,998	Growing demand for camera-centric flagships
Samsung Galaxy S25 Ultra	₹1,06,000	Premium flagship supremacy
Samsung Galaxy S25+	₹89,999	Budget flagship option
Vivo X200 Pro	₹84,999	Robust camera performance
iQOO Neo 10R	₹54,999	Gaming device
Realme GT 6 Pro	₹49,999	Performance-oriented flagship
OnePlus 13	₹79,999	Oxygen OS and Hasselblad cameras
OppoFind X7 Ultra	₹76,000	Camera innovation
Google Pixel 9 Pro	₹95,999	AI-powered photography
Motorola Edge 50 Ultra	₹72,999	Premium design & security

 

Conclusion:

India’s smartphone market continues to be extremely competitive with Android smartphones leading in sales. Vivo, Xiaomi and Samsung continue to top the market with high demand for features with AI, 5G connectivity, and flagship premium devices. Domestic smartphone manufacturing is increasing, lowering import dependence and enhancing the contribution of India as a primary production base for international brands. India’s smartphone market is likely to cross $100 billion, cementing its ranking among the world’s largest and fastest-expanding mobile markets, with more than 150 million smartphones expected to be shipped in 2025.

The post Top 10 Best Selling Android Phones in India appeared first on ELE Times.

In collaboration with NVIDIA of Santa Clara, CA, USA, Infineon Technologies AG of Munich, Germany is developing the next generation of power systems for AI data centers based on a new power delivery architecture with central power generation of 800V high-voltage direct current (HVDC)...

NUBURU Inc of Centennial, CO, USA — which was founded in 2015 and develops and manufactures high-power industrial blue lasers — has announced the official kick off of the working group formed by the mutual management teams of NUBURU and the targeted defense-tech company that is part of the acquisition plan. The working group will also oversee R&D of advanced laser-tech-based solutions designed specifically for defense applications, as part of the firm’s strategic expansion in the defense sector, under the joint-pursuit agreement signed in March...

Like any successful system-on-chip (SoC) effort, a multi-die system-in-package (SiP) project must start with a sound system design. But then what? Are the steps in the SiP design flow different from the stages in an SoC design? What is necessary to ensure that a 2.5D or 3D SiP will be functionally correct, within the power, performance, and cost specifications, and that it will be manufacturable?

The easiest way to answer these questions is to describe the multi-die design process we have developed at Faraday through our participation in SiP designs with our clients.

Co-design from the start

Ideally, the SiP specialists will be involved in the design from the early stages. Even when the design is just a block-level sketch on a napkin, it’s not too early to begin discussing how the IP blocks will be distributed among the dies, and what the implications will be for the completed SiP (Figure 1).

Figure 1 Collaboration on a SiP design can begin with the customer’s selection of chiplets and continue through to a production-ready design. Source: Faraday Technology Corp.

A 2.5D or 3D design adds one or two additional levels to the interconnect hierarchy between the fast, efficient, and dense on-die routing and the slow, power-hungry, and sparse board-level routing. First, advanced packaging provides a silicon interposer for interconnecting the dies.

This level of interconnect is dense, although far less dense than the lower metal layers on a die, and it’s relatively energy-efficient, low-latency, and high-bandwidth, albeit not as good as on-die metal. Stacking dies—going 3D—adds another level to the hierarchy: direct connections between dies, through-silicon vias, and microbumps or hybrid bonding. This level is better than interposer connections, but still not equal to on-die connections.

The challenge in partitioning the multi-die design is that the limitations of each level of interconnect will impose themselves on whatever signals are being routed through that level. Thus, choosing what signals to carry and where will they ultimately impact system power, performance, and area. Therefore, partitioning is a key decision in this process: which IP blocks to put on which dies.

Partitioning will determine which signal paths must be routed on which levels of the routing hierarchy. Thus, partitioning decisions will influence the ease, difficulty, or impossibility of routing and timing closure on each level. If critical signals are placed on an interconnect with insufficient bandwidth or excessive latency to meet requirements, they will impact system performance.

Additionally, they will affect system power, as interconnect power consumption is not inconsequential at the system level. For these reasons, the earlier the SiP-design experts engage with the system designers, the better the resulting design quality is likely to be.

Chip and SiP

There are two distinct cases to consider here. In some SiP designs, all dies that will go into the SiP are already designed. The SiP team will then decide on die placement and, possibly, the order of dies in stacks, and will route the connections between dies. However, the partitioning of functions among the dies and the locations of individual pads on each die have already been fixed. This significantly reduces the SiP design planning problem and limits the SiP designers’ freedom.

In contrast, in some projects, one or more dies are designed specifically for the SiP. One of these new dies will often be an SoC, carrying much of the system functionality and serving as the hub for connections within the SiP. In these cases, much more optimization is possible if the die design and SiP teams work together. At the very least, the die and interposer designers can cooperate on the die pad location to ease the interposer layout.

Deeper cooperation can include optimizing the die floorplan to get the pads for critical interconnect buses in the best place to minimize interconnect length and congestion. Early cooperation may influence choices of protocols and transceivers for die-to-die connections or even reconsider the partitioning.

This added freedom is valuable. The relatively long latency, limited bandwidth, and higher power consumption of interposer and package-substrate interconnect can dominate SiP performance. Therefore, minor adjustments to a die layout that allow for significant improvements in SiP routing can result in substantial gains in system-level quality of results.

Interposer and package

The result of all this planning and co-design is a list of the exact location of each pad on each die and each ball on the package substrate, together with a routing list indicating what must connect to what. An additional vital dataset contains the signal-integrity and power-integrity requirements for each connection.

These latter specifications may come from interface standards such as Universal Chiplet Interconnect Express (UCIe), Bunch of Wires (BoW), or the High-Bandwidth Memory (HBM) channel specifications. Or they may be dictated by specific pin requirements on the dies.

Now, the 2.5D/3D team must design an interposer and package substrate that satisfies the connection, signal, and power-integrity requirements. The design should also minimize overall SiP cost and ensure manufacturability. Needless to say, this is an over-constrained optimization problem—it requires excellent tools and deep design experience to get the best result.

SiP analyses

Successful routing is not the end of this story. Before the SiP design can be released, each trace must be subjected to signal-integrity or power-integrity analysis using special analysis tools, sometimes at the detailed level of multiphysics tools. The SiP design team should provide the system designers with the SiP’s thermal and electrical characteristics for complete thermal analysis. Ideally based on actual circuit activity with production software, this analysis is often vital to ensuring the SiP’s reliability in its intended environment.

This design flow has proven successful at Faraday, emphasizing early engagement among system designers, die design teams, and SiP designers. The latter group must possess the skills and experience to recognize potential issues early, before there is sufficient data for complete analysis, when a partitioning choice, die placement, or pad location may cause trouble downstream.

The SiP team must have the skills and tools to design, optimize, and analyze the interposer and package substrate. As important as this is, the organization must have close relationships with foundry, assembly, and test partners to ensure the SiP will be manufacturable in its intended supply chain (Figure 2).

Figure 2 Close collaboration between design teams, silicon foundries, and OSAT partners is essential for the successful production of a multi-die device. Source: Faraday Technology Corp.

To return to our original question: yes, additional steps, skills, and relationships are necessary to ensure the success of an SiP. These needs make choosing a design partner one of the most critical decisions the management will make on a SiP project.

Next, close cooperation between the design teams, the silicon foundry, and the OSAT partners is necessary to produce a successful multi-die device.

Wang-Jin Chen leads Faraday’s Design Development Methodology team, which focuses on methodology, design flow, verification, and sign-off for advanced package design.

 

Related Content

• A systems approach delivers SiP design
• Heterogeneous integration and the evolution of IC packaging
• Overcoming the Technical Challenges of System-in-Package (SiP)
• Advanced IC Packaging: Fundamentals for the ‘More than Moore’ Era
• SiP package styles for magnetic position sensors have benefits for automotive applications

The post From system design to SiP: What’s the design flow appeared first on EDN.

I do have 2 Hakko FX-100 one for micro soldering and one for bigger tips. They have more than 6 years of almost daily use. But everywhere I go nobody seems to know they exist. To me, old JBC and Weller user, are the holy grail of soldering, the tips are lasting years and they do heat up in couple of seconds, handling thermal grounds like a champ. BTW I did buy mine years ago and they were less than half of what they cost now (WTF) submitted by /u/lollokara [link] [comments]

Since I got taught a lot of new things with my last post, here's another fun peice in my collection. An XM22 Automatic Chemical Agent Detection alarm another chonky over engineered peice of tech that will last forever submitted by /u/Normal-Gur-6432 [link] [comments]

Благодійний концерт під патронатом Національної комісії України у справах ЮНЕСКО «Україна–Європа: жіноче обличчя» kpi вт, 05/20/2025 - 21:58

День донора 2025 в КПІ ім. Ігоря Сікорського kpi вт, 05/20/2025 - 21:48

У НН ІМЗ поліпшують сплави для літальних апаратів kpi вт, 05/20/2025 - 21:24

It's your old basic digital clock project but with simple gates made of diodes and transistors. Left - minutes 00-59 logic with 7490s and diode-transistor logic Middle - PCB for hour 00-23 logic Right - 1Hz clock module with 4060 counter and transistor divide-by-2 latch and "pseudo-sawtooth" output submitted by /u/ZaznaczonyKK [link] [comments]