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A frequently encountered category of analog system component is the precision current source. Many good designs are available, but concise and simple arithmetic for choosing the component values necessary to tailor them to specific applications isn’t always provided. I guess some designers feel such tedious details are just too trivially obvious to merit mentioning. But I sometimes don’t feel that. 

Wow the engineering world with your unique design: Design Ideas Submission Guide

Here are some examples I think some folks might find useful. I hope they won’t feel too terribly obvious, trivial, or tedious.

The circuit in Figure 1 is versatile and capable of high performance.

Figure 1 A simple high-accuracy current source that can source current with better than 1% accuracy.

With suitable component choices, this circuit can: source current with better than 1% accuracy and have Q1 drain currents ranging from < 1mA to > 10 A, while working with power supply voltages (Vps) from < 5V to > 100 V.

Here are some helpful hints for resistor values, resistor wattages, and safety zener D1. First note

• Vps = power supply voltage
• R1(W), Q1(W), and R2(W) = respective component power dissipation
• Id = Q1 drain current in amps

Adequate heat sinking for Q1(W). Another thing assumed is:

Vps > Q1 (Vgs ON voltage) + 1.24 + R1*100µA

The design equations are as follows:

1. R1 = (Vps – 1.24)/1mA
2. R1(W) = R1/1E6
3. Q1(W) = (Vps – Vload – 1.24)*Id
4. R2 = 1.24/Id
5. R2(W) = 1.24 Id
6. R2 precision 1% or better at the temperature produced by #5 heat dissipation
7. D1 is needed only if Vps > 15V

Figure 2 substitutes an N-channel MOSFET for Figure 1’s Q1 and an anode-referenced 431 regulator chip in place of the cathode-referenced 4041 to produce a very similar current sink. Its design equations are identical.

Figure 2 A simple, high-accuracy current sink uses identical design math.

Okay, okay, I can almost hear the (very reasonable) objection that, for these simple circuits, the design math really was pretty much tedious, trivial, and obvious. 

So I’ll finish with a very less obvious and more creative example from frequent contributor Christopher Paul’s DI “Precision, voltage-compliant current source.”

Taking parts parameters from Christopher Paul’s Figure 3, we can define:

1. Vs = chosen voltage across the R3R4 divider
2. V5 = voltage across R5
3. Id = chosen application-specific M1 drain current

Then:

1. Vs = 5V
2. V5 = 5V – 0.65V = 4.35V
3. R5 = 4.35V/150µA = 30kΩ
4. I4 = Id – 290µA
5. R3 = 1.24/I4
6. R4 = (Vs – 1.24)/I4 = 3.76/I4
7. R3(W) = 1.24 I4
8. R4(W) = 3.76 I4
9. M1(W) = Id(Vs – Vd)

For example, if Id = 50 mA and Vps = 15 V, then:

•  I4 = 49.7 mA
• R5 = 30 kΩ
• R4 = 75.7 Ω
• R3 = 25.2 Ω
• R3(W) = 1.24 I4 = 100 mW
• R4(W) = 3.76 I4 = 200 mW
• M1(W) = 500 mW

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

 Related Content

• A precision, voltage-compliant current source
• LM4041 voltage regulator impersonates precision current source
• Simple, precise, bi-directional current source
• A high-performance current source
• Precision programmable current sink

The post Basic design equations for three precision current sources appeared first on EDN.

The South Wales-based compound semiconductor cluster CSconnected has announced a £1m third call in its Supply Chain Development Programme (which was launched in March), delivered in partnership with Cardiff Capital Region (CCR), to accelerate the expansion of the compound semiconductor supply chain in South Wales. The initiative aims to drive job creation, stimulate economic growth and enhance the UK’s strategic position in advanced semiconductor manufacturing...

As the automotive industry transitions to zonal architectures for in-vehicle networking, designers face increasing challenges in connecting a growing number of sensors and actuators. Traditional approaches often rely on microcontrollers and custom software for each network node, resulting in greater system complexity, higher costs and longer development cycles. To overcome these obstacles, Microchip Technology introduced its LAN866x family of 10BASE-T1S endpoint devices with Remote Control Protocol (RCP), extending Ethernet connectivity to the very edge of in-vehicle networks and enabling the vision of Software Defined Vehicles (SDVs).

The LAN866x endpoints are designed to simplify network integration by serving as bridges that translate Ethernet packets directly to local digital interfaces. Unlike conventional solutions, these endpoints are designed to be software-less, reducing the need for node-specific software programming, streamlining silicon usage and physical footprint. With support for standard-based RCP protocols, the endpoints enable centralized control of edge nodes for data streaming and device management. By utilizing a 10BASE-T1S multidrop topology, this solution supports an all-Ethernet, zonal architecture that helps reduce cabling, software integration and cost.

By removing the need for software development at every node, the LAN866x endpoints are designed to reduce both hardware and engineering costs, accelerate deployment timelines and simplify system architecture. The endpoints are well-suited for critical automotive applications such as lighting—covering interior, front and rear headlamps, as well as audio systems and a wide range of control functions. In these applications, the endpoints provide direct bridging of Ethernet data to local digital interfaces controlling LED drivers for lighting, transmitting audio data to and from microphones and speakers, as well as controlling sensors and actuators over the network.

“With the addition of these RCP endpoint devices, Microchip’s Single Pair Ethernet product line empowers designers to realize a true all-Ethernet architecture for Software-Defined Vehicles,” said Charlie Forni, corporate vice president of Microchip’s networking and communications business unit. “We are committed to delivering innovative solutions and supporting our customers with global technical expertise, comprehensive documentation and development tools to further reduce design complexity and help them bring vehicles to market faster.”

The post Microchip introduces edge-enabling LAN866x 10BASE-T1S ethernet for SDVs appeared first on ELE Times.

Specialty analog foundry Tower Semiconductor Ltd of Migdal Haemek, Israel has announced the expansion of its existing, mature 300mm wafer bonding technology (originally developed and in mass production for stacked BSI image sensors) to enable heterogeneous 3D-IC integration across its silicon photonics (SiPho) and silicon germanium (SiGe) BiCMOS processes, including full support by Cadence design tools for the stacked platform technology...

Ascent Solar Technologies Inc of Thornton, CO, USA – which designs and makes lightweight, flexible copper indium gallium diselenide (CIGS) thin-film photovoltaic (PV) panels that can be integrated into consumer products, off-grid applications and aerospace applications – has signed a teaming agreement with Louisiana- and Texas-based NovaSpark Energy, which designs and manufactures mobile hydrogen generation systems for fueling long-range drones and powering critical infrastructure...

NUBURU Inc of Centennial, CO, USA — which was founded in 2015 and developed and previously manufactured high-power industrial blue lasers — has updated its strategic alliance with Tekne S.p.A. (a provider of integrated electronic warfare and cyber capabilities in military vehicles). The companies, along with Tekne’s shareholders, signed a new letter of agreement on 10 November, superseding their previous understanding and establishing a renewed strategic and industrial partnership. This agreement will be implemented by NUBURU via its specialized subsidiary Nuburu Defense LLC, which is focused on delivering laser-based solutions for defense, security and critical infrastructure applications...

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▶️ 43-я Міжнародна конференція IEEE з електроніки та нанотехнологій (ELNANO) kpi чт, 11/13/2025 - 10:00

Caliber Interconnects Pvt. Ltd., announced that it has achieved accelerated turnaround times and first-time-right outcomes for complex chiplet and Automated Test Equipment (ATE) hardware projects. The company has refined its proprietary design and verification workflow, which integrates powerful Cadence solutions to optimize performance, power, and reliability from the earliest stages of design.

Caliber’s advanced methodology significantly enhances the efficiency and precision of designing high-complexity IC packages and dense PCB layouts. By leveraging the Cadence Allegro X Design Platform for PCB and advanced package designs, which features sub- rawing management and auto- routing, Caliber’s teams can work in parallel across various circuit blocks, compressing overall project timelines by up to 80 percent. This streamlined framework is reinforced by a rigorous in-house verification process and custom automation utilities developed using the Allegro X Design Platform’s SKILL-based scripting, ensuring consistent quality and compliance with design rules.

To meet the demands of next-generation interconnects operating at over 100 Gbps, Caliber’s engineers utilize Cadence’s Sigrity X PowerSI and Sigrity X PowerDC solutions. These advanced simulation tools allow the team to analyze critical factors such as signal loss, crosstalk, and power delivery network (PDN) impedance. By thoroughly evaluating IR drop, current density, and Joule heating, Caliber can confidently deliver design signoff, reducing the risk of costly respins and speeding time to market for its customers.

“Our team has elevated our engineering leadership by creating a disciplined workflow that delivers exceptional quality and faster turnaround times for our customers across the semiconductor ecosystem,” said Suresh Babu, CEO of Caliber Interconnects. “Integrating Cadence’s advanced design and simulation environment into our proprietary methodology empowers us to push the boundaries of performance and reliability in complex chiplet and ATE hardware design.”

The post Caliber Interconnects Accelerates Complex Chiplet and ATE Hardware Design with Cadence Allegro X and Sigrity X Solutions appeared first on ELE Times.

The TCP/IP functionality of a connected device uses dynamic RAM allocation because of the unpredictable nature of network behavior. For example, if a device serves a web dashboard, we cannot control how many clients might connect at the same time. Likewise, if a device communicates with a cloud server, we may not know in advance how large the exchanged messages will be.

Therefore, limiting the amount of RAM used by the TCP/IP stack improves the device’s security and reliability, ensuring it remains responsive and does not crash due to insufficient memory.

Microcontroller RAM overview

It’s common that on microcontrollers, available memory resides in several non-contiguous regions. Each of these regions can have different cache characteristics, performance levels, or power properties, and certain peripheral controllers may only support DMA operations to specific memory areas.

Let’s take the STM32H723ZG microcontroller as an example. Its datasheet, in section 3.3.2, defines embedded SRAM regions:

Here is an example linker script snippet for this microcontroller generated by the CubeMX:

Ethernet DMA memory

We can clearly see that RAM is split into several regions. The STM32H723ZG device includes a built-in Ethernet MAC controller that uses DMA for its operation. It’s important to note that the DMA controller is in domain D2, meaning it cannot directly access memory in domain D1. Therefore, the linker script and source code must ensure that Ethernet DMA data structures are placed in domain D2; for example, in RAM_D2.

To achieve this, first define a section in the linker script and place it in the RAM_D2 region:

Second, the Ethernet driver source code must put respective data into that section. It may look like this:

Heap memory

The next important part is the microcontroller’s heap memory. The standard C library provides two basic functions for dynamic memory allocation:

Typically, ARM-based microcontroller SDKs are shipped with the ARM GCC compiler, which includes the Newlib C library. This library, like many others, has a concept of so-called “syscalls” featuring low level routines that user can override, and which are called by the standard C functions. In our case, the malloc() and free() standard C routines call the _sbrk() syscall, which firmware code can override.

It’s typically done in the sycalls.c or sysmem.c file, and may look this:

As we can see, the _sbrk() operates on a single memory region:

That means that such implementation cannot be used in several RAM regions. There are more advanced implementations, like FreeRTOS’s heap4.c, which can use multiple RAM regions and provides pvPortMalloc() and pvPortFree() functions.

In any case, standard C functions malloc() and free() provide heap memory as a shared resource. If several subsystems in a device’s firmware use dynamic memory and their memory usage is not limited by code, any of them can potentially exhaust the available memory. This can leave the device in an out-of-memory state, which typically causes it to stop operating.

Therefore, the solution is to have every subsystem that uses dynamic memory allocation operate within a bounded memory pool. This approach protects the entire device from running out of memory.

Memory pools

The idea behind a memory pool is to split a single shared heap—with a single malloc and free—into multiple “heaps” or memory pools, each with its own malloc and free. The pseudo-code might look like this:

The next step is to make each firmware subsystem use its own memory pool. This can be achieved by creating a separate memory pool for each subsystem and using the pool’s malloc and free functions instead of the standard ones.

In the case of a TCP/IP stack, this would require all parts of the networking code—driver, HTTP/MQTT library, TLS stack, and application code—to use a dedicated memory pool. This can be tedious to implement manually.

RTOS memory pool API

Some RTOSes provide a memory pool API. For example, Zephyr provides memory heaps:

The other example of an RTOS that provides memory pools is ThreadX:

Using external allocator

The other alternative is to use an external allocator. There are many implementations available. Here are some notable ones:

• umm_malloc is specifically designed to work with the ARM7 embedded processor, but it should work on many other 32-bit processors, as well as 16- and 8-bit processors.
• o1heap is a highly deterministic constant-complexity memory allocator designed for hard real-time high-integrity embedded systems. The name stands for O(1) heap.

Example: Mongoose and O1Heap

The Mongoose embedded TCP/IP stack makes it easy to limit its memory usage, because Mongoose uses its own functions mg_calloc() and mg_free() to allocate and release memory. The default implementation uses the C standard library functions calloc() and free(), but Mongoose allows user to override these functions with their own implementations.

We can pre-allocate memory for Mongoose at firmware startup, for example 50 Kb, and use o1heap library to use that preallocated block and implement mg_calloc() and mg_free() using o1heap. Here are the exact steps:

1. Fetch o1heap.c and o1heap.h into your source tree
2. Add o1heap.c to the list of your source files
3. Preallocate memory chunk at the firmware startup

4. Implement mg_calloc() and mg_free() using o1heap and preallocated memory chunk

You can see the full implementation procedure in the video linked at the end of this article.

Avoid memory exhaustion

This article provides information on the following design aspects:

• Understand STM32’s complex RAM layout
• Ensure Ethernet DMA buffers reside in accessible memory
• Avoid memory exhaustion by using bounded memory pools
• Integrate the o1heap allocator with Mongoose to enforce TCP/IP RAM limits

By isolating the network stack’s memory usage, you make your firmware more stable, deterministic, and secure, especially in real-time or resource-constrained systems.

If you would like to see a practical application of these principles, see the complete tutorial, including a video with a real-world example, which describes how RAM limiting is implemented in practice using the Mongoose embedded TCP/IP stack. This video tutorial provides a step-by-step guide on how to use Mongoose Wizard to restrict TCP/IP networking on a microcontroller to a preallocated memory pool.

As part of this tutorial, a real-time web dashboard is created to show memory usage in real time. The demo uses an STM32 Nucleo-F756ZG board with built-in Ethernet, but the same approach works seamlessly on other architectures too.

Sergey Lyubka is the co-founder and technical director of Cesanta Software Ltd. He is known as the author of the open-source Mongoose Embedded Web Server and Networking Library, which has been on the market since 2004 and has over 12K stars on GitHub. Sergey tackles the issue of making embedded networking simpler to access for all developers.

Related Content

• Developing Energy-Efficient Embedded Systems
• Can MRAM Get EU Back in the Memory Game?
• An MCU test chip embeds 10.8 Mbit STT-MRAM memory
• How MCU memory dictates zone and domain ECU architectures
• Breaking Through Memory Bottlenecks: The Next Frontier for AI Performance

The post How to limit TCP/IP RAM usage on STM32 microcontrollers appeared first on EDN.

Vishay Intertechnology, Inc. introduced a new high speed silicon PIN photodiode with enhanced sensitivity to visible and infrared light. Featuring a compact 3.2 mm by 2.0 mm top-view, surface-mount package with a low 0.6 mm profile, the Vishay Semiconductors VEMD8083 features high reverse light current and fast response times for improved performance in biomedical applications such as heart rate and blood oxygen monitoring.

The device offers a smaller form factor than previous-generation solutions, allowing for integration into compact wearables, such as smart rings, and consumer health monitoring devices. However, while its chip size is reduced, the photodiode’s package is optimized to support a large radiant sensitive area of 2.8 mm², which enables high reverse light current of 11 μA at 525 nm, 14 μA at 660 nm, and 16 μA at 940 nm.

The VEMD8083’s high sensitivity is especially valuable in biomedical applications like photo plethysmography (PPG), where it detects variations in blood volume and flow by measuring light absorption or reflection from blood vessels. Accurate detection in these scenarios is essential for diagnosing and monitoring conditions such as cardiovascular disease.

Pin to pin compatible with competing solutions, the device detects visible and near infrared radiation over a wide spectral range from 350 nm to 1100 nm. For high sampling rates, the VEMD8083 offers fast rise and fall times of 30 ns and diode capacitance of 50 pF. The photodiode features a ± 60° angle of half-sensitivity and an operating temperature range of -40 °C to +85 °C.

RoHS-compliant, halogen-free, and Vishay Green, the device provides a moisture sensitivity level (MSL) of 3 in accordance with J-STD-020 for a floor life of 168 hours.

Samples and production quantities of the VEMD8083 are available now.

The post New Vishay Intertechnology Silicon PIN Photodiode for Biomedical Applications appeared first on ELE Times.

thought it looked coo submitted by /u/PoweredBy555 [link] [comments]

This is more of a vent I guess. So maybe it’s because my workbench is in such disarray; my home office is trashed so I started doing work in the downstairs dining room and fucked that place up, too. Wreaking havoc around the house and the other half isn’t having it lol I’m trying to work on this board and wasn’t thinking about serviceability. Only after everything was done, I was like, “oh shit this thing better work”. Got everything wired up and proper, did point to point verification with a multimeter and resolved shorts on the 5v bus and come to find out, when powered on, the ESP32 is not working as expected. Everything is point to point soldered. So I need to rebuild this stupid thing from scratch, but the proper way using wire wrap techniques and socketing the ESP32 and logic level converter boards. Just FYI, this board I’m trying to build is meant to drive a HUB75 RGB panel with text/graphics from a Raspberry Pi’s UART interface. Prototype wise, it’s working as you can see in the background, now I’m trying to put everything on this perfboard as it is mean to be displayed in the open. The ESP32 is also driving 8 x MAX7219 8x8 LED matrix. This is an effort to build a thing centered around AI/LLM. My idea/concept got everyone in the AI community in an uproar, so I’m making an art piece out of it submitted by /u/Prijent_Smogonk [link] [comments]

Пам'яті Микити Купцова kpi ср, 11/12/2025 - 21:33

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Cree LED Inc of Durham, NC, USA (a Penguin Solutions brand) has filed a patent infringement lawsuit in the US District Court for the Northern District of Illinois alleging that Promier Products (trading as LitezAll) and Tractor Supply Co have infringed its rights in the following patents by selling certain portable lighting products: United States Patent Nos. 9070850, 9754926, 10439112, 11791442, D790486 and D892066...

South Korea-based SK keyfoundry — which provides specialty analog and mixed-signal foundry services on 8-inch wafers for consumer, communications, computing, automotive and industrial applications — says that it is accelerating the development of silicon carbide (SiC)-based compound power semiconductor technology, bolstering its efforts for the global power semiconductor market. Leveraging its manufacturing expertise and intellectual property (IP) portfolio across the semiconductor manufacturing process, in first-half 2025 the firm acquired SK powertech (formerly Yes Power Technix, until its acquisition by SK Inc in 2022), which has core competencies in the SiC sector...

Під час ворожої атаки загинув випускник КПІ, фотограф і морпіх Костянтин Гузенко kpi ср, 11/12/2025 - 17:46

😉 Запрошення до публічного обговорення проєкту Положення про отримання та використання благодійної допомоги kpi ср, 11/12/2025 - 17:11

КПІшники — перші серед 787 команд на міжнародних змаганнях з кіберзбезпеки! KPI4U-2 ср, 11/12/2025 - 16:35