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Відкриття Інноваційного комплексу kpi ср, 05/21/2025 - 17:39

One classic set you’ll see in most vintage mystery movies is an interrogation room with a “two-way” mirror on one wall. This cool gadget lets the witnesses see the suspects from another room while the suspects can see only themselves. Which direction the two-way mirror works in is determined by which side has more light. The bright side is the suspect’s mirror. The dim side is the witness’s window.

So, what does that have to do with electronics?

This simple design idea describes a two-way current mirror that, in dubious analogy to the optical kind, can mirror or transmit according to whether the input or output side is more positive. It comprises just two BJTs and one diode and is highlighted yellow in Figure 1’s 555 triangle wave VCO.

Figure 1 D1, Q3, and Q4 comprise the two-way current mirror. It passively conducts Q2’s collector current to C1 via Q3’s base-collector when OUT versus C1 is negative, but becomes an active inverting unity-gain current source when OUT goes positive and reverses the polarity.

Wow the engineering world with your unique design: Design Ideas Submission Guide

 Here’s how it works.

Let’s call the D1 node the input, and the C1 node the output. When U1’s OUT pin is low, D1 and the mirror are reversed biased. Now, Q2’s collector current I has nowhere to go except to forward-bias Q3’s base-collector junction, as shown in Figure 2. This connects Q2 to C1 so current I linearly ramps C1 negative.

Figure 2 When OUT goes low, Q4 is off while Q3 saturates and transmits negative current I to C1. Keep Vin < 1 V so Q2 won’t saturate.

When C1 descends to U1’s trigger voltage (1.33 V), OUT transitions positive. This swaps polarity across the mirror, forward biasing it, pulling the emitters of Q3 and Q4 positive relative to C1. Q3 and Q4 then assume the role of a normal active unity-gain current mirror. They now mirror an inverted positive version of I to C1, making it ramp positive, as shown in Figure 3. 

Figure 3 With OUT high, the mirror goes active and inverts I into a positive current to charge C1.

When C1 charges up to U1’s threshold (3.67 V), OUT snaps negative again and a new oscillation cycle begins, finishing output of a (theoretically) symmetrical isosceles triangle waveshape. Keep Vin < 1 V.

Details, including strengths and weaknesses, of the classic two-transistor current mirror can be found in numerous electronics design references.

Of course, a complementary version of the two-way mirror could also be made with NPN transistors. If a current source replaces Q2’s current sink, it will work equally well.

You might be wondering what’s D1 for? When OUT goes low, both transistor emitters are reverse-biased, so no current should flow through the input node anyway. Therefore, D1 is superfluous, right?

Well, no, it isn’t. The reason is summed up in the term “reverse beta.” It turns out that when you reverse-bias a BJT’s base-emitter junction and forward-bias its base-collector, significant current flow is possible—even likely—from collector to emitter. The associated current gain of this upside-down configuration is always way lower than normal beta, but it’s still more than leakage and definitely too significant to ignore. We need D1.

That wraps up the whodunit of the two-way current mirror. Thanks for reading. Sorry if it’s old news to you. It was new news to me when I thought of it, and I hope to show more applications for it in the near future.

 Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

 

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• LED strings driven by current source/mirror
• Current mirror drives multiple LEDs from a low supply voltage

The post A two-way mirror—current mirror that is appeared first on EDN.

Mining exploration company Nimy Resources Ltd of Perth, Western Australia says it has received firm commitments for $2.75m in a share placement from professional and otherwise exempt investors...

According to data from the SiC Patent Monitor of technology intelligence and IP strategy consulting company KnowMade, power silicon carbide (SiC) technology saw robust patenting activity in first-quarter 2025, with over 840 new patent families filed globally...

India’s smartphone market is among the most vibrant and competitive markets globally, with users constantly in search of the perfect balance of performance, innovation, and affordability. In 2025, top players such as Xiaomi, Samsung, Vivo, Oppo and Realme keep raising the tech bar with devices featuring new-generation processors, world class cameras, and fast charging technology. This article discusses the top 10 models that have drawn the attention of the Indian consumers, creating new standards for the mobile technology.

1. Xiaomi 15 Ultra

Headquarter in Beijing, China, Xiaomi is best-known for high-performance smartphones that are competitively priced. The company emphasizes state-of-the-art camera technology, AI-based features, and quick-charging innovations. Xiaomi 15 Ultra is a power-packed flagship phone that is optimized for top-level performance and camera perfection.

Features:

Display: 6.73-inch LTPO AMOLED, 1440×3200 pixels, 120Hz

Processor: Snapdragon 8 Elite (3nm)

RAM & Storage: 12 GB/16GB RAM, 256GB/512GB/1TB storage

Camera: Quad setup (50 MP wide, 50MP telephoto, 200 MP periscope, 50MP ultrawide)

Battery: 5410mAh, 90W wired, 80W wireless charging

OS: Android 15 with HyperOS 2

2. Samsung Galaxy S25 Ultra

Established in 1938, Samsung is a South Korean multinational corporation with headquarters in Suwon, South Korea. Samsung has grown to become one of the global technology giants, manufacturing state-of-the-art electronics, home appliances and smartphones. The Ultra variant from Samsung features a 6.9-inch Dynamic LTPO AMOLED 2 X screen, 200MP main camera, and One UI 7. It’s an expensive option for those seeking world-class performance.

Features:

Display: 6.9-inch Dynamic LTPO AMOLED 2X,1440×3120 pixels, 120Hz

Processor: Snapdragon 8 Elite (3nm)

RAM & Storage: 12GB/16GB RAM, 256GB/512GB/1TB storage

Camera: Quad configuration (200MP wide, 10MP telephoto, 50MP periscope, 50MP ultrawide)

Battery: 5000mAh, 45W wired, 15W wireless charging

OS: Android 15 with One UI 7

3. Samsung Galaxy S25+

Just a bit less pricey than the Ultra, the S25+ maintains high-end specs, such as Snapdragon 8 Elite, 120Hz AMOLED screen, and speedy charging.

Features:

Display: 6.7-inch Dynamic AMOLED 2X, 1440×3120 pixels,120Hz

Processor: Snapdragon 8 Elite

RAM & Storage: 12GB RAM, 256/512GB storage

Camera: Triple setup (50MP wide, 10MP telephoto, 12MP ultrawide)

Battery: 4900mAh, 25Wwired, 15W wireless charging

OS: Android 15 with One UI 7

4. Vivo X200 Pro

Established ijn 2009, Vivo is a Chinese technology brand that operates from its headquarters in Dongguan, China. The brand has become popular worldwide for its style-consious designs, high-end camera features, The Vivo X200 Pro is a professional-grade smartphone made for professional-level photography.

Features:

Display: 6.78-inch LTPO AMOLED, 1260×2800 pixels,120Hz

Processor: MediaTek Dimensity 9400 (3nm)

RAM & Storage: 16GB RAM, 256GB/512GB/1TB storage

Camera: Triple setup (50MP wide, 200 MP periscope, 50MP ultrawide)

Battery: 600mAh, 90W wired, 30W  wireless charging

OS: Andriod with Funtouch OS 15

5. Realme GT 6 Pro

Realme, with its headquarters in Shenzhen, China, is famous for budget-friendly yet high- performance smartphones with fast charging, AI-powered cameras, and gaming-centric features. Realme is famous for aggressive designs, top-notch performance, and flagship-grade features without the premium price. The Realme GT 6 Pro model is a high-end flagship phone built for speed, gaming.

Features:

Display: 6.78-inch LTPO AMOLED, 1264×2780 pixels, 120Hz

Processor: Snapdragon 8s Gen 3 (4nm)

Camera: Triple setup

Battery: 5500mAh, 120W wired charging

OS: Android 14 with Realme UI 5.0

6. OnePlus 13

OnePlus, established in Shenzhen, China, is renowned for high-end flagship phones with seamless OxygenOS, Hasselblad-optimized cameras and rapid charging. OnePlus 13 is a high-end flagship smartphone filled with high-end feature and performance.

Features:

Display: 6.82-inch LTPO AMOLED, 1440×3168 pixels, 120 Hz

Processor: Snapdragon 8 Elite(3nm)

RAM & Storage: 12GB to 1 TB storage

Battery: 6000mAh, 100W wired, 50W wireless charging

7. Oppo Find X7 Ultra

Oppo, headquartered in Dongguan, China, is a leader in camera technology, providing high-resolution photography, AI-driven photography. With emphasis on design, camera technology, and rapid charging, Oppo is a company that keeps innovating, resonating with consumers who desire beautiful yet powerful devices.

Features:

Processor: Snapdragon 8 Gen 3 (4nm)

RAM & Storage: 12GB to 512GB storage

Battery: 5000mAh,100W wired, 50W wireless charging

OS: Android 14 with ColorOS 14

8. Google Pixel 9 Pro

Google, with its headquarters in Mountain View, California, USA, manufactures Pixel phones with stock Android experience, AI-driven photography, and proprietary software features. Google’s Pixel series is renowned for its stock Android experience, unparalleled camera software and AI-driven optimizations, so users can experience, AI-driven photography, and proprietary software features.

Features:

Display: 6.3-inch LTPO OLED

Processor: Google Tensor G4

RAM & Storage: 16GB RAM to 1 TB storage

Camera: Triple arrangement (50MP wide,48MP periscope, 48MP ultrawide)

Battery: 4700mAh, wired 27W, wireless 21W charging

9. Motorola Edge 50 Ultra

Motorola, which was initially established in Chicago, USA, is currently owned by Lenovo (China). It specializes in rugged smartphones, pure Android experience, and AI-powered security features. Motorola Edge 50 Ultra comes with premium design, Snapdragon 8 Elite, and AI-powered security features.

Features:

Display: 6.7-inch P-OLED, pixels 1220×2712, 144Hz

Processor: Snapdragon 8s Gen(4nm)

Battery: 4500mAh, 125W wired, 50W wireless charging

10. iQOO  

Owned by Vivo, iQOO goes after performance-driven users who requires speed, gaming performance, and the latest hardware at a price that’s aggressively priced. iQOO deals in gaming smartphones with high-refresh-rate screens, high-performance chipsets and advanced cooling. iQOO, a gaming monster has a Snapdragon 8 Elite, 144Hz AMOLED screen and 6000mAh battery.

Features:

Display: 6.78-inch AMOLED

Camera: Dual setup (50MP wide, 8MP ultrawide)

Battery: 6400mAh, 80W wired charging

OS: Android 15 with Funtouch OS 15

Smartphone	Market Price	Trend
Xiaomi 15 Ultra	₹1,09,998	Growing demand for camera-centric flagships
Samsung Galaxy S25 Ultra	₹1,06,000	Premium flagship supremacy
Samsung Galaxy S25+	₹89,999	Budget flagship option
Vivo X200 Pro	₹84,999	Robust camera performance
iQOO Neo 10R	₹54,999	Gaming device
Realme GT 6 Pro	₹49,999	Performance-oriented flagship
OnePlus 13	₹79,999	Oxygen OS and Hasselblad cameras
OppoFind X7 Ultra	₹76,000	Camera innovation
Google Pixel 9 Pro	₹95,999	AI-powered photography
Motorola Edge 50 Ultra	₹72,999	Premium design & security

 

Conclusion:

India’s smartphone market continues to be extremely competitive with Android smartphones leading in sales. Vivo, Xiaomi and Samsung continue to top the market with high demand for features with AI, 5G connectivity, and flagship premium devices. Domestic smartphone manufacturing is increasing, lowering import dependence and enhancing the contribution of India as a primary production base for international brands. India’s smartphone market is likely to cross $100 billion, cementing its ranking among the world’s largest and fastest-expanding mobile markets, with more than 150 million smartphones expected to be shipped in 2025.

The post Top 10 Best Selling Android Phones in India appeared first on ELE Times.

In collaboration with NVIDIA of Santa Clara, CA, USA, Infineon Technologies AG of Munich, Germany is developing the next generation of power systems for AI data centers based on a new power delivery architecture with central power generation of 800V high-voltage direct current (HVDC)...

NUBURU Inc of Centennial, CO, USA — which was founded in 2015 and develops and manufactures high-power industrial blue lasers — has announced the official kick off of the working group formed by the mutual management teams of NUBURU and the targeted defense-tech company that is part of the acquisition plan. The working group will also oversee R&D of advanced laser-tech-based solutions designed specifically for defense applications, as part of the firm’s strategic expansion in the defense sector, under the joint-pursuit agreement signed in March...

Like any successful system-on-chip (SoC) effort, a multi-die system-in-package (SiP) project must start with a sound system design. But then what? Are the steps in the SiP design flow different from the stages in an SoC design? What is necessary to ensure that a 2.5D or 3D SiP will be functionally correct, within the power, performance, and cost specifications, and that it will be manufacturable?

The easiest way to answer these questions is to describe the multi-die design process we have developed at Faraday through our participation in SiP designs with our clients.

Co-design from the start

Ideally, the SiP specialists will be involved in the design from the early stages. Even when the design is just a block-level sketch on a napkin, it’s not too early to begin discussing how the IP blocks will be distributed among the dies, and what the implications will be for the completed SiP (Figure 1).

Figure 1 Collaboration on a SiP design can begin with the customer’s selection of chiplets and continue through to a production-ready design. Source: Faraday Technology Corp.

A 2.5D or 3D design adds one or two additional levels to the interconnect hierarchy between the fast, efficient, and dense on-die routing and the slow, power-hungry, and sparse board-level routing. First, advanced packaging provides a silicon interposer for interconnecting the dies.

This level of interconnect is dense, although far less dense than the lower metal layers on a die, and it’s relatively energy-efficient, low-latency, and high-bandwidth, albeit not as good as on-die metal. Stacking dies—going 3D—adds another level to the hierarchy: direct connections between dies, through-silicon vias, and microbumps or hybrid bonding. This level is better than interposer connections, but still not equal to on-die connections.

The challenge in partitioning the multi-die design is that the limitations of each level of interconnect will impose themselves on whatever signals are being routed through that level. Thus, choosing what signals to carry and where will they ultimately impact system power, performance, and area. Therefore, partitioning is a key decision in this process: which IP blocks to put on which dies.

Partitioning will determine which signal paths must be routed on which levels of the routing hierarchy. Thus, partitioning decisions will influence the ease, difficulty, or impossibility of routing and timing closure on each level. If critical signals are placed on an interconnect with insufficient bandwidth or excessive latency to meet requirements, they will impact system performance.

Additionally, they will affect system power, as interconnect power consumption is not inconsequential at the system level. For these reasons, the earlier the SiP-design experts engage with the system designers, the better the resulting design quality is likely to be.

Chip and SiP

There are two distinct cases to consider here. In some SiP designs, all dies that will go into the SiP are already designed. The SiP team will then decide on die placement and, possibly, the order of dies in stacks, and will route the connections between dies. However, the partitioning of functions among the dies and the locations of individual pads on each die have already been fixed. This significantly reduces the SiP design planning problem and limits the SiP designers’ freedom.

In contrast, in some projects, one or more dies are designed specifically for the SiP. One of these new dies will often be an SoC, carrying much of the system functionality and serving as the hub for connections within the SiP. In these cases, much more optimization is possible if the die design and SiP teams work together. At the very least, the die and interposer designers can cooperate on the die pad location to ease the interposer layout.

Deeper cooperation can include optimizing the die floorplan to get the pads for critical interconnect buses in the best place to minimize interconnect length and congestion. Early cooperation may influence choices of protocols and transceivers for die-to-die connections or even reconsider the partitioning.

This added freedom is valuable. The relatively long latency, limited bandwidth, and higher power consumption of interposer and package-substrate interconnect can dominate SiP performance. Therefore, minor adjustments to a die layout that allow for significant improvements in SiP routing can result in substantial gains in system-level quality of results.

Interposer and package

The result of all this planning and co-design is a list of the exact location of each pad on each die and each ball on the package substrate, together with a routing list indicating what must connect to what. An additional vital dataset contains the signal-integrity and power-integrity requirements for each connection.

These latter specifications may come from interface standards such as Universal Chiplet Interconnect Express (UCIe), Bunch of Wires (BoW), or the High-Bandwidth Memory (HBM) channel specifications. Or they may be dictated by specific pin requirements on the dies.

Now, the 2.5D/3D team must design an interposer and package substrate that satisfies the connection, signal, and power-integrity requirements. The design should also minimize overall SiP cost and ensure manufacturability. Needless to say, this is an over-constrained optimization problem—it requires excellent tools and deep design experience to get the best result.

SiP analyses

Successful routing is not the end of this story. Before the SiP design can be released, each trace must be subjected to signal-integrity or power-integrity analysis using special analysis tools, sometimes at the detailed level of multiphysics tools. The SiP design team should provide the system designers with the SiP’s thermal and electrical characteristics for complete thermal analysis. Ideally based on actual circuit activity with production software, this analysis is often vital to ensuring the SiP’s reliability in its intended environment.

This design flow has proven successful at Faraday, emphasizing early engagement among system designers, die design teams, and SiP designers. The latter group must possess the skills and experience to recognize potential issues early, before there is sufficient data for complete analysis, when a partitioning choice, die placement, or pad location may cause trouble downstream.

The SiP team must have the skills and tools to design, optimize, and analyze the interposer and package substrate. As important as this is, the organization must have close relationships with foundry, assembly, and test partners to ensure the SiP will be manufacturable in its intended supply chain (Figure 2).

Figure 2 Close collaboration between design teams, silicon foundries, and OSAT partners is essential for the successful production of a multi-die device. Source: Faraday Technology Corp.

To return to our original question: yes, additional steps, skills, and relationships are necessary to ensure the success of an SiP. These needs make choosing a design partner one of the most critical decisions the management will make on a SiP project.

Next, close cooperation between the design teams, the silicon foundry, and the OSAT partners is necessary to produce a successful multi-die device.

Wang-Jin Chen leads Faraday’s Design Development Methodology team, which focuses on methodology, design flow, verification, and sign-off for advanced package design.

 

Related Content

• A systems approach delivers SiP design
• Heterogeneous integration and the evolution of IC packaging
• Overcoming the Technical Challenges of System-in-Package (SiP)
• Advanced IC Packaging: Fundamentals for the ‘More than Moore’ Era
• SiP package styles for magnetic position sensors have benefits for automotive applications

The post From system design to SiP: What’s the design flow appeared first on EDN.

I do have 2 Hakko FX-100 one for micro soldering and one for bigger tips. They have more than 6 years of almost daily use. But everywhere I go nobody seems to know they exist. To me, old JBC and Weller user, are the holy grail of soldering, the tips are lasting years and they do heat up in couple of seconds, handling thermal grounds like a champ. BTW I did buy mine years ago and they were less than half of what they cost now (WTF) submitted by /u/lollokara [link] [comments]

Since I got taught a lot of new things with my last post, here's another fun peice in my collection. An XM22 Automatic Chemical Agent Detection alarm another chonky over engineered peice of tech that will last forever submitted by /u/Normal-Gur-6432 [link] [comments]

Благодійний концерт під патронатом Національної комісії України у справах ЮНЕСКО «Україна–Європа: жіноче обличчя» kpi вт, 05/20/2025 - 21:58

День донора 2025 в КПІ ім. Ігоря Сікорського kpi вт, 05/20/2025 - 21:48

У НН ІМЗ поліпшують сплави для літальних апаратів kpi вт, 05/20/2025 - 21:24

It's your old basic digital clock project but with simple gates made of diodes and transistors. Left - minutes 00-59 logic with 7490s and diode-transistor logic Middle - PCB for hour 00-23 logic Right - 1Hz clock module with 4060 counter and transistor divide-by-2 latch and "pseudo-sawtooth" output submitted by /u/ZaznaczonyKK [link] [comments]

Toshiba Electronic Devices & Storage Corp of Kawasaki, Japan has started volume shipments of four new 650V silicon carbide (SiC) MOSFETs (TW031V65C, TW054V65C, TW092V65C and TW123V65C), equipped with its latest third-generation SiC MOSFET chips and housed in a compact 8mm x 8mm x 0.85mm DFN8x8 package...

As introduced last October, the summer of 2024 was once again brutal from a lightning-induced electronics-culling standpoint at the Dipert household. I’ve already covered the hot tub control board that got zapped, as well as documenting the laundry list of other now-DOA devices:

Once again, several multi-port Ethernet switches (non-coincidentally on the ends of those exterior-attached network cable spans) got fried, along with a CableCard receiver and a MoCA transceiver (both associated with exterior-routing coax). My three-bay QNAP NAS also expired, presumably the result of its connection to one of the dead multi-port Ethernet switches. All this stuff will be (morbidly) showcased in teardowns to come.

Those teardown showcases start today with the last item on the list, the QNAP TS-328, which I’d purchased on sale for $169.99 back in January 2019 and fired up for service the following September in 2020. Here again to start are the stock photos I shared back in December 2020 when I editorially covered the TS-328 in detail for the first time (dimensions are 5.59” (H) × 5.91” (W) × 10.24” (D), and its net weight absent HDDs is 3.62 lbs.):

The NAS (network-attached storage device) is tipped over on its left side for “show” in that second photo, if not already obvious. In normal operation, it’s the HDDs that are on their sides.

Now for some real-life snapshots of today’s patient, as usual, accompanied by a 0.75″ (19.1 mm) diameter U.S. penny for size comparison purposes. Front (various status and activity LEDs along the left side, with the power and USB copy buttons, the latter with an integrated USB 3.0 connector for a tethered external storage device, below them):

(Bland) top:

(Even more bland, at least on the outside…hold that thought) left side:

Right side:

Back, with the fan dominating the landscape at upper left, a Kensington security lock site at lower left, the “full range” system speaker (vs the PCB buzzer, which you’ll see later) to its right, and (top-to-bottom along the right side) the recessed reset switch, an undocumented-details (TS-328 user manual is here) “maintenance port”, an audio line-out jack, two RJ45 Gigabit Ethernet ports, side-by-side USB 2.0 (left) and 3.0 (right) connectors, and the power input:

And last, but not least, bottom:

Before I forget, here’s the external power supply (which still seems to be fully functional):

Those three thumbscrews you may have noticed on the NAS’s back panel are our path inside:

Voila:

For orientation purposes, what you’re looking at here is the inside of the right-side shell, with the front of the NAS to the right in the photo:

And here are the now-exposed guts of the NAS, tipped over on its left side and looking down on the primary PCB mounted to the left side’s inside:

Here’s another perspective on the internal assembly, with the NAS still sideways:

And three more views, with the NAS back in its “normal” orientation. Top:

Bottom:

and front:

As it turns out, there are two PCBs in this design, the main one we’ve already caught a glimpse of, and another associated with the three SATA connectors at the back of the HDDs’ “cage” (I’ve briefly “jumped to the future” for the following shot, showing the “cage” already detached):

Back to the present moment. Detaching the “cage” involves removing seven screws, two each at the top and bottom:

And three more that normally mate with the back panel:

With them removed, all that’s left is to detach the two halves of the connection between the two PCBs:

and the “cage” (with PCB still attached) is now free:

Four more screws to go, to detach the PCB from the cage:

Mission accomplished:

Notice what looks like corrosion on this rectangular metal region?

Sorry for ruining the surprise, but this won’t be the last time you see it. I was unable to remove any of it with my fingernail, and trust me, the NAS was never exposed to moisture, so it’s not rust. I don’t know whether it’s an artifact of being lightning-zapped, or (my suspicion) just the outcome of long-term exposure to three heat-generating fast-spinning HDDs in a tiny enclosure.

The dominant IC at the bottom is unsurprising given the PCB’s function, an ASMedia ASM1062 PCI-to-SATA bridge and SATA controller. That said, I’m still somewhat surprised, because the ASM1062 supposedly only supports “two ports of Serial ATA 6Gbps”, but there are obviously three SATA connectors (therefore three SATA ports) in this design. Ideas, readers?

In the ASM1062’s lower left corner is a Macronix 25L4006E 4 Mbit serial interface (SPI, to be precise) NOR flash memory. Given the 25L4006E’s low capacity, not to mention its location on the other side of a PCI interface from the host CPU (whose heatsink you may have already glimpsed in a previous photo), I’m assuming that it only houses the firmware for the ASM1062, not the entire system. And no, it isn’t a NVM cache for the HDDs’ contents, either…

The other side of this PCB is comparatively unmemorable apart from a whole lot more of what looks like corrosion. Given that this side is more directly exposed to the heat coming off the HDDs, coupled with the fact that the HDDs remained fully functional after the NAS’s demise, my working theory as to the discoloration’s root cause (high temperatures) is seemingly bolstered.

Now for the main system PCB (look, more corrosion!):

Before diving in, here are some close-ups of the front while the PCB is still installed, showing the light pipes from the LEDs to the front panel, along with the USB3 port and switch assemblies:

In that earlier overview photo, you might have glimpsed five red marker-augmented (presumably to tip off the company to warranty-voiding owner removal) screw heads. Unfortunately, removing them didn’t enable the PCB to budge. But then I noticed a bulge in the warranty sticker in one corner:

Sneaky, QNAP. Very sneaky!

That further loosened the PCB, but I still couldn’t get it to fully detach from the metal bracket surrounding it, so I removed those four screws too:

Getting closer:

And finally, after disconnecting it from the zip cable-clustered multi-harness morass above it (which in retrospect may have been what kept it stuck in place after the initial six-screw removal process):

The PCB was finally free:

Before diving in, a brief diversion; let’s look more closely at the inside of the back panel, rotated 90° from its “normal” position in the images that follow. That’s the system fan to the left (duh) and the mounting bracket for the speaker to the right:

Remove the two screws that normally hold the mounting bracket in place:

And there’s your transducer!

Back to the PCB. There was, you may have already noticed from the earlier overview image, nothing of particular note on the backside…unless you’re into solder points (or corrosion patches), that is. The front side, however, was more interesting. Here’s the far-right end:

Top-to-bottom along the right edge, again, are the recessed reset switch, the mysterious “maintenance port”, an audio line-out jack, two RJ45 Gigabit Ethernet ports, side-by-side USB 2.0 and 3.0 connectors, and the power input. At the bottom left is the black-color connector, which originally mated with the SATA PCB. And the right-most two off-white colored ones above it go to the speaker (two-pin) and fan (four-pin). Curiously, as you may have already noticed, the other four-pin connector, directly above the upper right corner of the Faraday Cage, seems to be unused in this particular system design.

Speaking of the Faraday cage:

There’s another seemingly unused connector above it, eight-pin and black in color. And the IC in its upper left corner is where, I believe, the primary system firmware resides; it’s a Toshiba (now Kioxia) THGBMNG5D1LBAIL 4 GByte eMMC NAND flash memory module.

Shifting over once more to the left…

At far left is the earlier alluded-to PCB “buzzer”. Above it is a Weltrend Semiconductor WT61P803, which appears to be a microcontroller optimized for power management. Above that is another unpopulated four-pin connector. To the right of the buzzer is the RTC (aka, CMOS) battery (which, by the way, I confirmed post-NAS failure was still functional but swapped anyway, not that it helped…sometimes a dead battery can thwart a successful system start).

Let’s get that heatsink off, shall we? Needle-nose pliers did the trick:

The system CPU, a Realtek RTD1296 based on a 64-bit Arm Cortex-A53 four-core 1.4 GHz cluster, is now exposed to view.

And under the remainder of the Faraday cage:

are four Samsung K4A4g165We BCRC 4 Gbit DDR4-2400 SDRAMs, together comprising the NAS’s 2 GBytes of (non-expandable, obviously) system volatile memory:

I’ll close with a couple of PCB end shots:

and a premise, attempting to answer the fundamental question, “What caused the NAS to fail?” As I’ve mentioned in past coverage of the QNAP TS-328, this NAS doesn’t have a particularly stellar long-term reliability record; see, for example, this Reddit thread or this one, both of which are reminiscent of what I experienced. So, it may have just coincidentally chosen that point in time to expire, driven by long-term heat-induced failure of some component on the PCB, for example. But the chronological proximity to last summer’s lightning debacle is hard to ignore, given that it’d been reliably running for a few weeks shy of four years at that point.

I don’t think the DC power input was the failure point, as the PSU still seems fully functional (as I mentioned earlier). The only other thing physically connected to the NAS was its upper Gigabit Ethernet port; I’d wager that was the Achilles’ Heel, instead. Subsequent non-operation characteristics (a brief twitch of the system fan on each powerup attempt, for example) are past-history reminiscent to me of a PC whose CPU has gone awry. Fundamentally, after all, what is a NAS but a tailored-function, Arm- and Linux-based (in this case) computer? Although I’m unable to find a detailed datasheet on the Realtek RTD1296 online, the overview information I’ve dug up makes repeated mention of dual-port Gigabit Ethernet support, suggesting that, at minimum, the RTD1296 integrates the MAC, thereby providing the requisite failure path.

Agree or disagree with my premise? Anything else that jumps out at you from my dissection? Sound off with your thoughts in the comments!

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The post Analyzing a lightning-zapped NAS appeared first on EDN.

At the SID Display Week 2025 conference in San Jose, CA, USA (13–15 May), micro/nanotechnology R&D center CEA-Leti of Grenoble, France presented the paper ‘Co-Integration of Organic Photodetector with MicroLED Dedicated to Multifunctional Display Application’, representing a step toward multi-functional displays that combine both display and sensing capabilities...

US-based Raytheon (a business of aerospace & defense company RTX of Arlington, VA) has delivered the first AN/TPY-2 radar to the US Missile Defense Agency (MDA) with a complete gallium nitride (GaN)-populated array. The AN/TPY-2 is a missile defense radar that can detect, track and discriminate ballistic missiles in multiple phases of flight...

The speed, efficiency and overall performance of any computing device are all measured by its CPU (central processing unit). A few of the most popular CPU brands, which have made unique inventions and contributed to market value, are headquartered in the USA. Below is an overview of the top 10 CPU brands in the USA, including their popular models.

1. Intel

The Santa Clara, California, headquartered semiconductor giant Intel was founded in 1968 and is framed for its powerful Core and Xeon processors that have enabled it to maintain a dominant market share.

Popular Model:

Intel Core i9 -14900k – 24 cores (8P+ 16E), 32 threads, boost clock up to 6.0 GHz, Intel Thread Director, PCle Gen 5 support.

Intel Core Ultra 9 285K – Processing with AI, 24 cores, 24 threads, 5.7 GHz boost clock, PCle Gen 5 support.

Intel Xeon W9-3495X – Workstation grade, 56 cores, 112 threads, high-performance computing.

2. AMD

AMD is short for Advanced Micro Devices, was founded in 1969 and has its corporate headquarters in Santa Clara, California. Its Ryzen and EPYC processors are favorites in high-performance computing and gaming.

Popular Model:

AMD Ryzen 9 9950X – 16 cores, 32 threads, 5.7 GHz boost, 3D V-Cache tech, PCle Gen 5 compatibility.

AMD Ryzen 7 9800X3D- 8 cores, 16 threads, 5.2GHz boost, tuned for game performance.

AMD EPYC 9754 – Server grade CPU, 128 cores, 256 threads, data center intent.

3. Qualcomm

Qualcomm is headquartered in San Diego, California and is a global leader in the mobile industry. Its Snapdragon CPUs are the brains of smartphones and tablets across the globe.

Popular Model:

Snapdragon 8 Gen 3 – ARM architecture, AI-optimized processing, 5G capabilities, Adreno GPU for visuals.

Snapdragon X Elite – 12 high-performance CPU core, AI-based computing, 45 Tops NPU performance.

Snapdragon 8cx Gen 4 – Engineered for Windows laptops, AI-driven efficiency, ultra-low power consumption.

4. Apple
   

Apple, based in Cupertino, California, develops its own in-house M-series processors such as the M3 Pro and M3 Max that drive MacBooks and Mac desktops. These chips are recognized for their seamless integrations with macOS, offering high performance, energy efficiency and advanced GPU capabilities optimized for creative and professional workloads.

Popular Models:

Apple M3 Pro – 12-core CPU, 18-core GPU, optimized for macOS.

Apple M3 Max – Up to 16 CPU cores, 40 GPU cores.

5. NVIDIA

NVIDIA has its headquarters in Santa Clara, California, USA. It was established in 1993 and has evolved into a worldwide leader in graphics processing units (GPUs), artificial intelligence (AI) hardware, high-performance computing and data center CPUs, such as the Grace Hopper and tegra families.

Popular Model:

NVIDIA Grace Hopper CPU – Server-class, AI processing

Tegra X1+ – Used in consoles such as Nintendo Switch

6. IBM

IBM, Armonk, New York is legacy tech titan famous for its enterprise-level processors, specifically in mainframes and high-performance computing. IBM POWER and z-series processors are very popular among data centers, cloud computing and AI workloads.

Popular Models:

IBM Power10 – 15-core, high security enterprise CPU

IBM z16 – Mainframe chip, for banking and analytics

7. Marvell Technology

Santa Clara, California, based Marvell Technology is a cloud-optimized and networking- centric CPU specialist with scalable ARM-based solutions like ThunderX3 and OCTEON for data centers.

Popular Models:

ThunderX3 – 96-core ARM CPU for data centers.

OCTEON 10 – 5nm AI-optimized networking chip.

8. SiFive

San Mateo, California- based SiFive is a top player in RISC-V architecture, with high-performance, customizable CPUs for many applications, such as embedded systems and data centers.

Popular Models:

Performance P670 – Efficient edge device RISC-V core with high performance

Intelligence X280 – AI inference processing for AI applications.

9. Ampere Computing

Santa Clara, California, based Ampere Computing creates ARM-based server processors such as Altra Max and AmpereOne, designed to provide performance along with power savings in contemporary clouds.

Popular Models:

Ampere Altra Max – 128-core ARM CPU

AmpereOne – Cloud-native CPU for next-generation systems

10. Tenstorrent

Austin, Texas, based Tentorrent is a high-performance and AI company that designs RISC-V CPUs and AI accelerators. It is headed by Jim keller, a highly acclaimed chip architect. The company is looking to transform AI computing by combining high-performance CPUs and AI accelertors.

Popular Models:

Wormhole & Black Hole – High throughput AI datacenter CPUs

 

Brand	Price Range
Intel	$460-$7,103
AMD	$519-$4,998
Qualcomm	$849-$1,598
Apple	$1,499-$2,899
NVIDIA	$42,500
IBM	$41,00-$135,300
Ampere Computing	$2,299-$5,000+

 

Conclusion:

Intel and AMD lead the CPU markets, with their extensive lines of processors designed to support gaming, professional use cases and business applications. Qualcomm leads the space for mobile computing with Snapdragon chips optimized for artificial intelligence-based computing. Apple uses a high-end pricing model for its M-series chips, optimized for integration in macOS. NVIDIA and IBM are also interested in high-performance computing, AI processing and enterprise-level solutions like Grace Hopper and Power10 CPUs. Marvell, SiFive, Ampere and Tenstorrent are new entrants dealing with cloud computing, AI acceleration and RISC-V architecture, but their pricing details for processors are limited.

The post Top 10 CPU Brands in USA appeared first on ELE Times.

Today’s system-on-chip (SoC) designs integrate unprecedented numbers of diverse IP cores, from general-purpose CPUs to specialized hardware accelerators, including neural processing units (NPUs), tensor processors, and data processing units (DPUs). This heterogeneous approach enables designers to optimize performance, power efficiency, and cost. However, it also increases the complexity of on-chip communication, synchronization, and interoperability.

At around the same time, the open and configurable RISC-V instruction set architecture (ISA) is experiencing rapid adoption across diverse markets. This growth aligns with rising SoC complexity and the widespread integration of artificial intelligence (AI), as illustrated in figure below. Nearly half of global silicon projects now incorporate AI or machine learning (ML), spanning automotive, mobile, data center, and Internet of Things (IoT) applications. This rapid RISC-V evolution is placing increasing demands on the underlying hardware infrastructure.

The above graph shows projected growth of RISC-V-enabled SoC market share and unit shipments.

NoCs for heterogeneous SoCs

A key challenge in AI-centric SoCs is ensuring efficient communication among IP blocks from different vendors. These designs often integrate cores from various architectures, such as RISC-V CPUs, Arm processors, DPUs, and AI accelerators, which adds to the complexity of on-chip interaction. So, compatibility with a range of communication protocols, such as Arm ACE and CHI, as well as emerging RISC-V interfaces like CHI-B, is critical.

The distinction between coherent networks-on-chip (NoCs), primarily used for CPUs that require synchronized data caches, and non-coherent NoCs, typically utilized for AI accelerators, must also be carefully managed. Effectively handling both types of NoCs enables the design of flexible, high-performance systems.

NoC architectures address interoperability and scalability. This technology delivers flexible interconnectivity, seamlessly integrating the expanding variety and number of IP cores. Approximately 10% to 13% of a chip’s silicon area is typically dedicated to interconnect logic. Here, NoCs serve as the backbone infrastructure of modern SoCs, enabling efficient data flow, low latency, and flexible routing between diverse processing elements.

Advanced techniques for AI performance

The rapid rise of generative AI and large language models (LLMs) has further intensified interconnect demands, with some now surpassing trillions of parameters and significantly increasing on-chip data bandwidth requirements. Conventional bus architectures can no longer efficiently manage these massive data flows.

Designers are now implementing advanced techniques like data interleaving, multicast communication, and multiline reorder buffers. These methods enable widened data buses with thousands of bits for sustained high-throughput and low-latency communication.

In addition to addressing bandwidth demands, new architectural approaches optimize system performance. One technique is AI tiling, where multiple smaller compute units or tiles are interconnected to form scalable compute clusters.

These architectures allow designers to scale CPU or AI-specific processing clusters from dozens to thousands of cores. The NoC infrastructure manages data movement and communication among these tiles, ensuring maximum performance and efficiency.

Beyond tiling, physical and back-end design challenges intensify at advanced nodes. Below 10 nanometers, routing and layout constraints significantly impact chip performance, power consumption, and reliability. Physically aware NoCs optimize placement and timing for successful silicon realization. Early consideration of these physical factors minimizes silicon respin risk and supports efficiency goals in AI applications at 5 nm and 3 nm.

Reliability and flexibility

Hardware-software integration, including RISC-V register management and memory mapping, streamlines validation, reduces software overhead, and boosts system reliability. This approach manages coherent design complexity, meeting performance and safety standards.

Next. safety certifications have become paramount as RISC-V-based designs enter safety-critical domains such as autonomous automotive systems. Interconnect solutions must deliver high-bandwidth, low-latency communication while meeting rigorous safety standards such as ISO 26262 up to ASIL D. Certified NoC architectures incorporate fault-tolerant features to enable reliability in AI platforms.

Modularity and interoperability across vendors and interfaces have also become essential to keep pace with the dynamic demands of AI-driven RISC-V systems. Many real-world designs no longer follow a monolithic approach.

Instead, they evolve over multiple iterations and often replace processing subsystems mid-development to improve efficiency or time to market. Such flexibility is achievable when the interconnect fabric supports diverse protocols, topologies, and evolving standards.

Andy Nightingale, VP of product management and marketing at Arteris, has over 37 years of experience in the high-tech industry, including 23 years in various engineering and product management positions at Arm.

 

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The post Boosting RISC-V SoC performance for AI and ML applications appeared first on EDN.