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Tawazun Council (an independent government entity that works closely with the Ministry of Defence and security agencies in the United Arab Emirates), aerospace & defense company RTX of Arlington, VA, USA, and Emirates Global Aluminium (EGA, the world’s largest producer of ‘premium aluminium’, and the largest industrial firm in the United Arab Emirates outside the oil and gas industry) have signed a memorandum of understanding (MOU) to establish EGA as a new producer of gallium. EGA is equally owned by Mubadala Investment Company of Abu Dhabi and the Investment Corporation of Dubai, and is the largest company jointly owned by the two Emirates...

A recent Design Idea, “Three discretes suffice to interface PWM to switching regulators,” demonstrated one way to use PWM to control the output of a typical switching voltage regulator. There were some discussions in the comments section about circuit behavior, which influenced design modification. Here’s a low-cost design that evolved in light of those discussions. A logic gate IC, an op-amp, and a few resistors and capacitors buffer a PWM and supplies a signal to the regulator’s feedback pin, Figure 1.

Figure 1 A microprocessor produces a 12-bit, 20 MHz, PWM signal that controls a switching voltage regulator using an inverter IC, an op-amp, resistors, and capacitors to buffer the signal for the regulator’s feedback pin.

Wow the engineering world with your unique design: Design Ideas Submission Guide

For various reasons, it’s difficult, if not impossible, to control a regulator’s output voltage beyond a certain level of accuracy. This design proceeds with a PWM having 12 bits of resolution in mind, operating at a frequency of approximately 4900 Hz.

It’s easy these days to find microprocessors (µPs) that can produce a PWM clocked at 20 MHz. However, the supply currents running through that IC’s power supply bonding wires can cause voltage drops. This means that the PWM signals don’t quite swing to the rails. Worse yet, if the currents vary significantly with the µP’s tasks, the voltage drops can change, and it might not be possible to calibrate the errors out. A simple solution is to buffer the µP with logic gates (typically inverters), which draw negligible current except during switching transients. The gates can be powered from a clean, accurate voltage source, the same as or close in value to that which powers the µP.

The inverter in Figure 1 is a 74LVC2G14GW,125 IC whose paralleled outputs drive an op-amp-based low-pass filter whose passive components are of sufficiently high impedances to negligibly load those outputs. When powered from 3 V or more, this dual inverter has an output resistance of less than 15 Ω from -40°C to +85°C. (If you need to operate the µP at 1.8 V, parallel the 6 inverters of a 74LVC14AD,118 for a less than 19 Ω result.)

The TLV333IDBVR op-amp has a maximum input offset voltage of 15 µV (the maximum offset is specified for a 5-V supply; an unknown increase can be expected if the supply voltage is lower).

Its typical (maximum are not specified) input currents are 150 pA from -40°C to +85°C, contributing an offset through R1, R2, and R3 of 115 µV. At 1.8 V, ½ LSb for a 12-bit signal is 220 µV (370 µV with a 3.0-V supply.) The filter settles to much less than that 12-bit ½ LSb voltage in 10mS and has a peak (not peak-peak) ripple of less than 50µV.

R4 and R5 should be chosen so that the intended most positive op-amp output voltage multiplied by R4 / (R4 + R5) is at most slightly greater than Vfb. This allows a regulator output of Vfb. This ratio could be smaller if the minimum desired regulator output is larger than Vfb. The resistors’ parallel combination should be the value specified by the regulator for the single resistor connected between Vfb and ground, typically 10 kΩ. R6 should be set in accordance with the desired range of output voltages.

The allowed range of PWM duty cycles should exclude extremes for at least two reasons. First, the op-amp output is only guaranteed to swing within 70 mV of each rail (with a 10k load connected to half of the supply voltage.) Second, the processor, GPIO in particular (but also the gate to some extent), likely has unequal rise and fall times and delays. Although these differences are small, they have their greatest effects on accuracy at duty cycle extremes, which therefore should be avoided. Fortunately, accommodating these limitations has a negligible effect on functionality.

In this design, the output voltage is linear with the duty cycle. The regulator’s loop gain is unchanged from that of standard operation. With the regulator disabled until the PWM filter output settles, there are no startup issues. Finally, there is negligible inherent injection of noise into the feedback pin from an external supply.

Christopher Paul has worked in various engineering positions in the communications industry for over 40 years.

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The post Another PWM controls a switching voltage regulator appeared first on EDN.

Epitaxial deposition and process equipment maker Veeco Instruments Inc of Plainview, NY, USA has completed separate exchange transactions pursuant to privately negotiated exchange agreements with the holders of all of its outstanding 3.75% convertible senior notes due 2027...

In a major step towards strengthening India’s semiconductor manufacturing base, Murugappa Group firm CG Power and Industrial Solutions Ltd. has joined hands with Japan’s Renesas Electronics Corporation and Thailand’s Stars Microelectronics to set up an Outsourced Semiconductor Assembly and Test (OSAT) plant in Sanand, Gujarat. The joint venture (JV) plans to launch its first chip from a pilot production line by mid-2026, said Renesas CEO Hidetoshi Shibata.

The JV will invest ₹7,600 crore in five years, funded by a combination of subsidies, equity, and possible borrowings from banks.

CG Power will have a 92.3% shareholding, while Renesas and Stars Microelectronics will have about 6.8% and 0.9%, respectively.

The Sanand plant is set to build up to a capacity of 15 million units a day, manufacturing various semiconductor packages. These comprise traditional packages such as Quad Flat No-Lead (QFN) and Quad Flat Package (QFP), and newer packages such as Flip Chip Ball Grid Array (FC BGA) and Flip Chip Scale Package (FC CSP). The offerings will serve different sectors, including automotive, consumer electronics, industrial, and 5G technology. This initiative aligns with India’s broader strategy to enhance its semiconductor ecosystem and reduce dependence on imports. The Union Cabinet approved the project under India’s Semiconductor scheme on February 29, 2024.

“Renesas CEO Hidetoshi Shibata emphasized that India must focus on building its intellectual property (IP) to boost its competitiveness in the international semiconductor industry.”

Conclusion:

The partnership combines the manufacturing experience of CG Power, Renesas’s cutting-edge semiconductor technology, and Stars Microelectronics’ knowledge in legacy package technology as well as training. As India further develops its semiconductor expertise, the joint venture represents a turning point towards making the nation a leader in the manufacture of chips worldwide. The partnership between Renesas, CG Power and Stars Microelectronics creates the potential for innovation, economic development and technological advancement in India’s semiconductor industry.

The post India’s Semiconductor Push: Renesas-CG Power JV to Debut First Chip by 2026 appeared first on ELE Times.

The Union Cabinet has given clearance to a ₹3,706 crore semiconductor facility in Jewar, Uttar Pradesh, in a major boost to India’s semiconductor manufacturing plans. The facility, a joint initiative of HCL and Foxconn, will help consolidate India’s position in the international chip business.

The semiconductor plant will be set in the ‘Yamuna Expressway Industrial Development Authority’ (YEIDA) area, in the vicinity of the new ‘Noida International Airport’. This makes it easy to have uncontested connectivity and access to necessary infrastructure facilities, making it a most convenient location for semiconductor manufacturing.

The facility will concentrate on producing display driver chips, which are important parts used in mobile phones, laptops, automobile and other electronics. With its ability to produce 20,000 wafers per month, the plant is expected to be a significant player in India’s expanding electronics industry.

Economic Implication:

It is estimated that the semiconductor plant will provide around 2,000 job opportunities, which will offer highly qualified personnel with experience in the electronics and semiconductors industries. It’s also expected that the project will draw additional funding, which will enhance technological growth and development in the region.

The India Semiconductor Mission (ISM) has been actively encouraging indigenous production of chips and the plant is the sixth semiconductor manufacturing plant to be given approval under the scheme.

With the plant slated to go on stream by 2027, its contribution to job creation, technological innovation and economic growth will be substantial.

Conclusion:

The HCL- Foxconn chip manufacturing factory in ‘Jewar’ is an important milestone towards India’s path to self-sufficiency in making chips. The facility is constructed to produce 20,000 wafers per month and 36 million chips a month.

With the manufacture of display driver chips for the applications across many sectors, the plant will strengthen indigenous supply chains, decrease imports and enhance the country’s share in the international semiconductor industry.

The partnership between HCL and Foxconn demonstrates faith in India’s potential, opening doors for further innovation and investments in semiconductor production. As India continues to invest in semiconductor facilities, this move reaffirms its commitment to positioning itself as a global leader in the electronics sector.

The post India’s Semiconductor Expansion: Jewar Facility Set to Boost Chip Production appeared first on ELE Times.

A new co-packaged optics (CPO) solution claims to set the bar for next-generation interconnects serving hyperscale data centers and artificial intelligence (AI) workloads. Broadcom’s third-generation CPO technology delivers 200G per lane while significantly improving thermal designs, handling procedures, fiber routing, and overall yield.

Broadcom’s 200G co-packaged optics is engineered to address scale issues in interconnect, which often lead to link flaps and operational disruptions. This, in turn, affects the industry’s ability to achieve the lowest cost per token. The 200G CPO technology enables scale-up domains to exceed 512 nodes while addressing the bandwidth, power, and latency challenges associated with the increasing size of next-generation foundation model parameters.

CPO is a heterogeneous integration of optics and silicon on a single packaged substrate. Source: Broadcom

A CPO system design integrates optical and electrical components to maximize performance with lower-power optical interconnects. According to Near Margalit, VP and GM of the Optical Systems Division at Broadcom, the company’s CPO technology is driven by its switch ASICs, optical engine, and an ecosystem of passive optical components, interconnects, and system solutions partners.

Broadcom is working closely with its ecosystem partners to optimize the integration of CPO solutions. For instance, it has teamed up with Corning on advanced fiber and connector technologies. It’s also working closely with Twinstar Technologies on high-density fiber cables to scale optical interconnects in next-generation data center and AI infrastructures.

Broadcom’s CPO legacy

Broadcom began its CPO journey in 2021 with the launch of the first-generation Tomahawk 4-Humboldt chipset, which included high-density integrated optical engines, edge coupling, and detachable fiber connectors. Next, the second-generation Tomahawk 5-Bailly chipset deployed 100G per lane. According to Broadcom, it was the industry’s first volume-production CPO solution.

Now, after the launch of the third-generation 200G/lane CPO, Broadcom has telegraphed its commitment to developing a fourth-generation 400G/lane solution. That marks a steady progression of optical interconnect solutions for AI workloads driving higher bandwidth, lower latency, and more power-efficient optical interconnects.

Related Content

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• Global Insights into the Co-Packaged Optics Technology Platform
• Silicon Photonics and Co-Packaged Optics Shine a Light at OFC 2025

The post The 200G/lane CPO pushes optical interconnect boundaries appeared first on EDN.

Offered in TO-263 (D²PAK) Package, Device Combines High Pulse Absorption to 15 J/0.1 s With Power Dissipation of 35 W

Vishay Intertechnology, Inc. announced that it has extended its D2TO35 series of surface-mount thick film power resistors with a new AEC-Q200 qualified device that delivers higher pulse absorption up to 15 J/0.1 s. Offered in the TO-263 (D²PAK) package, the Vishay Sfernice D2TO35H provides high power dissipation of 35 W at a +25 °C case temperature.

The Automotive Grade device released today features a unique design that provides 30 % higher energy absorption than the standard D2TO35 resistor for enhanced protection against short transient pulses. The result is more stable operation in high stress environments, reducing the risk of failure and improving overall system reliability while requiring fewer components to save board space, simplify layouts, and reduce overall solution costs.

The D2TO35H offers high temperature operation to +175 °C; a broad range of resistance values from 1 Ω to 14 kΩ, with tolerances down to ± 2 %; and thermal resistance of 4.28 °C/W. The device will serve as the active discharge, discharge, or precharge resistor for controls, 48 V board nets, BMS, fuel cells, and on-board chargers for HEVs, EVs, and low speed electric vehicles; energy monitoring and metering systems; agricultural vehicles and farm equipment; industrial motor drives, welding equipment, and power tools; and military weapons guidance systems.

The RoHS-compliant resistor offers a non-inductive design and is solder reflow secure at 270 °C/10 s.

The post Vishay Intertechnology Automotive Grade, SMD Thick Film Power Resistor Offers Enhanced Protection Against Short Transient Pulses appeared first on ELE Times.

Two desiccant packs, humidity indicator, ESD bag and bubble wrap… for 2.54mm IDC headers!!! Probably a touch overkill haha! submitted by /u/Datzun91 [link] [comments]

Вартість навчання здобувачів вищої освіти - громадян України (контракт) kpi чт, 05/15/2025 - 23:59

Components 1.100uf ,100v capacitor 2.bc547 transistor 3.4.7k resistor 4.inductor :value unknown cus I grab it off a computer power supply 5.1n4007 diode It also makes this high frequency ringing when it's on like some scifi thing . submitted by /u/electron_561 [link] [comments]

День вишиванки 2025 у КПІ ім. Ігоря Сікорського kpi чт, 05/15/2025 - 21:53

Команда КПІ перемогла у масштабних змаганнях з  кібербезпеки  Hackfinity Battle CTF 2025 kpi чт, 05/15/2025 - 21:39

На війні загинув випускник нашого університету Максим Неліпа kpi чт, 05/15/2025 - 21:16

A new European project supported by the Photonics Partnership that aims to power the digital backbone of modern industry is laying the foundations for ultra-connected smart factories...

Recently placed an order with JLCPCB, and they sent an X-Ray of the board. It's for an LGA CAN transceiver with isolated power-CA-IS2062A. The transformer windings can also be seen. submitted by /u/jonathan__34 [link] [comments]

Sycamore-W, an ultra-thin near-field MEMS speaker from xMEMS, brings premium audio to smartwatches and fitness bands. With dimensions of just 20×4×1.28 mm, it reduces speaker package volume by up to 70%, freeing space within wrist-worn devices for additional biometric sensors or larger batteries. At just 150 mg, Sycamore-W also minimizes weight impact in space-constrained wearables.

Compared to conventional coil speakers—typically 3 mm to 4 mm thick and weighing up to 3 grams—Sycamore-W’s slim profile and low mass significantly reduce bulk. The lighter design minimizes strain and improves comfort for all-day wear.

With solid-state durability, the MEMS speaker offers component-level IP58-rated ingress protection and withstands mechanical shocks up to 10,000 g. It delivers zero phase delay and improved low-frequency response compared to dynamic drivers, exhibiting 1st-order decay—where output falls off more gradually (1/f vs 1/f², or –20 dB vs –40 dB from 2 kHz to 20 Hz)—for stronger bass performance.

Samples of the Sycamore-W are available now to early access customers, with volume production slated for Q2 2026.

Sycamore-W product page

xMEMS Labs 

The post Micro-speaker enables slimmer wearables appeared first on EDN.

The LSM6DSV320X inertial measurement unit (IMU) from ST features dual accelerometers for activity tracking up to 16 g and impact detection up to 320 g. To support edge computing, it integrates a machine-learning core for context awareness with exportable AI features, along with embedded functions such as a finite state machine for configurable motion tracking.

Housed in a compact 3×2.5-mm module, the IMU suits applications ranging from wearables and consumer medical devices to smart home and vehicle crash-detection systems. In addition to the 3-axis accelerometers, it includes a gyroscope with a range of up to ±4000 dps. All three sensors are fully synchronized to simplify application development.

Other features include an embedded sensor fusion low-power algorithm for spatial orientation and an adaptive self-configuration (ASC) function. With ASC, the sensors automatically adjust their settings in real time when a specific motion pattern or machine-learning core signal is detected—without requiring host processor intervention.

In production now, the LSM6DSV320X is supported in the Edge AI Suite and will be added to AIoT Craft by the end of 2025.

LSM6DSV320X product page

STMicroelectronics

The post IMU tracks high-G impacts and motion appeared first on EDN.

Qorvo has expanded its QPG6200 portfolio of low-power wireless SoCs supporting Matter over Thread, Zigbee, and Bluetooth LE. Featuring the company’s ConcurrentConnect technology, the devices enable seamless multiprotocol communication for smart home, industrial automation, and other IoT applications.

Based on the previously announced QPG6200L—now in production with leading smart home OEMs—the QPL6200J, QPL6200M, and QPL6200N deliver up to 20 dBm transmit power in a compact QFN package. Output power is software-configurable to meet global regulatory requirements. All devices are powered by an Arm Cortex-M4F processor running at up to 192 MHz, with 2 MB of nonvolatile memory and 336 kB of RAM.

The table below highlights key differences.

A PSA Certified Level 2 development kit based on the QPG6200L is available now, with the full device family scheduled for production in the third quarter of 2025.

QPG6200J product page

QPG6200L product page

QPG6200M product page

QPG6200N product page

Qorvo

The post SoCs boost smart home interoperability appeared first on EDN.

Anritsu’s Site Master cable and antenna analyzers are now available with optional vector network analyzer (VNA) and vector voltmeter (VVM) capabilities. These additions extend their use to field testing of filters and amplifiers, as well as maintenance of radar and antenna systems, including VHF omnidirectional range (VOR) and instrument landing system (ILS) navigation equipment.

The two-port, one-path VNA covers 5 kHz to 4 GHz or 6 GHz. Calibration options include standard open/short/load accessories, the one-step InstaCal module, or factory ReadyCal for immediate measurements. With over 100 dB of dynamic range and –45 dBm to +9 dBm output power, it supports testing of filters, diplexers, and amplifiers in communication base stations. A 380-µs/point sweep speed accelerates alignment and tuning.

The VVM performs cable phase matching in complex phased array antenna systems, such as VOR/ILS systems at major airports. A table display of individual results simplifies phase matching of multiple cables.

The VNA and VVM options for the Site Master MS2085A and MS2089A portable analyzers are now available, with existing instruments eligible for upgrade.

Site Master product page

Anritsu

The post Field analyzers gain vector functions appeared first on EDN.

Infineon’s CoolGaN 650-V G5 bidirectional switch (BDS) integrates two switches in a single device to actively block current and voltage in both directions. Its monolithic common-drain design with a double-gate structure, based on gate injection transistor technology, improves efficiency, reduces die size, and replaces conventional back-to-back configurations.

The GaN switch simplifies cycloconverter designs by enabling single-stage power conversion, eliminating the need for multiple conversion stages. In microinverters, it supports higher power density and a lower component count. It also enables advanced grid functions such as reactive power compensation and two-way power flow.

The CoolGaN 650-V G5 BDS is offered in a TOLT package with RDS(on) values of 110 mΩ and 55 mΩ. It is now open for ordering, with samples of the 110-mΩ version available.

Infineon Technologies 

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