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In Part 1 of this Design Idea (DI), we saw how a standard electret microphone capsule can be persuaded to detect infrasonic signals down to a fraction of a Hertz by adding some fairly simple equalization. In this second and concluding part, we will improve that circuitry and also add an audio output to allow us to hear the otherwise inaudible.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Figure 1 shows the revised schematic. While the equalization is much the same, the circuitry around the mic itself is more elaborate. Originally, the mic was fed straight from the power rail, potentially causing feedback problems. Now, it is powered from a clean reference source and also enclosed in a feedback loop to help stabilize its operating point.

Figure 1 A new input buffer stabilizes the mic’s operation, while other additions improve the circuit’s performance.

R1 and D1 define a nominal +1.24-V reference supply for the mic’s positive terminal. (D1 is not specified. I used an LM385-1.2, but that family is now obsolete—why?? They seemed trouble-free and well-specified, the -ADJ version being especially useful. But LMV431s or LM4041s look good.) In the absence of any offset, A1’s output rests at -1.24 V, needed for the low end of the mic’s load resistor R4. When everything is set up and stable, the junction of R4 and the mic’s negative terminal is close to 0 V (or common). The mic’s signal rides on that, and is amplified by A2, a portion of it being fed back into A1 by R5 to help to stabilize the mic’s operating point.

Calibration and setting up

All microphones behave slightly differently, mainly owing to the spreads on their internal JFETs, so some initial calibration is needed: the load resistor R4 must be trimmed. Sw1a allows R5 to be open-circuited to speed up this initial adjustment, while Sw1b keeps C2 out of circuit (see below) for the same reason. They are shown in the operating position on the schematic.

Once set, operation will be stabilized by feedback, largely compensating for temperature changes. Without the feedback from A2, the tempco of the voltage across the mic measured around 13 mV/°C; with it, it drops to around 1. R18 trims the residual offset, which can otherwise be up to 200 mV at the output of A4.

C1, at 100n, is enough to hold A1 stable during calibration, but it is C2—10 µF—that defines the low 3-dB point of A1’s circuit, once allowance has been made for the reduction in its effective value by the feedback. If C2 is in circuit at start-up, things take takes ages to settle, so that capacitor is pre-charged and only switched seconds after switch-on. (Charge-injection, as shown in Part 1’s Figure 5, scarcely helped here, perhaps because the feedback neutralizes it.)

U1a generates that delay. C3 and R6 control the period, with R7 and C4 adding positive feedback for a snappy action. U1a then switches U1b to control how C2 is connected. During start-up, C2 is connected between A1’s output (-1.24 V) and the common rail, charging it to its expected operating voltage; during operation, it spans R3, defining the circuit’s time-constant.

That hysteresis is necessary because controlling a ’4053 directly with the slowly changing voltage from an RC network leads to it oscillating (at least with the Motorola and RCA devices to hand; those names alone date them). The chosen delay is longer than strictly necessary, given the values of C1 and R3, but it allows time for the rest of the circuit to settle better. This leaves a spare section of the ’4053; using it to repeat the pre-charging trick on C5 or to short out R14+15 during the start-up period made little difference to the overall settling time.

Acoustically isolating the mic and allowing both it and the circuit to settle properly before calibration is necessary. Temporarily enclosing it in two hollow hemispheres of modeling clay, loosely sealed together, works well. During operation, it should be shielded from any air movements. Even a single sheet of fabric suffices, but a block of open-cell plastic foam or a wodge of acoustic fiber should be even better.

 The rest of the circuit

The circuit around A3 is unchanged except for the added offset-trimming pot R18. A4 adds a two-pole Sallen–Key low-pass filter (f3dB ≈ 12 Hz) to the signal path so that, along with the roll-off from A3, any 50/60 Hz components are attenuated by 35 to 40 dB.

C8 and R14+15 define the overall low-end cut-off which, with the values shown, can vary from about 300 mHz to 1.7 Hz (3 dB points). With R15 maxed out, C1/R3’s time-constant is dominant.

In Part 1, we tried a meter for indication but found it to be rather slow. However, it now becomes a useful add-on, allowing the mic’s load resistance and the offset trim to be set easily. It still indicates the lowest frequencies well.

Figure 2 shows the response to changes in air pressure with R15 set to both its maximum and minimum values. While these are LTspice-derived traces, they closely match the real-world measurements. Compare the top, red trace with Figure 2 in Part 1.

Figure 2 The calculated frequency responses of the circuit with the limiting values of R15.

Actual results are shown in Figure 3. These used the test rig described in Part 1, and were taken with R15 set for maximum bandwidth. Like Part 1’s Figure 5, with which it can be compared, it was scanned manually, so don’t trust the frequency scale to be truly logarithmic. As before, the trace wanders vertically because of flicker or 1/f noise from the JFET, but the overall response and linearity are both clear.

Figure 3 Measured response using a real microphone in the pressure-chamber test rig.

The microphone used was the 10mm-diameter type which was to hand. “Other types are available” but may work differently. Tests using salvaged 5-mm units imply that the sensitivity is roughly proportional to the diaphragm’s area—or the square of its diameter—which seems reasonable. The 5-mm devices were both newer and quieter, presumably like their internal JFETs, so their overall S/N ratios were similar. Use the largest ones you can.

Hearing the infrasound

If we take the infrasonic signals and use them to modulate an audio tone, we can then hear what’s going on, or at least a proxy for it. A recent DI was for a pitch-linear VCO: this DI is of course the project (or gadget) for which that was needed (or wanted).

The oscillator used here is almost identical to one of the variants in that article. It’s shown in Figure 4. We won’t describe its operation here (you can refer back for the details) but there are some changes and additions.

Figure 4 Frequency-modulating an audio tone lets us hear the form of the infrasonics.

As before, the main part of it generates a tone whose frequency is centered at around 500 Hz and which varies by plus or minus an octave—doubling or halving the frequency—for control inputs ranging from plus to minus a volt (roughly), so that it is linear in pitch rather than frequency. That control input is of course the detected infrasonic signal.

Under extreme conditions, that signal can span the power rails—up to ±2.5 V—so it is potted down by R23 and R24. (Something non-linear in place of R24 is tempting but untried. That should allow low-level signals through almost unchanged while compressing the peaks. Perhaps two pairs of back-to-back 1N4148s, with a higher value for R23…)

The audio square wave from U2b feeds R28 and the pair of limiting diodes bridged by C13 and C14 to give a trapezoid of about a volt peak-to-peak. That may be excessive, so C13/14 also pot it down to ~100 mV pk–pk. A8 buffers the signal, R29 providing a ground path while scarcely shunting C14.

For a straightforward ~1 V pk–pk audio output, short out C13, make C14 33 nF, and eliminate R29 and pot R30. Even simpler (and cruder) would be to feed the phones directly from U2 through a 5k pot acting as a volume control. Extra filtering caps across the phones could then be added to taste.

Mixing and matching

We may want that lower signal level because it’s then comparable with the output from A2, which is the mic’s amplified wideband audio signal. R30 lets us cross-fade between that and our tones, should we want to. (And we may, a little later.) The output can now be fed to a power amp (I used a TDA7052A—not shown) and speaker or earphones (with a series resistor). With the left and right ’phones in parallel, the sound is roughly in the middle of your head; connecting them in series (out of phase) gives an “out there” effect, which can be less distracting if you also want to hear the complex soundscape of the planes, trains, and automobiles causing the infrasonics.

While it might be nice to include a sound file here so that you can hear the results, we will have to make do with something visual: a typical trace, showing a passing high-speed train a few hundred meters distant while a couple of planes much further away approach Heathrow Airport.

Figure 5 The effects of a nearby train, a plane or two, and some local traffic can be seen in this trace. Note the x-axis time scale.

Air is not the only element

We mentioned cross-fading earlier, but why might we want it? Two things that I have yet to try will be under the ground and underwater. Sealing a mic in a suitable and appropriately-weighted drinks bottle should make an interesting hydrophone, and the local canal will soon be awash with propeller noises. But will these mainly be directly audible or much lower in frequency? Pressure variations should couple through the bottle walls to the air within and thence to the mic, though probably with low efficiently. Filling the bottle with oil might improve that, at least until it seeps into the mic’s innards.

Another bottle, buried in and grouted into the ground (the local bedrock is chalk, exposed in places) may work as a geophone, not that there should be much audio in that underworld. Seismically quiet it may be round here, but we still get the odd rumble at magnitude 2 or 3.

Final flights of fancy

Wouldn’t it be nice to have a pair of mics, suitably spaced to make a stereo pair and each with its own equalization, perhaps with their summed outputs controlling the tone’s frequency and their individual ones adjusting the relative left–right amplitudes? Control of phase might also be needed, that being the main source of directional information at low frequencies, which could involve some rather complicated voltage-controlled all-pass filtering. Or something. Or a DSP.

If you want to see what electrets can do if customized by serious funding, search for “NASA infrasound” which will produce a slew of fascinating results, spanning environments from the ocean depths to the edge of space. While this DI cannot compete with NASA’s sub-millihertz detection capability, it should be just as much fun and is certainly rather cheaper.

Editor’s Note:

 Part 1 of this DI uses an electret mic to create infrasound. It starts with a basic equalization circuit validated with a DIY test fixture and simulations, and ends with a deeper analysis of the circuit’s real response.

 Part 2 includes refinements to make the circuit more usable while extending its detectable spectrum with an additional technique that allows us to hear the infrasonic signals.

—Nick Cornford built his first crystal set at 10, and since then has designed professional audio equipment, many datacomm products, and technical security kit. He has at last retired. Mostly. Sort of.

 Related Content

• Revealing the infrasonic underworld cheaply, Part 1
• Squashed triangles: sines, but with teeth?
• A pitch-linear VCO, part 1: Getting it going
• Earplugs ready? Let’s make some noise!
• Supersized log-scale audio meter

 

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HARTING India subsidiary of HARTING Technology Group, a leading provider of industrial connectivity solutions, announced the grand opening of its new Technology Centre in Bangalore, often referred to as the Silicon Valley of India. This state-of-the-art facility is a strategically important location designed to foster innovation, enhance research and development, and support the growing demand for advanced connectivity solutions in the region. This location will hold well-trained core Innovation Hub team, Global IT solutions team, and is spread across approx. 7500+ Sq. Ft. area, and is in the industrial zone.

The inauguration took place in presence of some of Mr. Philip Harting, CEO of HARTING Technology Group, and Ms. Mabel Low, APAC Managing Director, along with Mr. Jacob Chandy, Managing Director of HARTING India. Some of the key customers also were present during the inauguration from companies like Schneider, BHEL, Biesse, ALSTOM, Wabtech, WEG, EVERAXIS. The new Technology Centre will serve as a hub for HARTING’s cutting-edge projects, focusing on the development of next-generation connectivity solutions for various industries, including manufacturing, transportation, and telecommunications. With a commitment to driving technological advancements, HARTING India aims to leverage local talent and expertise to create solutions that meet the evolving needs of its customers.

The Technology Centre will feature advanced laboratories, collaborative workspaces, and a dedicated team of engineers and researchers focused on developing innovative products and solutions. HARTING India is committed to investing in the local community and will also provide training and development opportunities for aspiring engineers and technology professionals.

“We are thrilled to establish our Technology Centre in Bangalore, a city known for its vibrant tech ecosystem and skilled workforce,” said Jacob Chandy, Managing Director of HARTING India. “This facility will not only enhance our R&D capabilities but also strengthen our collaboration with local partners and customers. We believe that innovation is key to staying ahead in today’s fast-paced market, and this centre will play a crucial role in our mission to deliver high-quality connectivity solutions.”

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Texas Instruments (TI) is demonstrating new power-management products and designs at the Power Conversion, Intelligent Motion (PCIM) Expo and Conference, May 6-8 in Nuremberg, Germany. At the show, TI is featuring semiconductor advancements for sustainable energy, automotive, USB Type-C and USB Power Delivery (PD), robotics, and motor control, including:

• Industry’s first automotive-qualified inductor-inductor-capacitor (LLC) controller for light electric vehicle charging: TI is debuting its new primary-side LLC controller, the UCC25661-Q1, in a three-stage AC/DC battery charger demonstration for electric two-wheelers. The demonstration showcases how the UCC25661-Q1 controller enables engineers to design a highly efficient and reliable power supply with double the power density using integrated features and TI’s patented Input Power Proportional Control (IPPC).

• 65W dual-port USB PD charger with self-biasing gallium nitride (GaN) flyback: TI is showcasing the industry’s first self-biasing GaN flyback converter, the UCG28826, in a demonstration of its 65W dual-port USB PD charger reference design. Designed for next-generation fast-charging applications, the UCG28826 converter delivers 65W across 90VAC to 264VAC in this reference design, enabling engineers to meet strict efficiency standards, minimize standby power consumption and increase power density.
• Short-circuit detection reference design with Flex: In collaboration with electronics manufacturer Flex, TI is demonstrating a comparison of shunt-based, desaturation and Hall-effect sensor methods for short-circuit detection in automotive onboard chargers and DC/DC converters. Booth visitors will learn how to enhance silicon carbide (SiC) metal-oxide semiconductor field-effect transistor (MOSFET) reliability by optimizing the current-sensing location, method and component selection, and printed circuit board layout to meet end-customer safety requirements.

Why it matters

Rising data consumption levels, shrinking consumer electronics, and a focus on renewable energy and vehicle electrification place unique demands on power engineers to maximize efficiency, push power into smaller spaces, and support higher voltages across all applications.

“TI’s broad portfolio and deep system design expertise on display at PCIM enable power engineers to achieve high performance, reliability and scalability in their next-generation applications,” said Mark Ng, director, Automotive Systems. “In automotive, for example, our power-dense and efficient semiconductors enable nearly every aspect of system design, from improved driving range to optimized charging, and new architectures for a feature-rich experience.”

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Hero MotoCorp, in collaboration with the Automotive Skills Development Council, launched Phase 2 of its flagship CSR initiative, Project Saksham, with a grand Training Inauguration Ceremony.

The initiative, aims to empower 20,000 women across India by providing specialized training for diverse roles in the automotive sector, including sales, service, and emerging areas like Electric Vehicle (EV) maintenance and diagnostics. This Event Was hosted in partnership with NIFA Infocom Services Pvt. Ltd. at the Pradhan Mantri Kaushal Kendra, Agra.

The ceremony was graced by Smt. Hemlata Divakar Kushwaha, Mayor of Agra Municipal Corporation, who served as the Chief Guest. She praised the program’s vision, stating, “Empowering women with technical skills not only benefits them individually but strengthens our economy and community. Initiatives like Project Saksham are crucial steps towards a more inclusive future.”

Adding to the occasion, Mr. Vinkesh Gulati, Vice President, ASDC, emphasized the broader industry impact of the initiative. “The automotive sector is undergoing a major transformation with emerging technologies like EVs. It is vital that women are not just participants but leaders in this evolution. Through Project Saksham, we are committed to building a skilled, gender-diverse workforce ready to meet the demands of the new mobility era,” Mr. Gulati remarked.

Phase 2 of Project Saksham builds on the success of the first phase by expanding its geographic footprint and curriculum. Alongside technical training, the program includes modules on soft skills, workplace readiness, and financial literacy to ensure holistic development.

The NIFA Infocomp-operated centre, Agra will serve as a key hub for delivering this transformative training. With initiatives like Project Saksham, Hero MotoCorp and ASDC reaffirm their dedication to fostering an inclusive, skilled workforce that will shape the future of the Indian automotive industry.

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NUBURU Inc of Centennial, CO, USA — which was founded in 2015 and develops and manufactures high-power industrial blue lasers — has received a notice from NYSE Regulation indicating that it not in compliance with Section 1003(a)(i) of the NYSE American LLC Company Guide, which requires a company to maintain stockholders’ equity of $2m or more if it has reported losses from continuing operations or net losses in two of its three most recent fiscal years...

Analysts estimate that the global market for semiconductors will exceed $600 billion in 2025 and hit the $1 trillion mark by 2030, suggesting a CAGR of over 8%. It’s no surprise that the drivers behind this growth include the semiconductor devices and systems needed to support the rapidly growing segments like artificial intelligence (AI), automotive industries (autonomous driving and EVs), data centers and cloud computing, communications, and consumer electronics.

Electronic design automation (EDA) plays a critical role in the growth of the global semiconductor industry. Yet it’s relatively unknown outside of those who participate directly in the industry. In order to understand the value of EDA, it helps to grasp where EDA fits within the semiconductor supply chain.

Semiconductor value chain

The semiconductor supply chain is both complex and globally distributed. If we consider the portion of the supply chain from design through finished semiconductor products—packaged chips and systems, for example—it comprises the parts shown below.

Figure 1 The semiconductor supply chain encompasses product specification, chip design and verification, manufacturing and assembly, and test and packaging. Source: Bob Smith

Semiconductor companies are the primary users of EDA tools required for designing chips that may contain upward of billions of transistors. In addition to EDA tools, these companies also use semiconductor intellectual property (IP) blocks that are pre-designed and characterized functional blocks to help simplify the design process.

The beginning of the process that feeds the supply chain is the development of new chip designs. Leading into design is the upfront planning, including assessing the target market(s) and market timing requirements—both too early and too late must be avoided—and functional and performance characteristics. Once the plan is in place, the chip design process begins.

Chip design is a complex process that starts with architectural planning and detailed specifications on chip functionality and performance (Figure 2). The next steps take the design through different levels of abstraction and verification. All the blocks in the diagram are served by EDA vendors providing many different EDA products.

Figure 2 Chip design and verification are complex and require several steps before the design can be handed off to manufacturing. Source: Bob Smith

Register transfer level (RTL) design creates a software model of the chip using a hardware description language (HDL) such as Verilog or VHDL. This design must then be rigorously verified using a simulator, and in some cases, the use of hardware-assisted verification known as hardware emulators or FPGA prototypes. Once the software-based design is verified, the next step is another transformation.

Synthesis takes the RTL software design and transforms it into a logic-level netlist. The netlist is a collection of logical components and blocks interconnected to form the circuitry that will perform the chip’s functions. Additional verifications steps are performed after synthesis to ensure that the netlist works as expected.

Once the netlist is verified, the next step is the creation of the actual physical geometries used to define the structures (transistors) and interconnects (wires) that will be manufactured. This step is called place and route. “Place” refers to locating the functional blocks on the chip and “route” speaks to generating the wires that interconnect the blocks.

Physical design is followed by exhaustive verification steps that include checking functionality and timing. Other checks such as power and thermal integrity and design and electrical rule checking assess that requirements for the target semiconductor process have been met. These verification steps are the “gatekeepers” that must be satisfied before the design can be released to manufacturing.

The manufacturing industry includes providers of the equipment and materials that are used to manufacture semiconductor chips. Once manufactured, the fabricated chips are handed off to companies that specialize in the next step of assembly, test, and packaging.

In this final step before the chips can be delivered to market, these companies test the chips and then assemble them into packages. The packaged chips then head to distribution channels that ultimately deliver the chips to product manufacturers to assemble into their products.

The value of EDA

The total revenue contribution of these segments of the supply chain in 2024 was approximately $420 billion. In this same period, the EDA segment generated about $20 billion or ~ 5% of the total revenue. While this sounds like a small piece of the puzzle, the value of EDA goes far beyond what revenue numbers convey.

Where is this “unseen” value in EDA coming from? The answer lies in the complexities of the design process itself, and the driving need to keep up with the competition.

Modern chip design is both complex and challenging. The most sophisticated chips may contain tens of billions of transistors—far beyond the realm of unaided manual design.

Moreover, time to market is everything in the highly competitive market. The ability to design and deliver a new chip to address a market need on time and with the features that will ensure success in the end market is a daunting task. Design teams invest in the EDA and verification tools that help them optimize these tradeoffs.

The cost of designing and verifying a leading-edge chip can be in the hundreds of millions of dollars to go from concept to design completion and release to manufacturing. A design flaw or late delivery can mean the end of a promising new chip and lead to hundreds of millions of dollars or more in unrecoverable costs. Failure is not an option.

EDA tools are the engines that drive the design process and allow semiconductor manufacturers to meet ever-shrinking market windows. The EDA tools themselves and the methodology and flows (“recipes”) that each company develops around them are regarded as highly valuable trade secrets.

While time to market is at the top of the list, there are other considerations that EDA tools also address. These can include product safety, product lifecycle and suitability for specialized applications for markets such as vehicles, medical devices, and defense and aerospace. All these requirements mandate sophisticated design and verification tools that can be applied to ensure designs meet these needs—and deliver on time.

EDA plays another valuable role in the chain as a key driver in bringing new process technologies to market. Development of new semiconductor processes relies on tight partnerships between the process developers and the EDA companies.

It’s expensive to bring a new process to the point where it has been characterized and dialed-in so that it can deliver the yield and performance that potential customers will demand. But to be able to accept designs, semiconductor manufacturing must be able to support the customers with verified EDA tools and flows that will support the new technology. No tool support, no customers.

Semiconductor design is at the front end of the supply chain and the EDA industry provides the tools that are essential for turning out today’s complex chip designs. Without availability of these design automation tools, the new innovations and products that drive the global semiconductor industry forward would come to a screeching halt and the supply chain would wither and atrophy.

Value beyond licensing fee

The insatiable demand for new products from the electronics industry keeps intense pressure on the semiconductor manufacturers to deliver the future. In turn, this demands that the EDA industry continually deliver new tools, technologies and functionality that support the ongoing move to the future. Simply said, there would be no new products or growth in the global electronics market without EDA. Measuring the EDA market solely on revenue contribution vastly understates the value that EDA delivers to the global semiconductor industry.

The ultimate value that the EDA industry delivers to the global semiconductor industry is almost incalculable. Certainly, it is far beyond the licensing and maintenance revenues that the industry generates.

Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI technology community, representing members in the electronic system and semiconductor design ecosystem responsible for its management and operations.

 

Related Content

• Chip design assistant, anyone?
• AI features in EDA tools: Facts and fiction
• EDA interview: with Samsung’s Jeong-Taek Kong
• Find out EDA startups on EE Times‘ Silicon 60 list
• To Conquer SoC Design Challenges, Change EDA Methods and Tools

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Rohde & Schwarz and industry partners will be providing a virtual platform for RF design engineers to enhance their RF expertise and engage with industry leaders at the forefront of innovation. The online event will feature informative presentations by experts from Rohde & Schwarz, The University of Cardiff, Maury Microwave, Qorvo, MathWorks, Analog Devices and Greenerwave.

At the virtual RF Testing Innovations Forum 2025, taking place from May 20 to 21, 2025, design engineers will be able to gain invaluable insights into the latest advancements in RF testing methodologies and technologies. Led by experts from Rohde & Schwarz and industry partners, the two-day event will explore the critical factors expected to shape the future of RF testing.

Agenda highlights of Session 1

Day one of the two-day online event will start by covering subjects such as how to enhance the accuracy of mmWave non-linear vector network analyzers, which monitor harmonic distortion, intermodulation and other non-linear effects that can influence mmWave system performance.

Participants will discover innovative approaches to wideband modulated load pull including how to address typical limitations. This novel approach to RF front-end testing uses an R&S RTP oscilloscope plus an R&S SMW200A wideband vector signal generator. The experts will then take a look at the importance of achieving stable and accurate test levels using closed-loop power control. Areas covered will include supported signal forms, suitable test instrumentation and what needs to be considered to achieve the best results.

Two further presentations will take place before the first day’s session closes at 1:00 pm. One presentation will explore load pull techniques for next generation sub-THz components while the next will look at how to characterize wideband active RF components using real-world stimulus signals, in particular how using a fully modulated signal can speed up the overall testing process as it offers deep insights in a single measurement.

Agenda highlights of Session 2

Day two will open with a keynote interview exploring the evolution of vector network analyzers, considering growing demand for faster and more accurate test solutions while keeping costs down. RF components are becoming more sophisticated, having more features integrated into them and offering unseen performance and frequency coverage, posing new challenges to RF design engineers.

This will be followed by a presentation on dealing with the challenges of on-wafer characterization of bulk acoustic wave filter harmonics, especially in achieving accurate measurements and minimizing distortions. The speaker will outline how to use an advanced probing technique when characterizing the second harmonic performance of BAW filters.

The next presentation will look at how to accelerate antenna pattern analysis and simulation using MATLAB. There will be a particular focus on building the full 3D radiation pattern from a subset of 2D pattern measurements using analytical methods and AI techniques. Participants will also learn how to integrate the measured data into a system level simulation model for wireless communication and radar systems. A talk on dataset acquisition optimization for AI-controlled electronically steerable antennas will then take place before a break.

The RF Testing Innovations Forum 2025 will conclude with a presentation on advanced measurement techniques for ultra-wideband software-defined radios and an outline of the role of the R&S ZNB3000 VNA in RF front-end production.

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NUBURU Inc of Centennial, CO, USA — which was founded in 2015 and develops and manufactures high-power industrial blue lasers — has initiated a strategic working group dedicated to revitalizing its Blue-Laser business unit. The initiative aims to redefine the company’s approach to leveraging laser technology within the defense sector...

Materials supplier Nitride Global of Wichita, KS, USA says it has been accepted into the Plug and Play Semiconductor Accelerator Program. Out of more than 600 applicants, Nitride Global was selected as one of only 20 standout companies chosen to participate in this year’s cohort, recognized for driving the future of semiconductor innovation...

X Міжнародна науково-практична конференція «Математика в сучасному технічному університеті» kpi вт, 05/06/2025 - 11:37

SuperLight Photonics of Enschede, the Netherlands — a spin-off from the University of Twente that is developing a photonic integrated circuit (PIC) wideband laser light source for measurement and detection applications — has partnered with Singapore-based photonics distributor Precision Technologies Pte Ltd...

Міжнародні акредитації освітніх програм КПІ ім. Ігоря Сікорського 2025/05 kpi пн, 05/05/2025 - 21:21

Went to a hamfest near me and found some fun toys. and numitrons submitted by /u/shittyretrocomps [link] [comments]

🎥 КПІАбітFest. Весна 2025 kpi пн, 05/05/2025 - 18:01

A month back, I tore down Walmart’s onn. 4K Streaming Box, the Google TV-based successor to the company’s initial Android TV-based UHD Streaming Device that I’d dissected mid-last year. And as promised in last month’s coverage, this time I’ll be taking a look at the guts of its “stick” form factor sibling, the Google TV-based Full HD Streaming Device, the successor to the Android TV-based FHD streaming stick predecessor that went “under the knife” last December.

Device, stick, or box?

Read through those previous two sentences again and you might catch the meaning behind the “just don’t call it a stick” bit in this writeup’s title; similarly, you might get why last month I wrote:

Also, it’s now called a “box”, versus a “device”. Hold that latter thought until next month…

The word “device” seems to have inconsistent form factor association within Walmart. In the first-generation onn. product line, it referred to the “box”, with the rectangular form factor explicitly called a “stick”. This time around, the “stick” is the “device”, with the square form factor referred to as a “box” instead. Then again, as I mentioned last month, the first generation “box’s” UHD maximum output resolution is now instead referred to as “4K”, and similarly, the “stick” form factor has transitioned from “2K FHD” to “Full HD” in the product name, so…

Anyway…in last month’s piece, I pointed out the surprising-to-me commonality between the hardware in the two “box” generations’ designs. Will the same be the case with the two generations of “stick” devices? And as with Walmart’s “box” devices in comparison to the TiVo RA2400 Stream 4K, will I also encounter commonality between Walmart’s “sticks” and other manufacturers’ devices? There’s only one way to find out…let’s begin with a “stock” shot:

Unboxing the product

Now for the actual packaging of today’s patient, which set me back $14.88 in November 2023.

The joke never seems to get old, at least for me…you might disagree…

Open sesame:

It’s a box-within-a-box!

Flip open the top flap, and we get our first glimpse of the still-protected-by-plastic device inside, along with a sliver of literature (PDF here).

Here they are now freed from their cardboard captivity, as usual accompanied by a 0.75″ (19.1 mm) diameter U.S. penny for size comparison purposes:

Underneath are the AC power adapter, an HDMI extension cable, the remote control and a set of batteries for the latter:

Here’s a close-up of the AC power adapter’s micro-USB connector:

and its markings; interestingly, the max input current is higher than that for last month’s “box” PSU (0.25 A vs 0.2 A), although the output current specs are the same (1 A). I suspect that the input current variance is just efficiency-reflective of the sourcing deviation between the two PSUs, not of the respective systems’ actual power requirements. In fact, I’m expecting a lower-power-consumption SoC inside this time, along with decreased memory and the like.

Here are the “male” and “female” ends of the HDMI extension cable:

And here’s the battery compartment-exposed backside of the remote control, which appears to be identical to last month’s “box” remote:

The teardown

Now for our patient, with dimensions of 3.54 x 1.18 x 0.51 inches (90.5 x 30 x 13 mm), quite close to those of its Android TV-based precursor (3.81 x 1.39 x 0.61 inches). That said, there are some physical design variations between them:

• No passive airflow vents either top or bottom this time, and
• Last time there was no status LED included in the design, and the recessed reset switch and micro-USB power input were on opposite sides of the device. This time, the micro-USB power input is on one end (with the HDMI connector again on the other), and a status LED has been added, next to the reset switch.

A closeup of that last shot reveals, among other things, the FCC ID (2AYYS-8822K2VTG, and no, reminiscent of what I also said last month, I don’t know why there are 21 different FCC documents posted for this ID, either!).

Applying a spudger to the gap between the two case halves get them apart with damage to only one of the plastic tabs.

For orientation purposes, we’re looking at the inside of the top half of the device case, along with the top of the PCB (“top” and “bottom” being somewhat meaningless with a “stick” form factor, as I’ve noted before, but I’m going by where the brand logo is stamped on the case):

The PCB then lifts easily out of the remaining bottom case half.

Here’s the inside of the bottom half of the case, once again accompanied by the top of the PCB:

and now with the PCB flipped over to reveal its bottom side. Note, for example, the light guide (aka, light pipe, light tube) that, as with the one we saw last month, routes the output of the LED on the PCB (at bottom, to the right of the Faraday cage) to the outside world.

Speaking of Faraday cages, let’s flip back to the PCB topside and begin our disassembly. En route to that destination, here are snapshots of both sides:

The heat sink on top clung to the Faraday cage below it stubbornly finally relented in the face of my intense spudger attention.

The Faraday Cage itself was much less removal-resistant:

A look at the ICs

Focusing in proved to be…interesting, among other things (including initially frustrating).

The IC on the left was easy to ID, although the marking was faint (stay tuned for another photo where it’s clearer, courtesy of augmented lighting). It’s Amlogic’s S805X2, another in a long line of examples of onn. devices based on application processors from this supplier. The S805X2 was introduced in Q2 2020, and Wikipedia lumps it into the company’s fourth-generation product line in seeming contrast to the “2” end character in its product line. The “X”, as I explained last month and versus the “Y” version seen in that teardown, refers to its integration of wired Ethernet support, which is a bit curious, particularly for a “stick” form factor device, albeit not unique (note, for example, Ethernet over micro-USB on the Chromecast Ultra).

Versus the Amlogic S805Y-B seen in the Android TV-based “stick” predecessor, the S805X2 bumps up the quad-core Arm Cortex-A35 processor cluster’s clock speed from 1.5 GHz to 1.8 GHz (vs 2 GHz in the Amlogic S905Y4 seen last month, however), upgrades the GPU from the Mali-450MP to the Mali-G31 MP2, and (like last month’s S905Y4) adds decoding support for the AV1 video codec. And speaking of Chromecasts, I need to give credit where it’s due (the Reddit crowd) on this one; it’s essentially-to-exactly the same SoC found in the “HD” variant of Google’s Chromecast with Google TV. The only variance, for which I can’t find clarifying documentation, is that in this case it’s marked “S805X2-B” whereas the one in Google’s design is the “S805X2G”.

Move to the right and you’ll encounter another example of Chromecast with Google TV commonality…sort of. And this one caused me no shortage of teeth-gnashing until I eventually figured it out. Revisiting my last-December teardown of this device’s Android TV-based predecessor, you’ll find that it contains 1 GByte of system DRAM, comprised of two 4 Gbit memory devices. Last month’s “box” sibling, conversely, touts 2 GBytes of system DRAM, assembled from two 8 Gbit memories. I already knew from the product specs on Walmart’s website that this device embeds 1.5 GBytes of DRAM. And so, since I’d thought memory pretty much always is sold in binary-increment capacities (1, 2, 4, 8, 16…), I figured that as with the similarly 1.5 GByte-equipped Chromecast with Google TV HD Edition, I’d find the two-device combo of 8 Gbit and 4 Gbit memories inside.

Problem is, though, that after identifying the other two notable ICs in this design, which you’ll see next, I could only find one other chip: this one. And it’s marking were unlike any I’d ever seen before. Again, they’re quite faint under ambient light; I tried both a loupe and supplemental lighting to make at least the company logo clearer for both me and thee:

Here’s the four-line mark:

[COMPANY LOGO] ARTMEM
ATL4X12324
M102
325M10

Doing web searches for “ARTMEM”, “ATL4X12324” and the combination of the two got me…basically nothing. Eventually, however, I stumbled across an obscure page on MIT’s website that clued me in to the likely full company name, Artmem Technology. That website is totally            in Chinese, however, which didn’t help me at all. But after searching again on the full “Artmem Technology” phrase, I came across the website of another China-based semiconductor supplier, Rayson HI-Tech, which offers an English-language option and identifies Artmem as its subsidiary.

Progress! Diving further into Rayson’s website, specifically to the “Industrial/Automotive LPDDR4/4X” product page, I indeed found a 1.5 GByte product variant (along with other non-binary increment options…3 GBytes and 6 GBytes, specifically) with the following parameters:

• Product model: RS384M32LX4D2BNR-53BT
• Bit width: x32
• Speed (presumably max, and operating voltage-dependent): 3733 Mbps
• Encapsulation mode: FBGA 200-ball
• (Operating) voltage: 1.8/1.1/0.6V
• (Operating) temperature: 25-85°C)

I’m guessing this is our chip, with alternate (subsidiary) supplier branding. Is there an atypical 12 Gbit monolithic memory die inside that package? Or did the company combine more common 8 Gbit and 4 Gbit die side-by-side under a single package “lid”? Or was it a three-die 4 Gbit “stack”? Or did the supplier just “down-bin” a 16 Gbit die to come up with the 12 Gbit guaranteed capacity? I ran this mystery by my long-time colleague Jim Handy, semiconductor memory expert at market analyst firm Objective Analysis, and he had several insights:

• Non-binary packaged unit capacities are more common than I’d realized, especially for LPDDR DRAM variants (which are also commonly spec’d in GByte vs Gbit densities)
• His guess is that there’s a three-die “sandwich” inside, with each die 4 Gbit in capacity, likely sourced from CXMT and/or JHICC, the two major DRAM makers in China, and
• The built-in translation support offered by Google’s Chrome browser works pretty well, judging from the screenshots of Artmem Technology’s English language auto-converted website that he sent me (I’m normally a Mozilla Firefox guy).

Please respond in the comments, readers, if you have additional informed insights on this!

The other notable IC—wireless module, to be precise, as you’ve probably already guessed from its antennas’ proximity—on this side of the PCB and to the right of the mystery DRAM, is much easier to ID. Like its predecessor in last December’s teardown, and unlike its sibling in last month’s teardown, it’s clearly marked on top. This is the 6222B-SRC from Fn-Link, containing a Realtek RTL8822CS Bluetooth-plus-Wi-Fi transceiver (which you can see in the internal photos on the FCC website). There was no separate (PCB-embedded or otherwise) Bluetooth antenna that I could see in this particular design, and Fn-Link’s documentation subsequently confirmed my suspicion that the module optionally supports multiplexing the 2.4-GHz Bluetooth and Wi-Fi functions on the same antenna:

Speaking of which, here are some closeups of those antennas:

Last, but not least, let’s flip the PCB back over again and see what’s underneath that bottom-side Faraday cage we earlier glimpsed:

It’s the nonvolatile memory counterpart to the earlier volatile DRAM; a FORESEE FEMDNN008G-08A39 8 GByte eMMC NAND flash memory module. FORESEE is one of the brand names of a Chinese company called Longsys, who had also acquired the Lexar brand from Micron Technology back in 2017. And speaking of “see”, I think that’s all to see today, at least from me. Let me know what I might have overlooked in the comments!

—Brian Dipert is the Editor-in-Chief of the Edge AI and Vision Alliance, and a Senior Analyst at BDTI and Editor-in-Chief of InsideDSP, the company’s online newsletter.

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The post Walmart’s onn. full HD streaming device: Still not thick, just don’t call it a stick appeared first on EDN.

In booth 450 (Hall 6) at the Power Electronics, Intelligent Motion, Renewable Energy and Energy Management (PCIM 2025) Expo & Conference in Nuremberg, Germany (6–8 May), fabless company Wise-integration of Hyeres, France — which was spun off from CEA-Leti in 2020 and designs and develops digital control for gallium nitride (GaN) and GaN IC-based power supplies — is debuting its digital controller of a silicon carbide (SiC) power demonstrator model. This underscores its expansion into complementary wide-bandgap (WBG) technologies and showcases its WiseWare digital controller’s universality and adaptability across those technologies...

Micro-LED technology firm VueReal Inc of Waterloo, ON, Canada has announced a significant expansion of its reference design kit (RDK) portfolio with new industry-specific bundles. Purpose-built for automotive and consumer electronics, the vertical RDKs are designed to fast-track micro-LED product development and commercialization with unprecedented speed and integration readiness. Debuting in booth 1447 at Display Week 2025 in San Jose, CA, USA, the next-gen bundles validate VueReal’s mission to unlock scalable, sustainable micro-LED adoption across global markets...

Compound semiconductors will be critical to helping the UK achieve its AI action plan, driving economic growth and significant benefits for society, according to a report by Compound Semiconductor Applications (CSA) Catapult...

Embedded Multi-die Interconnect Bridge-T (EMIB-T) was a prominent highlight of the Intel Foundry Direct Connect event. Intel is promoting this advanced packaging technology as a key building block for high-speed chiplet designs and has partnered with major EDA and IP houses to accelerate implementations around EMIB-T technology.

As the nomenclature shows, EMIB-T is built around the Embedded Multi-die Interconnect Bridge (EMIB) technology, a high-bandwidth, low-latency, and low-power interconnect for multi-die silicon. EMIB-T stands for EMIB-TSV and it supports high-bandwidth interfaces like HBM4 and Universal Chiplet Interconnect Express (UCIe). In other words, it’s an EMIB implementation that uses the through-silicon via (TSV) technique to send the signal through the bridge with TSVs instead of wrapping the signal around the bridge.

Figure 1 EMIB-T, which adds TSVs to the bridge, can ease the enablement of IP integration from other packaging designs. Source: Intel

Another way to see EMIB-T is the combination of EMIB 2.5D and Foveros 3D packaging technologies for high interconnect densities at die sizes beyond the reticle limit. Foveros is a 3D chip stacking technology that significantly reduces the size of bump pitches, increasing interconnect density.

All three major EDA powerhouses have joined the Intel Foundry Chiplet Alliance Program, which is intrinsically linked to EMIB-T technology. So, all three are working closely with Intel Foundry to develop advanced packaging workflows for EMIB-T. Start with Cadence’s solution, which helps streamline the integration of complex multi-chiplet architectures.

Next, Siemens EDA has announced the certification of a TSV-based reference workflow for EMIB-T. It supports detailed implementations and thermal analysis of the die, EMIB-T and package substrate, signal and power integrity analysis, and package assembly design kit (PADK)-driven verification.

Synopsys is also collaborating with Intel Foundry to develop an EDA workflow for EMIB-T advanced packaging technology using its 3DIC Compiler. In addition to the EDA trio, Intel Foundry has engaged other players for EMIB-T support. For instance, Keysight EDA is working closely with Intel Foundry to bolster the chiplet interoperability ecosystem.

Figure 2 The EMIB-T advanced packaging technology promises power, performance, and area (PPA) advantages for multi-die chiplet designs. Source: Intel

The EMIB-T silicon bridge technology is a major step toward harnessing advanced packaging for the rapidly emerging chiplets world. Intel Foundry Direct Connect highlighted how the Santa Clara, California-based chipmaker sees this advanced packaging technology in its future roadmaps. More technical details about EMIB-T are likely to emerge later in 2025.

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