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This phenomenon has nothing to do with “Gunsmoke” or with “Have Gun, Will Travel”. (Do you remember those old TV shows?) The phrase “shoot- through” describes unwanted and possibly destructive pulses of current flowing through power semiconductors in certain power supply designs.

In half-bridge and full-bridge power inverters, we have one pair (half-bridge) or two pairs (full-bridge) of power switching devices connected in series from a rail voltage to a rail voltage return. Those devices could be power MOSFETs, IGBTs, or whatever but the requirement in each case is the same. That requirement is that the two devices in each pair turn on and off in alternate fashion. If the upper one is on, the lower one is off. If the upper one is off, the lower one is on.

The circuit board seen in Figure 1 was one such design based on a full-bridge power inverter, and it had a shoot- through issue.

Figure 1 A full-bridge circuit board with a shoot-through issue and the test arrangement used to assess it.

A super simplified SPICE simulation shows conceptually what was going amiss with that circuit board, Figure 2.

Figure 2 A SPICE simulation that conceptually walks through the shoot-through problem occurring on the circuit in Figure 1.

S1 represents the board’s Q1 and Q2 upper switches and S2 represents the board’s Q4 and Q3 lower switches. At each switching transition, there was a brief moment when one switch had not quite turned off by the time its corresponding switch had turned on. With both switching devices on at the same time, however brief that “same” time was, there would be a pulse of current flowing from the board’s rail through the two switches an into the board’s rail return. That current pulse would be of essentially unlimited magnitude and the two switching devices could and would suffer damage.

Electromagnetic interference issues arose as well, but that’s a separate discussion.

Old hands will undoubtedly recognize the following, but let’s take a look at the remedy shown in Figure 3.

Figure 3 Shoot-through problem solved by introducing two diodes to speed up the switchs’ turn-off times.

The capacitors C1 and C2 represent the input gate capacitances of the power MOSFETs that served as the switches. The shoot-through issue would arise when one of those capacitances was not fully discharged before the other capacitance got raised to its own full charge. Adding two diodes sped up the capacitance discharge times so that essentially full discharge was achieved for each FET before the other one could turn on.

Having thus prevented simultaneous turn-ons, the troublesome current pulses on that circuit board were eliminated.

John Dunn is an electronics consultant, and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

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The post Shoot-through appeared first on EDN.

Professor Can Bayram and his colleagues at University of Illinois at Urbana-Champaign (UIUC) in the USA have reported diamond photoconductive semiconductor switches (PCSS) with record-breaking voltage/current handling and slew rates, efficiency and reliability simultaneously (Z. Han et al, ‘Record Performance in Intrinsic, Impurity-Free Lateral Diamond Photoconductive Semiconductor Switches’ Appl. Phys. Lett. 126, 152105 (2025)...

Проректорка з навчальної роботи Тетяна Желяскова про розбудову в КПІ якісної високотехнологічної освіти та підготовку фахівців, яких потребує сучасний ринок праці Інформація КП чт, 04/17/2025 - 13:27

Compound Semiconductor Applications (CSA) Catapult says that Dr Jayakrishnan (Jay) Chandrappan, its head of technology – advanced packaging, has been appointed visiting industrial professor at the University of Bristol and visiting professor at the University of Strathclyde...

Meta trained one of its AI models, called Llama 3, in 2024 and published the results in a widely covered paper. During a 54-day period of pre-training, Llama 3 experienced 466 job interruptions, 419 of which were unexpected. Upon further investigation, Meta learned 78% of those hiccups were caused by hardware issues such as GPU and host component failures.

Hardware issues like these don’t just cause job interruptions. They can also lead to silent data corruption (SDC), causing unwanted data loss or inaccuracies that often go undetected for extended periods.

While Meta’s pre-training interruptions were unexpected, they shouldn’t be entirely surprising. AI models like Llama 3 have massive processing demands that require colossal computing clusters. For training alone, AI workloads can require hundreds of thousands of nodes and associated GPUs working in unison for weeks or months at a time.

The intensity and scale of AI processing and switching create a tremendous amount of heat, voltage fluctuations and noise, all of which place unprecedented stress on computational hardware. The GPUs and underlying silicon can degrade more rapidly than they would under normal (or what used to be normal) conditions. Performance and reliability wane accordingly.

This is especially true for sub-5 nm process technologies, where silicon degradation and faulty behavior are observed upon manufacturing and in the field.

But what can be done about it? How can unanticipated interruptions and SDC be mitigated? And how can chip design teams ensure optimal performance and reliability as the industry pushes forward with newer, bigger AI workloads that demand even more processing capacity and scale?

Ensuring silicon reliability, availability and serviceability (RAS)

Certain AI players like Meta have established monitoring and diagnostics capabilities to improve the availability and reliability of their computing environments. But with processing demands, hardware failures and SDC issues on the rise, there is a distinct need for test and telemetry capabilities at deeper levels—all the way down to the silicon and multi-die packages within each XPU/GPU as well as the interconnects that bring them together.

The key is silicon lifecycle management (SLM) solutions that help ensure end-to-end RAS, from design and manufacturing to bring-up and in-field operation.

With better visibility, monitoring, and diagnostics at the silicon level, design teams can:

• Gain telemetry-based insights into why chips are failing or why SDC is occurring.
• Identify voltage or timing degradation, overheating, and mechanical failures in silicon components, multi-die packages, and high-speed interconnects.
• Conduct more precise thermal and power characterization for AI workloads.
• Detect, characterize, and resolve radiation, voltage noise, and mechanism failures that can lead to undetected bit flips and SDC.
• Improve silicon yield, quality, and in-field RAS.
• Implement reliability-focused techniques—like triple modular redundancy and dual core lock step—during the register-transfer level (RTL) design phase to mitigate SDC.
• Establish an accurate pre-silicon aging simulation methodology to detect sensitive or vulnerable circuits and replace them with aging-resilient circuits.
• Improve outlier detection on reliability models, which helps minimize in-field SDC.

Silicon lifecycle management (SLM) solutions help ensure end-to-end reliability, availability, and serviceability. Source: Synopsys

An SML design example

SLM IP and analytics solutions help improve silicon health and provide operational metrics at each phase of the system lifecycle. This includes environmental monitoring for understanding and optimizing silicon performance based on the operating environment of the device; structural monitoring to identify performance variations from design to in-field operation; and functional monitoring to track the health and anomalies of critical device functions.

Below are the key features and capabilities that SLM IP provides:

1. Process, voltage and temperature monitors

• Help ensure optimal operation while maximizing performance, power, and reliability.
• Highly accurate and distributed monitoring throughout the die, enabling thermal management via frequency throttling.

2. Path margin monitors

• Measure timing margin of 1000+ synthetic and functional paths (in-test and in-field).
• Enable silicon performance optimization based on actual margins.
• Automated path selection, IP insertion, and scan generation.

3. Clock and delay monitors

• Measure the delay between the edges of one or more signals.
• Check the quality of the clock duty cycle.
• Measure memory read access time tracking with built-in self-test (BIST).
• Characterize digital delay lines.

4. UCIe monitor, test and repair

• Monitor signal integrity of die-to-die UCIe lane(s).
• Generate algorithmic BIST patterns to detect interconnect fault types, including lane-to-lane crosstalk.
• Perform cumulative lane repair with redundancy allocation (upon manufacturing and in-field).

5. High-speed access and test

• Enable testing over functional interfaces (PCIe, USB and SPI).
• For in-field operation as well as wafer sort, final test, and system-level test.
• Can be used in conjunction with automated test equipment.
• Help conduct in-field remote diagnoses and lower-cost test via reduced pin count.

6. HBM external test and repair

• Comprehensive, silicon-proven DRAM stack test, repair and diagnostics engine.
• Support third-party HBM DRAM stack providers.
• Provide high-performance die to die interconnect test and repair support.
• Operate in conjunction with HBM PHY and support a range of HBM protocols and configurations.

7. SLM hierarchical subsystem

• Automated hierarchical SLM and test manageability solution for system-on-chips (SoCs).
• Automated integration and access of all IP/cores with in-system scheduling.
• Pre-validated, ready ATE patterns with pattern porting.

Silicon test and telemetry in the age of AI

With the scale and processing demands of AI devices and workloads on the rise, system reliability, silicon health and SDC issues are becoming more widespread. While there is no single solution or antidote for avoiding these issues, deeper and more comprehensive test, repair, and telemetry—at the silicon level—can help mitigate them. The ability to detect or predict in-field chip degradation is particularly valuable, enabling corrective action before sudden or catastrophic system failures occur.

Delivering end-to-end visibility through RAS, silicon test, repair, and telemetry will be increasingly important as we move toward the age of AI.

Shankar Krishnamoorthy is chief product development officer at Synopsys.

Krishna Adusumalli is R&D engineer at Synopsys.

Jyotika Athavale is architecture engineering director at Synopsys.

Yervant Zorian is chief architect at Synopsys.

Related Content

• Uncovering Silent Data Errors with AI
• 11 steps to successful hardware troubleshooting
• Self-testing in embedded systems: Hardware failure
• Understanding and combating silent data corruption
• Test solutions to confront silent data corruption in ICs

The post Addressing hardware failures and silent data corruption in AI chips appeared first on EDN.

Featuring Low 0.88 mm Profile and Wettable Flanks, Space-Saving Devices Provide Improved Thermal Performance and Efficiency

Vishay Intertechnology, Inc. introduced 27 standard and Trench MOS Barrier Schottky (TMBS) surface-mount rectifiers in the low profile DFN33A package with wettable flanks. Providing space-saving, high efficiency solutions for commercial, industrial, telecom, and automotive applications, the standard devices are the industry’s first in this package size and provide current ratings up to 6 A, while the TMBS devices deliver industry-best current ratings up to 9 A. Offering a wide range of voltage options from 60 V to 200 V for TMBS and up to 600 V for standard rectifiers, the devices are available in Automotive Grade, AEC-Q101 qualified versions.

The latest package in Vishay’s Power DFN family, the DFN33A features a compact 3.3 mm by 3.3 mm footprint and an extremely low typical height of 0.88 mm, allowing the Vishay General Semiconductor rectifiers released today to make more efficient use of PCB space. Compared to the conventional SMB (DO-214AA) and eSMP series SMPA (DO-220AA), the package’s size is 44 % and 20 % smaller, respectively. In addition, the device’s low profile is 2.6x thinner than the SMB (DO-214AA) and SMC, and 7 % thinner than the SMPA (DO-220AA). At the same time, the rectifiers’ optimized copper mass design and advanced die placement technology allow for superior thermal performance that enables operation at higher current ratings.

The devices are intended for low voltage, high frequency inverters, DC/DC converters, freewheeling diodes, and polarity and rail to rail protection in hot swap circuits for baseband antennas and power over Ethernet (PoE) for switches, routers, and optical network equipment. For these applications, the rectifiers offer high temperature operation up to +175 °C, while their exceptionally low forward voltage drop and low leakage current enhance design efficiency. The wettable flanks of their DFN33A package allow for automatic optical inspection, eliminating the need for an X-ray inspection.

Ideal for automated placement, the rectifiers offer an MSL moisture sensitivity level of 1, per J-STD-020, LF maximum peak of 260 °C. The devices are RoHS-compliant and halogen-free, and their matte tin-plated leads meet the JESD 201 class 2 whisker test.

The post Vishay Intertechnology 600 V Standard and 60 V to 200 V TMBS Rectifiers Deliver High Current Ratings to 9 A in DFN33A Package appeared first on ELE Times.

submitted by /u/knw_a-z_0-9_a-z [link] [comments]

Polar Semiconductor of Bloomington, MN, USA (the only US-owned merchant foundry specializing in sensor, power and high-voltage semiconductors) has finalized a strategic agreement with Renesas Electronics Corp of Tokyo, Japan to license its gallium nitride-on-silicon (GaN-on-Si) D-mode technology...

The SEMI Silicon Photonics Industry Alliance (SiPhIA) has held the ‘Bridging Light & Silicon: SEMI SiPhIA SIGs Kick-off & Seminar’, announcing the official launch of three Special Interest Groups (SIGs) aimed at integrating expertise from various sectors to formulate industry standards and accelerate technological innovation and commercialization. K.C. Hsu, vice president of TSMC, and Dr C.P. Hung, vice president of ASE, attended as co-chairs of SEMI SiPhIA and delivered speeches to guide the SIGs. The seminar gathered over 200 industry leaders and experts to discuss the development of silicon photonics technology and the layout of the global supply chain...

This was a project that I worked on a couple months ago that was really fun and cool, I followed it on YouTube if you look up adhd engineer. (Black was the first version) submitted by /u/counterstrikenewbie [link] [comments]

submitted by /u/White_Septendecim [link] [comments]

Tachometry, the measurement of the speed of spin of rotating objects, is a common application. Some of those objects, however, have quirky aspects that make them extra interesting, even scary. One such category includes outdoor noncontact sensing of large, fast, and potentially hazardous objects like windmills, waterwheels, and aircraft propellers. The tachometer peripheral illustrated in Figure 1 implements optical sensing using available ambient light that provides a logic-level signal to a microcontroller digital input and is easily adaptable to different light levels and mechanical contexts.

Figure 1 Logarithmic contrast detection accommodates several decades of variability in available illumination.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Safe sensing of large rotating objects is best done from a safe (large) distance and passive available-light optical methods are the obvious solution. Unless elaborate lens systems are used in front of the detector, the optical signal is apt to have a relatively low-amplitude due to the tendency of the rotating object (propeller blade, etc.) to fill only a small fraction of the field of view of simple detectors. This tachometer (Figure 1) makes do with an uncomplicated detector (phototransistor Q1 with a simple light shield) by following the detector with a high-gain, AC coupled, logarithmic, threshold detector.

Q1’s photocurrent produces a signal across Q2 and Q3 that varies by ~500 µV pp for every 1% change in incident light intensity that’s roughly (e.g. neglecting various tempcos) given by:

V ~ 0.12 log10(Iq1/Io)
Io ~ 10 fA

This approximate log relationship works over a range of nanoamps to milliamps of photocurrent and is therefore able to provide reliable circuit operation despite several orders of magnitude variation in available light intensity. A1 and the surrounding discrete components comprise high gain (80 dB) amplification that presents a 5-Vpp square-wave to the attached microcontroller DIO pin.

Programming of the I/O pin internal logic for pulse counting allows a simple software routine to divide the accumulated count by the associated time interval and by the number of counted optical features of the rotating object (e.g., number of blades on the propeller) to produce an accurate RPM reading.

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

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The post Photo tachometer sensor accommodates ambient light appeared first on EDN.

Gallium nitride (GaN) power IC and silicon carbide (SiC) technology firm Navitas Semiconductor Corp of Torrance, CA, USA has announced that its high-power GaNSafe ICs have achieved automotive qualification for both AEC-Q100 and AEC-Q101, showcasing GaN’s next inflection into the automotive market, it is reckoned...

The market for electric vehicles continues to gather pace with a strong volume growth of both battery electric vehicles and plug-in hybrid electric vehicles. The share of electric vehicles produced is expected to see double-digit growth by 2030 with a share of around 45 percent compared to 20 percent in 2024. Infineon Technologies AG is responding to the growing demand for high-voltage automotive IGBT chips by launching a new generation of products. Among these offerings are the EDT3 (Electric Drive Train, 3rd generation) chips, designed for 400 V and 800 V systems, and the RC-IGBT chips, tailored specifically for 800 V systems. These devices enhance the performance of electric drivetrain systems, making them particularly suitable for automotive applications.

The EDT3 and RC-IGBT bare dies have been engineered to deliver high-quality and reliable performance, empowering customers to create custom power modules. The new generation EDT3 represents a significant advancement over the EDT2, achieving up to 20 percent lower total losses at high loads while maintaining efficiency at low loads. This achievement is due to optimizations that minimize chip losses and increase the maximum junction temperature, balancing high-load performance and low-load efficiency. As a result, electric vehicles using EDT3 chips achieve an extended range and reduce energy consumption, providing a more sustainable and cost-effective driving experience.

“Infineon, as a leading provider of IGBT technology, is committed to delivering outstanding performance and reliability”, says Robert Hermann, Vice President for Automotive High Voltage Chips and Discretes at Infineon Technologies. “Leveraging our steadfast dedication to innovation and decarbonization, our EDT3 solution enables our customers to attain ideal results in their applications.”

The EDT3 chipsets, which are available in 750 V and 1200 V classes, deliver high output current, making them well-suited for main inverter applications in a diverse range of electric vehicles, including battery electric vehicles, plug-in hybrid electric vehicles, and range-extended electric vehicles. Their reduced chip size and optimized design facilitate the creation of smaller modules, consequently leading to lower overall system costs. Moreover, with a maximum virtual junction temperature of 185°C and a maximum collector-emitter voltage rating of up to 750 V and 1200 V, these devices are well-suited for high-performance applications, enabling automakers to design more efficient and reliable powertrains that can help extend driving range and reduce emissions.

“Infineon, as Leadrive’s primary IGBT chip supplier and partner, consistently provides us with innovative solutions that deliver system-level benefits,” said Dr. Ing. Jie Shen, Founder and General Manager of Leadrive. “The latest EDT3 chips have optimized losses and loss distribution, support higher operating temperatures, and offer multiple metallization options. These features not only reduce the silicon area per ampere, but also accelerate the adoption of advanced packaging technologies.”

The 1200 V RC-IGBT elevates performance by integrating IGBT and diode functions on a single die, delivering an even higher current density compared to separate IGBT and diode chipset solutions. This advancement translates into a system cost benefit, attributed to the increased current density, scalable chip size, and reduced assembly effort.

Infineon’s latest EDT3 IGBT chip technology is now integrated into the HybridPACK Drive G2 automotive power module, delivering enhanced performance and capabilities across the module portfolio. This module offers a power range of up to 250 kW within the 750 V and 1200 V classes, enhanced ease of use, and new features such as an integration option for next-generation phase current sensors and on-chip temperature sensing, contributing to system cost improvements.

All chip devices are offered with customized chip layouts, including on-chip temperature and current sensors.

The post Infineon introduces new generation of powerful and energy- efficient IGBT and RC-IGBT devices for electric vehicles appeared first on ELE Times.

Made a full adder with CSD15380F3 N channel FETs and 0402 resistors. I probably won't actually get it made. submitted by /u/Ok_Arachnid2186 [link] [comments]

Power semiconductor product supplier Diodes Inc of Plano, TX, USA has expanded its silicon carbide (SiC) product portfolio with a series of five high-performance, low figure-of-merit (FOM) 650V SiC Schottky diodes. Rated at 4A, 6A, 8A, 10A and 12A, the DSCxxA065LP series is housed in the ultra-thermally efficient T-DFN8080-4 package and is designed for high-efficiency power switching applications, such as DC-to-DC and AC-to-DC conversion, renewable energy, data centers (especially those that process heavy artificial intelligence (AI) workloads), and industrial motor drives...

NUBURU Inc of Centennial, CO, USA — which was founded in 2015 and develops and manufactures high-power industrial blue lasers — is to provide a comprehensive update to its shareholders regarding its newly formulated business model canvas, which encompasses two synergistic key business lines...

Microcontrollers (MCUs) have undergone a remarkable transformation, evolving from basic controllers into specialized processing units capable of handling increasingly complex tasks. Once confined to simple command execution, they now support diverse functions that require rapid decision-making, heightened security, and low-power operation.

Their role has expanded across industries, from managing complex control systems in industrial automation to supporting safety-critical vehicle applications and power-efficient operations in connected devices.

As MCUs take on greater workloads, the conventional bus-based interconnects that once sufficed now limit performance and scalability. Adding artificial intelligence (AI) accelerators, machine learning technology, reconfigurable logic, and secure processing elements demands a more advanced on-chip communication infrastructure.

To meet these needs, designers are adopting network-on-chip (NoC) architectures, which provide a structured approach to data movement, alleviating congestion and optimizing power efficiency. Compared to traditional crossbar-based interconnects, NoCs reduce routing congestion through packetization and serialization, enabling more efficient data flow while reducing wire count.

This is how efficient packetization works in network-on-chip (NoC) communications. Source: Arteris

MCU vendors adopt NoC interconnect

Many MCU vendors relied on proprietary interconnect solutions for years, evolving from basic crossbars to custom in-house NoC implementations. However, increasing design complexity encompassing AI/ML integration, security requirements, and real-time processing has made these solutions costly and challenging to maintain.

Moreover, as advanced packaging techniques and die-to-die interconnects become more common, maintaining in-house interconnects has grown increasingly complex, requiring constant updates for new communication protocols and power management strategies.

To address these challenges, many vendors are transitioning to commercial NoC solutions that offer pre-validated scalability and significantly reduce development overhead. For an engineer designing an AI-driven MCU, an NoC’s ability to streamline communication between accelerators and memory can dramatically impact system efficiency.

Another major driver of this transition is power efficiency. Unlike general-purpose systems-on-chip (SoCs), many MCUs must function within strict power constraints. Advanced NoC architectures enable fine-grained power control through power domain partitioning, clock gating, and dynamic voltage and frequency scaling (DVFS), optimizing energy use while maintaining real-time processing capabilities.

Optimizing performance with NoC architectures

The growing number of heterogeneous processing elements has placed unprecedented demands on interconnect architectures. NoC technology addresses these challenges by offering a scalable, high-performance alternative that reduces routing congestion, optimizes power consumption, and enhances data flow management. NoC enables efficient packetized communication, minimizes wire count, and simplifies integration with diverse processing cores, making it well-suited for today’s MCU requirements.

By structuring data movement efficiently, NoCs eliminate interconnect bottlenecks, improving responsiveness and reducing die area. So, the NoC-based designs achieve up to 30% higher bandwidth efficiency than traditional bus-based architectures, improving overall performance in real-time systems. This enables MCU designers to achieve higher bandwidth efficiency and simplify integration, ensuring their architectures remain adaptable for advanced applications in automotive, industrial, and enterprise computing markets.

Beyond enhancing interconnect efficiency, NoC architectures support multiple topologies, such as mesh and tree configurations, to ensure low-latency communication across specialized processing cores. Their scalable design optimizes interconnect density while minimizing congestion, allowing MCUs to handle increasingly complex workloads. NoCs also improve power efficiency through modularity, dynamic bandwidth allocation, and serialization techniques that reduce wire count.

By implementing advanced serialization, NoC architectures can reduce the number of interconnect wires by nearly 50%, as shown in the above figure, lowering overall die area and reducing power consumption without sacrificing performance. These capabilities enable MCUs to sustain high performance while balancing power constraints and minimizing die area, making NoC solutions essential for next-generation designs requiring real-time processing and efficient data flow.

In addition to improving scalability, NoCs enhance safety with features that help toward achieving ISO 26262 and IEC 61508 compliance. They provide deterministic communication, automated bandwidth and latency adjustments, and built-in deadlock avoidance mechanisms. This reduces the need for extensive manual configuration while ensuring reliable data flow in safety-critical applications.

Interconnects for next-generation MCUs

As MCU workloads grow in complexity, NoC architectures have become essential for managing high-bandwidth, real-time automation, and AI inference-driven applications. Beyond improving data transfer efficiency, NoCs address power management, deterministic communication, and compliance with functional safety standards, making them a crucial component in next-generation MCUs.

To meet increasing integration demands, ranging from AI acceleration to stringent power and reliability constraints, MCU vendors are shifting toward commercial NoC solutions that streamline system design. Automated pipelining, congestion-aware routing, and configurable interconnect frameworks are now key to reducing design complexity while ensuring scalability and long-term adaptability.

Today’s NoC architectures optimize timing closure, minimize wire count, and reduce die area while supporting high-bandwidth, low-latency communication. These NoCs offer a flexible approach, ensuring that next-generation architectures can efficiently handle new workloads and comply with evolving industry standards.

Andy Nightingale, VP of product management and marketing at Arteris, has over 37 years of experience in the high-tech industry, including 23 years in various engineering and product management positions at Arm.

 

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• Network-on-chip (NoC) interconnect topologies explained

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India is accelerating its semiconductor ambitions, aiming to secure 10% of global chip demand by 2030. Central to this strategy is the India Semiconductor Mission (ISM), launched in December 2022 with an allocation of ₹76,000 crore, designed to foster a sustainable semiconductor ecosystem and reduce reliance on imports.

In a significant development, Tata Electronics and Taiwan’s PSMC have announced a joint venture to establish India’s first 12-inch wafer fabrication facility in Dholera, Gujarat. With an investment of $11 billion, this project is expected to generate over 20,000 jobs and focus on manufacturing power management ICs, display driver ICs, microcontrollers, and high-performance computing logic components.

The 2025 budget reflects the government’s commitment, doubling the allocation for chip initiatives to ₹2,499.96 crore for FY26. This includes increased funding for compound semiconductors, sensors, and chip assembly/testing units, with a 56% rise to ₹3,900 crore, and nearly doubling the allocation for the design-linked incentive (DLI) to ₹200 crore.

Strategic partnerships with countries like Singapore, the US, Japan, and Taiwan are also being pursued to enhance technology transfer, skill development, and foreign direct investment. These efforts position India as a key player in the global semiconductor supply chain, aligning with the ‘China Plus One’ strategy amid evolving geopolitical dynamics.

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