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Applications in the AI era are memory starved. They need more capacity and, in many cases, more effective memory bandwidth than traditional server designs. Generative AI and large language models (LLMs) store trillions of parameters that must be accessed frequently. And real-time inference for translation, chatbots, and similar services demands low-latency memory paths.

Larger memory footprints enable bigger batch sizes, improving training and inference efficiency. However, while the fastest memory sits on die—in CPU caches—capacity there is inherently limited. For decades, systems have relied on double data rate (DDR) interfaces for high-capacity, relatively low-latency off-chip memory.

Adding more DDR to a CPU, however, runs into hard limits: each interface consumes scarce I/O pins (288 pins on modern DDR4/DDR5 modules), demands strict signal integrity at ever-higher data rates, and carries significant cost. An alternative that has gained real traction is Compute Express Link (CXL) Type 3 memory expanders—devices that attach over a CXL link and present additional system memory to the host.

CXL is a cache-coherent interconnect that lets a CPU access device-resident resources with semantics closer to memory than traditional PCI Express (PCIe) peripherals. A Type 3 memory expander exposes DRAM (and, in some designs, other media) as byte-addressable memory that firmware and the operating system can map and allocate like conventional RAM—after discovery, decode programming, and policy setup.

The critical implication for bring-up and validation is that this memory is logically host-visible yet physically and administratively distinct from local dual inline memory modules (DIMMs). That distinction affects discovery, non-uniform memory access (NUMA) topology, performance, and error-handling paths through firmware and the OS.

Figure 1 The memory-latency pyramid describes relative ordering and validation implications. Source: arXiv

The memory latency–capacity pyramid

System memory is best understood as a latency–capacity pyramid. Small, fast, most expensive structures—CPU caches—sit at the top. Larger, slower, progressively cheaper tiers sit below; local DRAM, then expansion memory, and then I/O-backed storage. Absolute nanoseconds vary by CPU generation, CXL version, link width, topology (direct attach versus retimer or switch), firmware tuning, and contention; the pyramid describes relative ordering and validation implications, not a single fixed latency table.

Local DDR, typically attached near the CPU socket, offers the lowest DRAM access times the OS sees for general-purpose allocation. CXL Type 3 expander memory is DRAM-class and byte-addressable from software’s perspective, but it’s reached across a CXL fabric hop (often with additional buffering and coherency handling).

It therefore sits below local DDR—higher average and tail latency, sometimes behaving like “far memory” in NUMA terms. In other words, imaging CPU 0 accessing DDR memory is attached to CPU 1 in the system, as shown in Figure 2.

Figure 2 Here is a typical two-socket system with a CXL memory expander device attached to CPU 0 via a Gen5, x16 CXL bus. Source: Author

For bring-up, that placement matters as correctness tests may pass while performance and quality-of-service (QoS) tests fail. Workloads with pointer chasing, fine-grained random access, or strict tail-latency budgets are the first to expose suboptimal placement, interleaving, or contention.

Storage and networked memory (NVMe, RDMA, and similar) form the broad base of the pyramid with much higher latency and usually block or page semantics. CXL memory is not in the same tier as SSDs, but it’s meaningfully different from local DIMMs for latency-sensitive software. On a typical two-socket system, the access latency of DDR behind a CXL device can be comparable to accessing DDR attached to the adjacent CPU—a useful mental model when setting performance expectations.

Platform prerequisites: A cross-layer contract

Whether CXL Type 3 memory becomes reliably visible, addressable, and serviceable depends on aligned support across the stack: CPU CXL capability and enablement; system BIOS/firmware support for discovery, decode, and ACPI tables; kernel CXL enumeration and memory management; and expander device firmware for DRAM training, HDM reporting, and mailbox/DOE services. All layers must agree.

Consider CXL Integrity and Data Encryption (IDE); it requires CPU support, BIOS enablement, and device firmware support to be usable end to end. Similarly, the kernel needs a CXL-aware path to recognize the device class, bind memory resources, and transition capacity to an online state the allocator can use.

Reliability, availability, and serviceability (RAS) matter equally. Corrected and uncorrected error notifications must propagate from hardware through firmware to OS subsystems that can log, isolate, or offline affected regions. Because behaviors evolve quickly across kernel releases, validation plans should treat OS version, configuration (huge pages, numactl policies, memory mode), and boot/firmware settings as explicit test variables. Failures are often misattributed to the expander when the root cause is a policy or enablement gap.

Host-managed expander memory generally relies on the in-kernel CXL/memory management stack rather than a monolithic device-specific driver, though platform integrations may include monitoring agents, telemetry exporters, or hardware management interfaces that affect how engineers observe link state, temperature, power, and error counters during bring-up.

Linux and the NUMA story

On Linux, a Type 3 memory expander normally appears as a PCI/CXL function. In upstream kernels with CXL support enabled, the in-tree cxl_pci module is the default bind target. A stock Type 3 host-managed device (HDM) endpoint typically comes up under cxl_pci rather than a vendor-specific host driver for basic enumeration.

The cxl_pci module is PCI-facing glue: it attaches to the device, brings up CXL.io access (including the configuration mailbox), and registers the endpoint with the CXL core so the rest of the stack can expose memory devices to the OS.

In a NUMA machine, the operating system groups CPUs and memory into nodes and treats local memory as cheaper than remote memory. DRAM next to a socket is usually the lowest-latency memory for CPUs in that socket, so the scheduler and allocator try to keep threads and pages on nearby nodes (subject to policy).

CXL Type 3 expander memory is still host-coherent and byte-addressable, but it’s physically and topologically distinct from local DIMMs. Platforms and operating systems therefore commonly expose expander memory ranges as a distinct NUMA node, or as memory with different affinity and distance metadata in ACPI proximity hints. The same application binary can run correctly while performance changes sharply depending on where pages are allocated and whether threads migrate across sockets.

For CXL bring-up and validation, the NUMA story is central. Issues often appear as unexpected remote access or imbalanced bandwidth rather than hard functional failures. Engineers must verify not only that memory is online, but that placement and distance metadata match the intended system topology.

What comes next

Part 2 of this series introduces the user-space tooling ecosystem—cxl/libcxl, ndctl, daxctl, numactl, and topology helpers—and traces the full boot sequence from slot power and DRAM training through DVSEC discovery, decode programming, CDAT delivery, ACPI table handoff, and OS driver binding. Part 3 turns to practical test and debug: interpreting lspci output, validating HDM ranges, exercising CXL-attached memory with numactl, and selecting bandwidth and stress tools for validation gates.

Together, these three parts provide a vendor-neutral, OS-focused playbook for engineers, bringing CXL Type 3 memory expanders from first power-on to production-ready validation.

Ameet Sanghavi works in post-silicon validation for PCIe and CXL at Nvidia with a focus on interface bring-up and validation on shipping products. He has worked on PCIe since 2005 (from PCIe 1.1 onward) and on CXL since 2020 (from CXL 1.1 onward).

Editor’s Note

This is Part 1 of the mini-series on CXL Type 3 memory technology. Part 2 of this series introduces the user-space tooling ecosystem. And Part 3 turns to practical test and debug work.

The views and content of the article are the author’s own and not affiliated to any of his current or previous employers.

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The post Why CXL Type 3 memory matters, what your platform must provide appeared first on EDN.

Converting frequency signals to loop current signals creates an economical result for process industry applications.

Process industry applications commonly employ multiple motors. Their speeds are monitored by tachometers using magnetic pickups from gear wheels mounted on the motors’ shafts. The tachometers produce pulses whose frequencies are proportional to their speeds. Local displays of speeds is generally done by counter/timer-based LEDs or LCDs.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Special modules incorporating expensive counter/timers find use for recording these speeds in control room-based programmable logic controllers (PLCs) and more complex distributed control systems (DCSs). Shielded cables are necessary to carry these pulse signals to the control room, as the signals may induce noise in adjoining cables carrying conventional analog signals. Such an approach is expensive. A more economical alternative solution would be to convert each frequency signal to a 4-20 mA  loop current signal and then transport it to the control room using less expensive cables like those carrying analog signals. Figure 1’s circuit does exactly this.

Figure 1 In one switch SW1 position, this circuit converts 0-50 kHz frequency signals to 4-20 mA loop current alternatives. In the other switch position, the circuit converts 0-5V into 4-20 mA loop current.

The frequency to voltage conversion circuit discussed here is based on an industry-standard LM2907 IC. This chip is extensively used in automotive applications and hence is easily available and inexpensive. It needs only three components to set the basic relationship between frequency and voltage. It uses a charge pump circuit to convert frequency to voltage.

• V output = Vcc*F*R*C (In Figure 1’s circuit, R=R5, C=C4)
• U2 is wired to give a 12 V output, which is fed to the circuit. F is pulse frequency.
• With Vcc as 12V and substituting the component values shown in the circuit, the voltage output works out to 0.264V/KHz.

Exact values for R5 and C4 are not necessary; approximate values are sufficient. The signal is amplified by U1B so that a voltage relationship of 1V/KHz is obtained by tuning potentiometer RV1. C5 filters ripples; increasing its value filters ripples more effectively but also increases the response time. The portion of the circuit surrounding U3 converts 0 to 5KHz into 0 to 5 volts.

The remaining portion of the circuit converts 0/5V into 4/20 mA loop current. R2 determines the “zero” current of 4 mA. If an exact-value resistor is not available, R2 may be replaced with a potentiometer. R13 determines the current span value. Again, if an exact-value resistor is not available, it can be replaced with a potentiometer.

The current going through R2 plus the current going through R13 must be equal to current through R4, as these currents are at the + input of operational amplifier U1A, whose -ve input is grounded. A detailed description of a loop current converter with governing equations can be found in my earlier Design Idea “A 0-20 mA source current to 4-20 mA loop current converter”.

As a bonus, this circuit converts 0-5V into 4-20mA loop current by flipping switch SW1 to the alternative 0-5V input position. Multiple industrial sensors and transmitters generate 0-5V outputs for the parameters they monitor. This circuit may be used to comfortably connect such sensors and transmitters to PLCs and DCSs. Linearity and accuracy are primarily dictated by the LM2907 IC. A simulation study of this circuit indicates accuracy of better than +/- 5%.

Jayapal Ramalingam has over three decades of experience in designing electronics systems for power & process industries and is presently a freelance automation consultant.

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• Silly simple precision 0/20mA to 4/20mA converter
• A 0-20mA source current  to 4-20mA loop current converter

The post Tachometer frequency to 4-20mA loop current converter appeared first on EDN.

Solid-state drives (SSDs) are among the evolutionary success stories of modern computing. They replaced spinning disks, eliminated mechanical bottlenecks, and enabled the high-speed data access that today’s applications depend on. Plus, they fit into ever-smaller form factors, which we all love.

But as workloads evolve—especially with the rise of edge AI—SSDs are bumping against a critical limitation: heat.

What was once a distant consideration has become a frontline performance constraint. Today’s SSDs are faster, denser, and more heavily utilized than before. And the devices they live in—ultrabooks, tablets, gaming handhelds, and emerging AI-enabled wearables—are thinner, more compact, and often fanless. This clash of trends is creating a perfect thermal storm.

The forecast is ominous—both for consumers and system designers. SSDs will continue buckling under real-world workloads; they’ll throttle data speeds when things get hot; and users will pay the price in diminished performance.

But there must be a cooler way out.

The new reality of sustained workloads

Historically, many storage workloads—the read/write patterns of moving data—were burst-oriented. Opening files, launching applications, and saving documents created short spikes in activity, followed by idle periods that allowed components to cool. Under these conditions, passive thermal solutions such as heat spreaders, vapor chambers, and thermal pads were sufficient.

That’s no longer the case.

Modern workloads, particularly those driven by AI, are sustained and data intensive. Running local LLMs requires loading gigabytes of parameters from storage into memory. AI-powered photo and video editing tools generate continuous read/write cycles during rendering and export. Even gaming has evolved, with real-time asset streaming and procedural generation placing constant demands on storage subsystems.

They are prolonged, high-throughput operations that keep SSD controllers and NAND flash memory active for extended periods. And that changes everything.

Thermal throttling: Hidden performance killer

SSDs are designed with thermal safeguards to prevent damage. Most standard, high-speed controllers begin to throttle performance when temperatures reach approximately 70°C to 80°C. Once that threshold is crossed, the drive reduces its speed to lower heat output.

From a reliability standpoint, this is essential. From a performance standpoint, it’s detrimental. In practical terms, thermal throttling of SSDs can reduce throughput by 20% to 30% or more. A drive capable of delivering 2.0 GB/s may drop to 1.5 GB/s under sustained load. For users, this translates into longer file transfers, slower application performance, and increased latency in AI-driven tasks.

Usually, such performance degradation is unpredictable. And in edge AI applications, where consistent performance is critical, this variability can be unacceptable.

Why passive cooling is no longer enough

The root of the problem lies in the limitations of passive cooling. Passive thermal solutions are designed to spread heat away from hotspots, redistributing it across a larger surface area. This can delay temperature spikes and improve short-term performance, but it doesn’t actually remove heat from the device.

In compact, sealed systems where SSDs operate, heat accumulates over time. Without airflow to carry that heat away, temperatures inevitably rise until throttling occurs.

This challenge is exacerbated by modern device design. In many ultrathin laptops and handheld systems, SSDs are positioned near CPUs, GPUs, and other heat-generating components. The thermal environment is already saturated, leaving little headroom for additional heat dissipation.

The industry has pushed passive cooling to its limits with advanced materials and clever mechanical designs. But physics imposes a hard boundary. Without active airflow, sustained high-performance operation is not achievable.

Micro-cooling: A new approach to active thermal management

How to achieve that airflow? Traditional active cooling relies on fans. Fans move air, enabling heat transfer that effectively removes thermal energy from a system. In desktops and larger laptops, this approach works well.

But fans are not a universal solution. They take up space, generate noise, consume power, and introduce mechanical complexity. In ultra-thin devices, wearables, and sealed systems, integrating a fan is often impractical or undesirable. As a result, many edge devices are designed without active cooling, despite the increasing thermal demands placed on their components. Still, there’s a need for active cooling that fits within the constraints of modern device design.

Micro-cooling (µCooling) technology offers a new approach. Instead of miniaturizing traditional fans, µCooling uses piezoMEMS technology to generate airflow through microscopic motion inside a silicon chip. Often referred to as a “fan on a chip,” µCooling devices are fabricated using semiconductor processes, making them extremely compact, thin, and reliable.

Because they have no moving mechanical parts, µCooling devices avoid many of the drawbacks associated with conventional fans. They operate silently, consume minimal power, and can be integrated into tight spaces where traditional cooling solutions cannot fit. But most importantly, µCooling “fans” move heat out of a system and away from SSDs, something no passive cooling solution can accomplish.

What µCooling means for SSD performance

For SSDs, the introduction of µCooling is transformative. By generating localized airflow around the SSD controller and NAND components, µCooling systems can actively remove heat before it accumulates to critical levels. This helps maintain operating temperatures below throttling thresholds, even during sustained workloads.

Instead of experiencing performance degradation over time, SSDs can sustain higher throughput for longer durations. This is particularly valuable for AI workloads, where consistent data access speeds are essential. In practical terms, this means faster model loading, smoother real-time processing, and more reliable performance during extended tasks such as video rendering or large-scale data transfers.

µCooling also enables system designers to rethink thermal constraints. With active cooling available at the micro level, they can push performance boundaries without being limited by the thermal management challenges.

Enabling the future of edge AI devices

The evolution of SSDs has always been about addressing bottlenecks—first mechanical, then architectural. The next bottleneck is clearly thermal. Without addressing heat, we can’t realize the full potential of modern storage systems in edge devices. Throttling will undermine performance gains, and the user experience will suffer.

µCooling provides a path forward. By bridging the gap between passive and traditional active cooling, it enables a new class of thermal solutions tailored to the needs of modern electronics. It ensures that SSDs, a critical component of the data pipeline, don’t become a bottleneck. And that’s crucial.

As edge AI continues to proliferate, the importance of efficient thermal management will only increase. Devices are expected to do more—process more data, run more complex models, and deliver richer experiences—within smaller and more constrained form factors. Storage systems must keep pace with the demands for sustained, not just peak, performance.

Mike Housholder is VP and GM of thermal management at xMEMS.

 

 

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The post SSDs are hot: Why AI demands micro-cooling appeared first on EDN.

• DIRK (German Investor Relations Association) awards Infineon first place for best Investor Relations among DAX 40 companies
• IR Impact has honored Infineon with first-place rankings at the European level in the categories “Best Overall Investor Relations (Large Cap)” and “Best Investor Relations Officer (Large Cap)”
• Awards confirm the quality and credibility of Infineon’s capital markets communication

Infineon Technologies AG receives several awards for its Investor Relations (IR) activities. At the German Investor Relations Award presented by DIRK, the German Investor Relations Association, the Infineon IR team achieve first place for best Investor Relations among all DAX 40 companies for the first time, jointly with Siemens Energy AG. Infineon also ranked third in the categories “Best ESG Communication by a Company” and “Best IR Communication by a Head of IR”. The latter award was presented to Alexander Foltin, Head of Finance, Treasury & Investor Relations, who accepted the prize together with Chief Financial Officer Dr. Sven Schneider at the ceremony in Frankfurt on 30 June.

Just two weeks earlier, the team had already been recognized at the 2026 IR Impact Awards – Europe. Infineon’s entire IR team ranked first in the category “Best Overall Investor Relations (Large Cap).” Alexander Foltin and Daniel Györy, Team Lead Investor Relations, also jointly secured the top position in the category “Best Investor Relations Officer (Large Cap).”

“The strong recognition of Infineon’s Investor Relations work at national and international level confirms the high quality and credibility of our capital markets communication,” said Dr. Sven Schneider. “My sincere thanks go to the colleagues who continuously foster an open and transparent dialogue with our investors and analysts, particularly at a time marked by unprecedented growth opportunities and geopolitical challenges. We remain committed to shaping Infineon’s equity story, meeting the expectations of analysts and investors, and to maintaining a close and constructive exchange with the capital markets.”

The German Investor Relations Award is presented annually by Extel, WirtschaftsWoche and DIRK. The winners are determined based on Extel’s Developed Europe Executive Team Survey, which gathers independent feedback each year from thousands of buy- and sell-side professionals worldwide on the IR activities of listed companies.

The IR Impact Awards – Europe are presented annually by IR Impact and are among the most prestigious distinctions in the Investor Relations field in Europe. They recognize excellence in financial communications as well as in the dialogue between listed companies and the capital markets. Winners of the respective categories are determined by an independent survey of analysts and investors.

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The enterprise AI platform turns millions of engineering artifacts that run a plant into accurate, decision-ready data, delivering up to 85% extraction accuracy and full, audit-ready traceability

L&T Technology Services announces the launch of Ainfonix 4.0, a next-generation Engineering Intelligence platform for process industries. Unveiled at EI Live, LTTS’ flagship event that brings together analysts, industry leaders and engineering experts, Ainfonix 4.0 marks an important step in the company’s Enterprise AI and Engineering Intelligence strategy.

As industrial enterprises accelerate AI adoption, decades of engineering knowledge remain trapped in fragmented drawings, specifications, and technical records across disparate systems. Without trusted and accessible engineering data, organizations struggle to realize the full value of AI, automation, and digital transformation initiatives.

Ainfonix 4.0, developed in LTTS’ Sustainability segment, addresses this challenge by transforming engineering artifacts and multi-modal data into structured, asset-linked information that can be governed, searched and reused across the enterprise for faster and better decision-making. Built on decades of process industry expertise, the platform combines AI-powered extraction, engineering intelligence and human-in-the-loop validation to improve data quality, strengthen traceability and create a trusted foundation for engineering execution, operational visibility, and lifecycle performance. In early deployments, Ainfonix 4.0 has delivered up to 85% accuracy in technical data extraction, 30-50% faster artifact retrieval and review, and 100% audit-ready traceability, helping enterprises operate with greater speed, reliability, and control. LTTS was recently rated as a Leader in the ISG Provider Lens 2025 study for Enterprise Asset Management in the Oil & Gas Industry Service & Solutions (Americas).

Amit Chadha, CEO & Managing Director, L&T Technology Services, said, “Engineering Intelligence begins with trusted engineering data. While enterprises invest heavily in digitization, much of the engineering knowledge remains locked within disconnected engineering systems. Ainfonix 4.0 helps bridge that gap by transforming engineering information into structured, asset-linked intelligence that can be used across the asset lifecycle, from engineering and project execution to operations and maintenance. As organizations look to scale AI adoption, we believe trusted engineering data will become a critical competitive advantage, and Ainfonix 4.0 is designed to help clients unlock that value.”

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• Advance single-die solution with PQC (post-quantum cryptography) hardware accelerator
• Helps mobile device makers prepare for future security requirements while enabling rich consumer and ecosystem use cases.

STMicroelectronics introduces the ST54M, a secure mobile chip designed to help smartphone and personal electronics manufacturers meet upcoming quantum-ready security requirements while supporting a seamless user experience across connected services.

ST54M brings to the market a single-die device featuring an innovative hardware accelerator for post-quantum cryptography (PQC) with NFC, secure element and eSIM functionality, delivering a powerful future-ready solution for secure mobile connectivity and services. The solution supports a wide range of use cases, including contactless payments, transit ticketing, access control, digital identity, driving licenses, connectivity services, and digital car keys.

Future-proof protection for expanding mobile use cases

As mobile devices increasingly serve as trusted platforms for financial transactions, identity credentials, operator services, and secure access, product developers need solutions that combine multiple functions without compromising security, performance, or convenience. ST54M addresses this need by enabling OEMs and ecosystem partners to support multiple applications on one platform while preparing for the transition toward PQC.

The device is designed for use across personal electronics ecosystems involving mobile network operators, banks, governments, transit operators, car manufacturers, digital-wallet and service providers. It helps manufacturers create devices that maintain a stable, familiar user experience while meeting stronger long-term security expectations.

Arriving now, ST54M enables customers and partners to deliver post-quantum-ready implementations with enough time to meet demanding industry-driven market deployment requirements, which are expected to be mandated around 2030.

“With ST54M, we are extending our mobile-convergence platform to help customers address evolving security challenges while supporting the rich set of services users now expect from their devices,” said David Richetto, Connected Security Group VP, Division General Manager, STMicroelectronics. “By combining a PQC hardware accelerator with NFC, embedded secure element, and embedded SIM capabilities, ST54M gives device makers a secure path to start preparing next-generation mobile experiences.”

Engineered for security, integration, and RF performance

ST54M is an advanced single-die solution that integrates an NFC controller with a secure element supporting secure applications, eSIM, and NFC-compliant products. A key feature is its hardware accelerator for post-quantum cryptography algorithms, including ML-KEM and ML-DSA, supporting the transition from hybrid cryptographic approaches toward full post-quantum deployment. The hardware engine is designed to address emerging PQC requirements while helping protect against side-channel and fault-injection attacks and is the latest result from ST’s long-term commitment that also includes certified software libraries NesLib-PQML and X-CUBE-PQC in STM32 microcontrollers.

In addition to its security architecture, the device integrates a large memory capacity to support multiple applications and includes an enhanced RF front end. These capabilities can help improve performance with smaller antennas and single-ended configurations, support more stable reader-writer operation, and enable demanding use cases such as mobile Point-of-Sale (mPOS) and wireless charging. The platform has completed certification testing under Common Criteria 2022 EUCC and EMVCo, underscoring its suitability for security-sensitive mobile applications.

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Featuring AI-powered noise reduction, real-time audio transmission, compact lightweight design, Type-C connectivity, and seamless audio-video synchronisation for content creators

Portronics launches the VlogMate Neo, an AI-powered Type-C wireless microphone designed to help creators capture crystal-clear audio with ease. Built for vloggers, influencers, podcasters, educators, and mobile content creators, the VlogMate Neo combines intelligent audio processing with a compact, lightweight design to deliver professional-grade sound on the go.

Built for modern content creation needs, the VlogMate Neo features a dual-microphone system with AI-powered noise reduction, enabling it to effectively isolate voices while minimising unwanted background noise for consistently clear and natural audio across diverse environments. It also offers seamless plug-and-play functionality with Type-C smartphones, eliminating the need for additional apps or complex pairing processes.

Its lightweight and discreet form factor ensures comfortable wear during extended recording sessions, making it ideal for on-the-go creators. With real-time wireless audio transmission, the device delivers stable, low-latency performance for smooth and uninterrupted recording.

The VlogMate Neo supports audio-video synchronisation, ensuring perfectly aligned output for polished, professional-quality content. With a wireless range of up to 30 meters, creators can move freely while filming travel vlogs, fitness tutorials, interviews, presentations, and outdoor shoots without compromising audio quality.

Adding to its versatility, the microphone comes with a removable magnetic clip for quick attachment and flexible positioning. The included charging case protects the device and extends battery life, making it suitable for long recording sessions across multiple locations. Compatible with Type-C smartphones and devices, the VlogMate Neo offers true plug-and-play functionality, allowing users to start recording instantly without additional apps or complex setup procedures.

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Part 1 of this mini-series on advanced packaging outlined the basic comparison between CoWoS, wafer-scale integration, and CoWoP. It established why the package substrate, silicon wafer, and platform PCB represent different settings for future AI system bottlenecks.

Part 2 continues with the advanced CoWoP concept: pitch translation, transition patches, VRM and memory placement, Universal Chiplet Interconnect Express (UCIe) routing, and trusted realization governance.

The most challenging CoWoP part is not only whether the package substrate can be reduced or removed. The harder question is whether the architecture can physically transition from silicon-interposer pitch to platform-PCB pitch.

A wafer-level interposer, silicon bridge, or advanced redistribution structure operates in a fine-pitch environment. Micro-bumps, hybrid bonding, and high-density redistribution can exist in the tens-of-microns range. A platform PCB, even an advanced HDI board, operates at a much larger manufacturing scale, closer to hundreds of microns for practical solderable attach and board-level assembly.

This creates a major geometric discontinuity:

• Interposer/wafer-level interface: roughly tens of microns
• Platform-PCB attach interface: roughly hundreds of microns

Trying to force the primary interposer to absorb this entire fan-out directly would consume expensive interposer area, increase routing complexity, reduce yield, and weaken the economic argument for CoWoP. Therefore, the more practical CoWoP architecture may require an intermediate transition structure.

• Die/HBM → wafer-level interposer → transition redistribution patch → platform PCB

This patch is not simply another conventional package substrate. It’s a localized pitch-translation and CTE-management layer. Its role is to convert the silicon/interposer interface into a PCB-compatible attach interface while preserving electrical, mechanical, and thermal continuity.

A useful name for this structure is interposer-to-PCB transition patch, or more specifically, pitch-transition redistribution patch. This transition patch becomes the governed bridge between wafer-level precision and platform-level manufacturability.

Glass as a local transition patch

One possible implementation is a thin glass-core transition patch. A 2-3-layer glass-based transition patch could provide dimensional stability, CTE compatibility with the silicon/interposer side, and a controlled vertical path through TGVs. In this use case, glass is not being treated as a full package substrate replacement; it’s being used as a local transition bridge between wafer-level precision and board-level attach.

The concept is similar in spirit to wafer-to-package redistribution: expand the pitch in controlled stages rather than forcing one layer to absorb the entire geometric transformation. The transition could look like this in silicon die/HBM:

• Micro-bumps or hybrid bonding at fine pitch
• Primary wafer-level interposer
• First-stage redistribution
• Glass-core transition patch with TGVs
• Second-stage fan-out toward PCB pitch
• Platform PCB

The value of the glass patch is that it may preserve the CTE and dimensional-stability advantages near the interposer while providing a more manufacturable path toward the PCB. This matters because the hardest interface may not be the PCB alone or the interposer alone. It may be the transition between the two.

A glass transition patch can potentially help with:

• Fine-pitch registration
• CTE continuity near the silicon/interposer side
• Controlled vertical fan-out through TGVs
• Reduced interposer area devoted only to fan-out
• More stable pad alignment across thermal cycling
• A shorter vertical PDN path toward the platform PCB

But the glass patch also introduces its own realization needs:

• TGV reliability
• Glass/copper stress
• Attach fatigue
• Inspection accuracy
• Edge cracking
• Lifecycle drift

In other words, glass can make the transition more governable.

Organic as a compliant transition patch

Another possible implementation is a high-density organic transition patch. An organic patch may not match the dimensional stability of glass, but it may provide mechanical compliance. That compliance could help absorb shear stress between a rigid silicon/interposer structure and a larger platform PCB that expands, warps, and bends differently under thermal and mechanical loading.

This creates an important trade-off. A glass transition patch may offer stronger dimensional stability, stronger CTE matching to silicon/interposer, better fine-pitch registration, and a stronger TGV-based vertical transition. An organic transition patch may offer better mechanical compliance, more familiar substrate processing, and potentially better stress absorption between rigid silicon and PCB.

This trade-off is exactly why CoWoP should be treated as a governed realization problem, not only a layout concept. The transition patch becomes a decision point. The best material may depend on system size, thermal cycling, pitch requirements, power density, board stiffness, rework needs, reliability targets, and cost.

CoWoP as an interposer-to-patch-to-PCB corridor

With the transition-patch concept included, CoWoP becomes technically more credible. The architecture is not simply interposer directly attached to PCB, as shown below.

Interposer → controlled transition patch → platform PCB

It means CoWoP is not only a substrate-removal concept. It’s a pitch-transition, CTE-governance, and system-integration concept. The package substrate may be reduced, localized, or re-architected, but the realization burden does not disappear. It moves into a new corridor where the interposer-to-transition patch-to-platform PCB corridor must govern:

• Pitch translation
• Pad registration
• TGV or via integrity
• CTE continuity
• Attach fatigue
• Return-path continuity
• PDN impedance
• Decoupling location
• Thermal spreading
• Inspection and test
• Lifecycle reliability

Why CoWoP may be attractive for VRM placement

One of the strongest opportunities is power delivery. In advanced AI packages, the VRM is often physically far from the die. The power-delivery path must travel through the PCB, package substrate, interposer, bumps, and on-die distribution. This creates loop inductance, PDN impedance challenges, transient-response limitations, dI/dt sensitivity, resonance concerns, and pressure to place decoupling capacitance closer to the load.

Moving active power components onto the interposer or package may reduce distance, but it introduces other risks:

• Thermal density
• Active-component integration complexity
• Manufacturing risks
• Repairability concerns
• Reliability uncertainty

CoWoP may offer a more practical middle path. The VRM can remain on the PCB, where active power components are more manufacturable, serviceable, thermally manageable, and familiar to the design ecosystem. At the same time, however, the vertical corridor from platform PCB to transition patch to interposer may become shorter and more direct than the conventional package-substrate path.

So, the value is not that the VRM is placed on interposer; the value is that the VRM can stay on the PCB while the power corridor to the interposer becomes shorter, more controlled, and potentially lower inductance. That may reduce part of the package-dominated loop inductance and improve the power-delivery architecture without forcing active VRM components into the interposer itself.

This creates a new chiplet power architecture opportunity: PCB-side VRM, transition-patch power delivery, lower package burden, and governed PDN evidence. But the power problem is not solved automatically. The transition patch must preserve current return paths, minimize spreading inductance, support decoupling strategy, avoid PDN anti-resonance, and remain reliable under thermal cycling.

In short, while the corridor is shorter, it still must be governed.

Why CoWoP may be attractive for DDR and LPDDR

Memory is another important area. HBM will remain critical for high-bandwidth AI accelerators, but not every memory requirement should necessarily move onto the package. DDR and LPDDR placed on package can create manufacturing, warpage, thermal, test, yield, and reliability concerns.

So, memory on the PCB remains attractive because it’s more familiar, more serviceable, and more compatible with established board-level manufacturing. The problem is distance and signal quality.

In a conventional architecture, the memory path may be:

Die → interposer → package substrate → PCB → DDR/LPDDR with CoWoP

The path may become closer to:

Die → interposer / wafer-level routing → transition patch → platform PCB → DDR/LPDDR

This does not make PCB memory identical to on-package memory. However, it may improve the compromise: memory can remain on the PCB while the routing path becomes shorter, more direct, and potentially more controllable than the conventional package-to-board path.

That is a meaningful system architecture advantage. It may also reduce pressure to place every useful memory element inside the package, which can help with manufacturability, reliability, thermal control, and module yield.

But DDR/LPDDR on the PCB still demands careful governance.

• Timing margin
• Impedance control
• Crosstalk
• Return path
• Via transitions
• Thermal drift
• Board manufacturing variation

CoWoP may improve the memory compromise, but it does not eliminate memory convergence risk.

Why CoWoP may help UCIe and chiplet routing

UCIe and other chiplet interconnect strategies need dense routing, controlled impedance, short paths, clean return current, low jitter, and manageable power/thermal interaction. However, in conventional 2.5D architectures, much of the high-density routing is constrained by interposer size, substrate escape, package boundary, and board transition.

CoWoP may create more flexibility by making the platform PCB part of the high-density system-integration fabric. This could support more flexible routing between chiplets, memory, power, and system I/O. It may also support larger integration footprints without relying on ever-larger package substrates.

But this is also where the challenge appears. The platform PCB can no longer be treated as an ordinary board. It becomes part of the advanced-package realization path. That means PCB materials, dimensional accuracy, layer stack-up, shielding, via structures, reference planes, surface finish, warpage, inspection, and assembly control all become part of the governed convergence problem.

The transition patch makes this more realistic, but it also introduces a new boundary that must be modeled, measured, inspected, and qualified.

The new CoWoP challenges

CoWoP may reduce several package-level burdens, but it does not eliminate complexity. It shifts complexity into a new interposer-to-transition patch-to-platform PCB corridor. The key challenges include:

• Low-loss platform PCB materials
• Interposer-to-transition patch attach reliability
• Transition-patch-to-PCB attach reliability
• Pitch translation from fine-pitch interposer scale to PCB attach scale
• TGV or via reliability inside the transition patch
• Warpage and CTE mismatch
• Board flatness and dimensional control
• High-density routing precision
• Shielding between dense high-speed traces
• Return-path continuity across multiple interfaces
• PDN impedance and resonance
• VRM placement and transient response
• Decoupling location and effectiveness
• DDR/LPDDR timing and signal integrity
• UCIe routing and crosstalk
• Thermal spreading from die and HBM into board-level structures
• Inspection accuracy
• Rework strategy
• Lifecycle reliability

These challenges are solvable, but they require a different mindset. CoWoP does not simply move packaging onto a PCB. It asks the PCB ecosystem to operate closer to semiconductor-grade precision, while also asking the package ecosystem to think beyond the traditional package substrate. This is why CoWoP is not only a packaging innovation. It is a governed realization challenge.

Three architectures, three bottleneck locations

The most useful way to compare these architectures is by asking where each one places the system bottleneck. CoWoS places the bottleneck in advanced package scaling: interposer size, package substrate capability, HBM integration, substrate supply, package warpage, thermal design, SI/PI, PDN, and board transition.

Wafer-scale integration places the bottleneck in system adaptation around a very large silicon object: power delivery, cooling, mechanical design, yield management, redundancy, system serviceability, and workload mapping.

CoWoP places the bottleneck in the interposer-to-transition patch-to-platform PCB realization corridor: pitch translation, CTE continuity, low-loss PCB materials, precision manufacturing, attach reliability, power delivery, memory routing, UCIe flexibility, shielding, return-path continuity, inspection, and lifecycle evidence.

None of these paths eliminates convergence complexity. Each path chooses where complexity will live.

Why CoWoP needs a trusted realization layer

CoWoS, wafer-scale integration, and CoWoP all create different evidence domains, but the same fundamental governance problem remains. Which evidence is mature enough to support a deterministic engineering decision?

For CoWoS, the evidence includes interposer routing, substrate PDN, HBM integration, warpage, thermals, package attach, SI/PI, EM/IR, and board transition. For wafer-scale integration, the evidence includes wafer yield, defect tolerance, power delivery, cooling uniformity, mechanical stability, redundancy, board interaction, and system operation.

For CoWoP, the evidence includes interposer-to-transition-patch attach, transition-patch-to-PCB attach, platform PCB materials, VRM proximity, loop inductance, decoupling strategy, LPDDR/DDR routing, UCIe flexibility, shielding, return-path continuity, warpage, inspection, and lifecycle reliability.

The common requirement is governed convergence. This is where a scalable trusted realization layer (STRL) becomes important. STRL does not need to decide that one packaging structure is always superior. Instead, it asks whether each corridor has enough normalized, admissible, causally grounded evidence to support closure.

In this sense, CoWoP is a powerful new vector for trusted realization because it converts the platform PCB from a passive board into an active realization corridor. With the transition-patch concept included, the sharper statement is: CoWoP converts the interposer-to-transition patch-to-platform PCB boundary into a governed realization corridor.

Platform PCB as an active realization corridor

The most important idea is this: CoWoP may turn the platform PCB into the next active control plane for AI system realization. This does not mean the board replaces the interposer. It means the board becomes more deeply integrated into the convergence path.

The platform PCB must support power delivery, memory routing, thermal interaction, high-speed signaling, mechanical stability, shielding, and manufacturing precision. The board is no longer downstream from the package. It becomes part of the package-system continuum.

That creates a new research and industry-development opportunity: Interposer + transition patch + platform PCB as a governed system EM corridor. This corridor can be evaluated across:

• Power delivery and transient response
• Loop inductance and dI/dt sensitivity
• Decoupling effectiveness
• UCIe/chiplet routing flexibility
• DDR/LPDDR signal integrity
• Shielding and crosstalk
• Thermal spreading
• Mechanical stability
• CTE and warpage
• Manufacturing yield
• Inspection and test
• Field reliability

This is not only convergence theory; it’s a practical architecture direction.

Evidence domains for a governed CoWoP corridor

For CoWoP to become a credible production architecture, the key evidence domains must be governed together, not separately.

A CoWoP realization corridor would need evidence from:

• Interposer layout and redistribution
• Micro-bump or hybrid-bonding interface quality
• Transition-patch material selection
• TGV/via resistance and reliability
• Pad registration and pitch expansion
• CTE transition and shear stress
• Patch-to-PCB attach integrity, platform PCB flatness, and dimensional stability
• VRM phase-current behavior
• PDN impedance and transient droop
• Decoupling effectiveness across frequency
• DDR/LPDDR timing margin
• UCIe crosstalk and return-path continuity
• Thermal gradients and cycling stress, inspection, rework, and lifecycle failure signatures

In conventional workflows, these may be treated as separate domains. In a governed realization architecture, they become one corridor. That is the role of STRL:

• Normalize evidence
• Preserve causality
• Qualify admissibility
• Support bounded engineering authority

Why this idea matters now

The current package stack is under pressure. AI packages are becoming larger, more complex, more thermally constrained, more power-hungry, and more challenging to manufacture. Moreover, package substrates face size, availability, yield, warpage, layer-count, PDN, and cost challenges.

At the same time, memory, UCIe, power delivery, thermal design, and system-level integration are becoming harder to close independently. CoWoP may not be mature enough today to replace CoWoS in mainstream high-volume AI accelerators. But the direction is important.

If low-loss PCB materials, precision board manufacturing, inspection capability, transition-patch technology, and interposer-to-board attach reliability continue to improve, CoWoP may become one of the important platform-level architectures for future AI systems. The reason is simple.

It reduces the number of realization layers between silicon and system, but only if the transition boundary is engineered correctly. Instead of managing interposer, package substrate, and PCB as three separate convergence domains, CoWoP points toward a tighter corridor: interposer → transition patch → platform PCB.

That can potentially improve power-delivery proximity, reduce package-dominated loop inductance, keep active VRM components on the board, preserve DDR/LPDDR manufacturability, support flexible UCIe routing, and reduce some package-size and substrate-related burdens. But it also demands stronger governance.

What makes CoWoP practical

CoWoS proved that advanced packaging is central to AI scaling. Wafer-scale integration proved that silicon-scale system integration can unlock a different class of compute architecture. CoWoP may become an important middle path: wafer-level density brought closer to the platform PCB, with power, memory, routing, and system realization governed through a shorter corridor.

However, the most important CoWoP challenge is not only substrate removal; it’s the transition from silicon/interposer scale to PCB scale. The opportunity is not that CoWoP solves every problem. The opportunity is that it relocates the problem to a corridor that may be more scalable, more board-integrated, and more compatible with practical power and memory placement.

The challenge is that this corridor must be governed. Low-loss materials, pitch translation, transition-patch reliability, VRM proximity, PDN impedance, loop inductance, decoupling, LPDDR routing, UCIe flexibility, shielding, thermal behavior, warpage, and lifecycle reliability must be treated as one convergence problem. This is where STRL becomes relevant.

The future question is not only whether CoWoP can be built. The future question is whether the interposer-to-transition patch-to-platform PCB corridor can remain electrically, thermally, mechanically, manufacturability, and operationally converged across lifecycle. That is trusted realization.

It’s also the next bottleneck. And it may also be the next opportunity.

Interoperability moves data. STRL qualifies evidence. Governed convergence closes decisions.

Dr. Moh Kolbehdari is senior director of IC/packaging at Socionext US.

Editor’s Note

This is Part 2 of the mini-series on advanced packaging. Part 1 highlighted the basic comparison between CoWoS, wafer-scale integration, and CoWoP technologies.

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• Intel’s Embarrassment of Riches: Advanced Packaging
• Nvidia, TSMC, and advanced packaging realignment in 2025
• Intel flash move could put wafer-level packages on the map

The post The interposer-to-PCB realization corridor in CoWoP appeared first on EDN.

Built around the NXP RW612 wireless MCU, Quectel’s FCM365X module combines dual-band Wi-Fi 6, Bluetooth LE 5.4, Zigbee, and Thread connectivity in a single device. It integrates a 260-MHz Arm Cortex-M33 processor with TrustZone, 1.2 MB of SRAM, and 8 MB of flash, with optional PSRAM expansion.

The FCM365X gives developers the flexibility to support multiple wireless protocols while simplifying device design. Zigbee and Thread enable low-power, reliable mesh networking across smart home and industrial IoT ecosystems, with Thread emerging as a key technology for Matter-enabled devices.

Suited for power-constrained applications, the FCM365X offers multiple low-power modes and keep-alive mechanisms. Standard interfaces include GPIO, SDIO, UART, USB, SPI, and JTAG, while the QuecOpen SDK enables access to I²C, I²S, ADC, LCD, and PWM. The module also complies with WPA-PSK, WPA2-PSK, and WPA3-SAE security standards and uses AES-128 encryption.

The FCM365X is housed in an LCC+LGA surface-mount package with a compact footprint of 25.5×18.0×3.16 mm. A timeline for availability was not provided at the time of this announcement.

FCM365X product page 

Quectel Wireless Solutions

The post Wireless module simplifies multiprotocol IoT design appeared first on EDN.

The TPM1R408RH 80-V N-channel MOSFET is built on Toshiba’s latest-generation low-voltage U-MOS11-H process. It features an optimized device structure with an RDS(on) of 1.4 mΩ—about 26% lower than the 80-V TPM1R908QM based on the previous-generation U-MOS X-H process. It also improves the RDS(on)-Qg tradeoff, reducing figure of merit by ~45% versus the TPM1R908QM.

These reductions lower power loss in switch-mode power supplies for industrial equipment such as AI data centers and communication base stations. The TPM1R408RH also suppresses drain-source voltage spikes during switching, reducing EMI. This helps minimize late-stage design rework and simplifies filter and snubber circuits.

The MOSFET is supplied in the SOP Advance(E) package, which delivers approximately 65% lower package resistance and approximately 15% lower thermal resistance than Toshiba’s current SOP Advance(N) package. This reduces conduction losses and improves thermal performance, enabling higher power density in compact power supply designs.

The TPM1R408RH is available through Toshiba’s authorized on-line distributors.

TPM1R408RH product page 

Toshiba Electronic Devices & Storage 

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Infineon’s AIROC UWB TSL100 SoC enables centimeter-level distance measurement and localization using ultra-wideband (UWB) time-of-flight (ToF) technology. Designed for low-power, secure operation, the device targets automotive, consumer, and industrial applications such as secured vehicle access, in-cabin presence detection, contactless payment and ticketing, and industrial asset tracking and collision avoidance.

The TSL100 is the first member of a scalable UWB product family intended to align with upcoming standards such as IEEE 802.15.4ab. It includes a CCC-, FiRa-, and Aliro-compliant MAC. The PHY delivers 48-bit FiRa and CCC security in challenging non-line-of-sight conditions, detecting and verifying direct paths up to 100,000 times weaker than reflected paths.

The SoC enables more than two years of coin-cell battery life in CCC ranging schemes for key fobs, achieved through a dedicated low-power mode that reduces current consumption by more than 50%. Its RF architecture extends sensing functions to presence detection, kick sensing, intrusion detection, and NCAP scenarios. Additionally, AIROC zoning technology enables configurable unlock zones and inside/outside detection for Aliro-enabled smart locks.

Engineering sample kits for the AIROC UWB TSL100 are available upon request.

AIROC USB TSL100 product page 

Infineon Technologies 

The post UWB SoC provides precise distance measurement appeared first on EDN.

ST’s ST54M integrates a post-quantum cryptography (PQC) hardware accelerator, NFC controller, secure element, and eSIM on a single die. The chip helps smartphone and personal electronics manufacturers prepare for future post-quantum security requirements while enabling secure mobile connectivity. Applications include contactless payment, transit ticketing, access control, digital identity, and mobile driver’s licenses.

The ST54M’s hardware accelerator supports PQC algorithms such as ML-KEM and ML-DSA, aiding the transition from hybrid cryptographic approaches to full post-quantum deployment. It also helps protect against side-channel and fault-injection attacks and addresses emerging PQC requirements.

Based on an Arm Cortex-M3 32-bit MCU, the contactless front-end provides NFC card emulation, reader/writer, and peer-to-peer communication modes. It increases RF communication distance, simplifies NFC integration, and supports efficient low-power operation. An integrated step-up DC/DC converter enables transmit drive up to 3 W.

Samples are available now. Production and Common Criteria 2022 EUCC and EMVCo certifications are targeted for July 2026.

ST54M product page 

STMicroelectronics

The post Chip combines NFC and post-quantum security appeared first on EDN.

The Melexis MLX91229 Hall current sensor provides a second-order sigma-delta digital output that improves signal integrity in EV traction inverter applications. Optimized for automotive systems, this output tolerates heavy EMI, helping maintain signal integrity over longer PCB traces or wiring where electrical noise can introduce disturbances between the sensor and MCU.

Unlike analog sensors, the MLX91229 encodes measured current into a sigma-delta bitstream, with information represented by the density of digital pulses rather than absolute voltage levels. This encoding makes the signal inherently more resistant to electrical noise during transmission to the MCU. Because demodulation is performed in the host MCU, designers can optimize the tradeoff between fast overcurrent detection and high-accuracy current measurement.

Supporting current sensing from 200 A to 2000 A, the MLX91229 measures peak magnetic fields from 11 mT to 400 mT. It uses Manchester-encoded data transmission over differential RS-422 or LVDS interfaces. The AEC-Q100-qualified sensor operates over an ambient temperature range of –40°C to +125°C and is powered from a selectable 3.3-V or 5-V supply.

The MLX91229 is available in a 4-pin SIP through authorized distributors and is designed as a drop-in replacement for conventional analog sensors.

MLX91229 product page 

Melexis

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Старт другого Міжнародного конкурсу інноваційних проєктів Melville Sikorsky Challenge Accelerator kpi ср, 07/01/2026 - 17:31

Як університету готувати фахівців, яких індустрія телекомунікацій потребує вже сьогодні? KPI4U-2 ср, 07/01/2026 - 17:09

КПІ ім. Ігоря Сікорського — у трійці лідерів академічного рейтингу «Топ-200 Україна 2026» KPI4U-2 ср, 07/01/2026 - 17:06

A linearized output is a useful elaboration of a capacitive sensor design. But what if the circuit is located a significant distance from the control electronics?

Recently, Design Ideas included a circuit that comprised a simple analog interface to basic capacitive position sensors. Figure 1 shows its minimal six parts topology with complementary outputs: Out and –Out.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Figure 1 U1a and U1b cross-coupled Schmidt trigger timers form a ~1MHz RC multivibrator. The Tsense pulse width is inversely proportional to sensor displacement Tref/Tsen = Cref/Csen = d.

Doubling the parts count to 12 transmogrifies Figure 1 into Figure 2 and provides a linear voltage mode output,  Then, with the exemplar 38mm-diameter sensor plate capacitor connected, separation d between plates reads out as d = (Vout – 1) = 0 to 4 millimeters as Vout goes from 1 to 5v.  Vout ripple is just half a millivolt pk-pk. The linear voltage output modification is described in this Design Idea.

Figure 2 Averaging integrator A1 implicitly computes the output voltage needed to linearly balance the charge transferred onto C1 during Tref through discharge during Tsense. Vout = Tref / Tsense  + 1 = Cref / Csense + 1 = d + 1.

So, let’s take it as granted that providing a linearized output was a useful elaboration of the original design.  But suppose the capacitive sensor is located a significant distance from the control electronics.  Voltage mode analog outputs are notoriously vulnerable to noise pickup and disturbances like ground loop voltage differentials.  What to do then?  Figure 3 shows a simple and plausible remedy.  It’s a classic, if I do say so myself.  A noise- and cable length- tolerant, linear 4 to 20mA, current mode output.

Figure 3 Dangling the TLV431 shunt voltage reference Z1 from the 15 volt supply is a shortcut toward implementing a noise- and cable length- tolerant current mode output.

Here’s how it works. Figure 3’s A1 integrator generates a 1 to 5 volt linear output, much like Figure 2’s A1 does.  The difference is this 1 to 5v is inverted, referenced to +15v, and developed across 249ohm current sense resistor R5.  It’s therefore an accurate readout of Pfet Q1’s 4 to 20mA source current.  Shunt reference Z1 provides both the 1.00v integrator reference and a 5v step-down supply for U1 and U2.  DC blocking C4 and R9 trickle protect the chips from being instantly fried in case the sensor capacitor plate shorts to ground.

Some random remarks: U1’s unused inputs should be tied to +15v.  C1, 2, 3, and 4 should be rated for the full supply voltage, which itself isn’t critical but shouldn’t exceed 20v.  Otherwise Q1’s gate will be at risk for over-voltage if the load becomes disconnected.  If  the supply equals 15v as shown, voltage compliance and consequent ground noise resistance is >9v. Iout ripple is ~0.01% pk-pk.  Figure 4 shows the net nicely linear response.

Figure 4 In this graph, black = sensor readout d in mm, and red = the nicely constant 4 microamps per micrometer resolution.

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

Related Content

• Capacitive position sensor with linearized output
• ~0.1% resolution capacitive position sensor
• CMOS flip-flop used “off label” implements precision capacitance sensor
• Flip-flop plus choke comprise simple and cheap inductive sensor

The post Position sensor gets linear 4 to 20mA current source output appeared first on EDN.

Нотатки з семінару Секції вихованців КПІ у Польщі 2026 Інформація КП ср, 07/01/2026 - 13:00

⭐ Вступ до магістратури 2026 kpi ср, 07/01/2026 - 12:00

🔔 Вступ до аспірантури 2026 kpi ср, 07/01/2026 - 08:30