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Shielded inductors reduce emissions in tight layouts
Bourns’ SRP2008DP series of shielded power inductors provides the saturation current needed for dense DC/DC converter designs and miniature electronic devices. These low-profile devices, with dimensions of just 2.0×1.6×0.8 mm, enable use in compact circuits with minimal routing changes.
The eight inductors in the SRP2008DP series cover inductances from 0.24 µH to 4.70 µH, heating current (IRMS) from 1.10 A to 3.50 A, and saturation current (ISAT) from 1.60 A to 5.50 A. DC resistance ranges from 36 mΩ to 468 mΩ, and operating temperature spans -40°C to +125°C.
In crowded layouts, radiated emissions and magnetic coupling can compromise signal integrity and complicate EMC compliance. The SRP2008DP series addresses these issues with a small, shielded package and a metal-alloy powder core. The shielded design contains magnetic flux, reducing emissions to nearby circuitry, while the high-resistivity core suppresses eddy currents and limits core losses at high switching frequencies. Contained flux also minimizes coupling to adjacent traces, lowering interference in densely populated layouts.
The SRP2008DP series is available through Bourns’ authorized distributors. Request samples here.
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RISC-V SoC supports voice-enabled IoT devices
Espressif Systems is sampling its ESP32-S31 dual-core RISC-V SoC with Wi-Fi 6, Bluetooth 5.4, Thread, Zigbee, and Ethernet. Rich HMI and security features make it well-suited for IoT applications such as consumer and industrial appliances, voice-controlled devices, and automation systems.
Running at 320 MHz, the ESP32-S31’s 32-bit RISC-V microcontroller achieves 6.86 CoreMark/MHz and integrates a memory management unit and 60 GPIOs for design flexibility. One of its two cores features a 128-bit-wide SIMD data path for fast parallel processing. Memory resources comprise 512 KB SRAM and support for 250-MHz, 8-bit DDR PSRAM, with concurrent flash and PSRAM access. External memory expansion (up to octal SPI) further supports memory-intensive multimedia and AI/ML workloads at the edge.
The ESP32-S31’s HMI capabilities include a DVP camera interface, LCD support, and up to 14 capacitive touch channels. Security features span secure key management, secure boot, flash and PSRAM encryption, cryptographic hardware acceleration, and a trusted execution environment. Supported by Espressif’s open-source IoT Development Framework, the device works with common LLMs to build voice-enabled client devices that run or interact with AI agents.
To request samples of the ESP32-S31 SoC, contact Espressif’s customer support team.
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Leveling up Industry 4.0
Industry 4.0 is all about transforming manufacturing processes with advances in smart capabilities, data connectivity, and automation. It encompasses devices from sensors that capture data to motors and motor control and power devices that have a big impact on efficiency. Edge computing is also playing a larger role to combat challenges around latency, particularly in safety critical applications, and cybersecurity is critical for protecting connected devices.
(Source: Adobe Stock)
The March/April issue covers some of the key components that are vital to Industry 4.0, from new sensing approaches such as event-based sensing that enable faster and more reliable decisions to the latest designs in power devices to deliver higher efficiency in industrial systems. We also look at designing edge AI for industrial and industrial IoT systems for cybersecurity.
Machine vision plays a big role in industrial automation applications, ranging from object tracking to vibration monitoring. Prophesee believes the industry should be rethinking machine vision in industrial automation, addressing challenges around latency, data processing, and decision-making.
“As industrial systems move toward higher levels of automation and autonomy, vision is becoming a core component of the perception pipeline,” said Thibaut Willeman, head of business development and go-to-market at Prophesee.
This is driving the demand for new sensing approaches that address these challenges: reducing latency, limiting unnecessary data, and enabling faster and more reliable decisions, he added.
Willeman explains how event-based vision addresses these challenges: “By mimicking biological vision, this technology utilizes efficient sensing and collection techniques that capture changes within a specific scene. This reduces processing requirements compared with traditional frame-based methods while revealing details that conventional systems miss, opening new possibilities for precision and performance in industrial applications.”
Applications that can benefit from event-based vision include industrial automation, IoT, automotive, and edge applications.
Another component area that has a large impact on applications in the Industry 4.0 world is power electronics. As factories, energy systems, and data centers get smarter and more connected, it requires more efficient power solutions that offer high power density, said Stefano Lovati, contributing writer.
Lovati discusses some of the latest approaches to designing, packaging, and controlling power devices to deliver higher efficiency, flexibility, and scalability. One of the most significant changes introduced in the power system is the move to 800-VDC distribution in data centers.
There is also a key focus on wide-bandgap materials such as silicon carbide (SiC) and gallium nitride (GaN). SiC can operate efficiently and provide high reliability in high-voltage and high-power environments, thanks to its high breakdown voltage, low switching losses, and high thermal conductivity, while GaN, suited for low- and medium-voltage applications, can switch at high frequencies, up to the megahertz range, with very low power loss, making power converters more efficient and smaller and requiring less cooling, Lovati said.
In addition, GaN is delivering on integration, which is helping to simplify power design.
Another big element of implementing smart manufacturing within Industry 4.0 is motor control ICs and motor drives. Similar to power devices, a big challenge is efficiency. “About 50% of global energy consumption is due to electric motors, and therefore, even a moderate improvement in efficiency can provide meaningful economic benefits, helping reduce the carbon footprint,” Lovati reports.
These modern industrial motor solutions are smart and connected with advanced capabilities to identify irregularities such as excessive heat or voltage surges and respond automatically. Lovati said the introduction of AI technologies brings this function to the next level, allowing predictive maintenance and reducing factory downtime.
He covers everything from motor driver architecture and connectivity in smart motor control to AI and ML integration and software tools.
Edge computing is becoming critical for real-time data processing in industrial automation. Industrial manufacturing systems require real-time decision-making, adaptive control, and autonomous operation, but many cloud-dependent architectures can’t deliver the millisecond response required for safety-critical functions such as robotic-collision avoidance, in-line quality inspection, and emergency shutdown, said Sam Al-Attiyah, head of machine learning at Infineon Technologies AG.
Al-Attiyah said edge AI addresses high-performance and low-latency requirements by embedding intelligence directly into industrial devices and enabling local processing to support machine-vision workloads for real-time defect detection, adaptive process control, and responsive human-machine interfaces that react instantly to dynamic conditions.
He outlines an approach to designing edge AI systems for industrial applications, covering everything from requirements analysis to deployment and maintenance.
Security is also a growing concern and an industry requirement as more devices are connected in industrial environments. Francesco Vaiani, senior product manager at Seco, looks at how designing for industrial IoT systems is changing to meet the European Cyber Resilience Act and the cybersecurity extension of the Radio Equipment Directive. This marks a structural shift in how connected products must be designed, documented, and maintained, he said.
For industrial OEMs, this means more than documentation updates and demands architectural decisions that remain technically defensible throughout the operational lifetime of the device, which often exceeds 10 years, Vaiani said.
Also in this issue, we select the top 10 DC/DC converters introduced over the past year. DC/DC converter manufacturers continue to focus on two big areas: delivering higher efficiency and offering greater flexibility.
Don’t miss the APEC 2026 product roundup. This annual conference showcases the latest in power electronics devices and solutions across industries. Some of these power devices highlight major technology advances in areas such as topologies and packaging, along with meeting growing demand for higher efficiency and higher power density. They also address system complexity by helping to simplify power design.
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Finally nailed down my homebrew PCB fab process (see photos)
 | The photos are:
Over all I'm very happy with how it turned out. The main thing I'm unsure of at the moment is whether I should leave the paint on the traces or not. I figured it would provide some protection against corrosion, but as you can tell it's pretty fragile and has already been scraped off in several places. I might still just clean it all off. [link] [comments] |
METCASE expands accessory options for enclosures
METCASE’s new enclosure accessories brochure features its expanded range of options including metal tilt/swivel bail arms, a wide range of molded enclosure feet, PCB mounting parts, 19″ front panels, rack shelves and rack hardware.
(Source: METCASE USA)
These universal accessories fit METCASE models and other manufacturers’ enclosures, as well as bespoke OEM equipment housings. Applications include networking, communications, laboratory instrumentation, industrial control, test/measurement, peripherals, interfaces and medical devices.
Bail arms with 30° indexing double as desk stands. The aluminum handle profile (ordered separately) fits between two diecast side arms. It is supplied cut to the required length for the customer’s enclosure. The bail arms are available in a range of color combinations including off-white, anthracite, light gray, black and traffic white.
METCASE’s recently expanded range of molded ABS (UL 94 HB) enclosure feet kits can be specified with/without tilt legs. They are suitable for metal and plastic enclosures. There are two models: robust CASE FEET and the designer TECHNOFEET. The feet are easy to fit (just three holes required) with the fixing screws supplied. TPE non-slip inserts are included to prevent the enclosure skidding on the desk. Choose from five standard colors: off-white, traffic grey A, light gray, black and anthracite.
For mounting circuit boards, METCASE offers a range of snap-in guides (for slide-in PCB fitment) in different lengths and for board thicknesses from 0.031″ to 0.078″. For screw fitting PCBs to enclosure panels, there is a kit that includes M3 PCB pillars (0.394″ high) and mounting hardware.
METCASE also offers a range of accessories for 19″ racks. This includes matt anodized aluminum 10.5″/19″ front panels (ventilated/unventilated) in all standard heights from 1U to 6U; the 10.5″ front panels are 3U and 4U. There are also mild steel CR4 2U cantilever rack shelves for mounting equipment without rack brackets. Choose from two depths 11.02″/15.75″ in light gray or anthracite. 19″ equipment mounting kits include four bolts, four cup washers (black or gray) and four caged nuts.
For further information, view the METCASE website and download the accessories brochure: https://www.metcaseusa.com/en/Accessories/Accessories-for-Enclosures.htm
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Advancing AI performance with HBM4, SPHBM4 DRAM solutions
Over the past two decades, the raw compute capability of processors used in high‑performance computing (HPC) and artificial intelligence (AI) systems has increased at an extraordinary pace. Figure 1 illustrates this trend: XPU floating‑point performance has scaled by more than 90,000×, while DRAM bandwidth and interconnect bandwidth have improved by only about 30× over the same period.
Figure 1 The above chart highlights increases in XPU performance and interconnect bandwidth over 20 years.
This growing disparity between compute capability and data movement—often described as the memory wall and the I/O wall—has become one of the most significant constraints on achievable system performance.
For system designers, this imbalance translates directly into underutilized compute resources, rising power consumption, and increasing architectural complexity. As a result, memory bandwidth and packaging technologies have become just as critical to AI performance scaling as transistor density or core count.
HBM as a foundation for modern AI architectures
To address these bandwidth challenges, HPC and AI systems have increasingly adopted disaggregated architectures built around chiplets. While LPDDR and DDR memories continue to play important roles, high bandwidth memory (HBM) has emerged as the highest‑bandwidth DRAM solution available and a key enabler for modern accelerators.
HBM devices consist of a buffer (or base) die at the bottom and multiple 3D‑stacked DRAM layers above it. The buffer die uses very fine‑pitch micro‑bumps, allowing the memory stack to be co‑packaged with an ASIC using advanced packaging technologies such as silicon interposers or silicon bridges. Supported by rigorous standardization through the JEDEC HBM task group, HBM has become one of the most successful and widely adopted examples of chiplet‑based integration in production systems.
Figure 2 shows a representative side view of an HBM DRAM stack connected to an ASIC through a silicon interposer.
Figure 2 Here is how an HBM DRAM stack is connected to an ASIC through a silicon interposer. Source: Eliyan
A widely deployed example of HBM in practice is Nvidia’s B100 Blackwell accelerator, shown in Figure 3. The package contains two large, reticle‑sized XPU dies connected to one another through high‑bandwidth links, with HBM devices placed along the top and bottom edges of each die. Each XPU die integrates four HBM stacks—two on each long edge—resulting in a total of eight HBM devices per package.
Figure 3 Nvidia’s B100 Blackwell accelerator uses two XPUs connected to eight HBMs in a single package. Source: Nvidia
Using typical HBM3 specifications available at the time the JEDEC standard was adopted, each HBM3 device could employ an 8‑high stack of 16-Gb DRAM layers, providing 16 GB of capacity per stack. With a data rate of 6.4 Gb/s and 1,024 I/Os, each HBM3 device delivers approximately 0.8 TB/s of bandwidth. Across eight devices, this configuration provides 128 GB of total memory capacity and roughly 6.6 TB/s of aggregate bandwidth.
HBM4: Scaling bandwidth and capacity
To continue scaling memory performance alongside compute, JEDEC recently published JESD270‑4, the HBM4 standard. HBM4 introduces a number of architectural improvements over HBM3 that directly address the growing bandwidth and capacity requirements of AI workloads.
One of the most significant changes in HBM4 is a doubling of the channel count, increasing the number of I/Os from 1,024 to 2,048. In parallel, supported data rates have increased into the 6–8 Gb/s range and beyond. Memory density has also scaled, with 24 Gb and 32 Gb DRAM layers specified, along with support for 12‑high and 16‑high stacks. Reliability, availability, and serviceability (RAS) features—including DRFM—have also been enhanced.
Taken together, these advances enable substantial improvements in bandwidth, power efficiency, and capacity relative to HBM3. As an illustrative example, an HBM4e device using a 16‑high stack of 32 Gb layers provides 64 GB of capacity per device, as shown in Figure 4.
Figure 4 Eight HBM4 devices are shown in an example package accomplishing increased total capacity and bandwidth. Source: Eliyan
With 2,048 I/Os operating at 8 Gb/s, such a device can deliver up to 2 TB/s of bandwidth. In a package containing eight HBM4 devices, total memory capacity scales to 512 GB—four times that of the earlier HBM3 example—while aggregate bandwidth exceeds 16 TB/s, a 2.5× increase.
Custom HBM and the role of the base die
As HBM4 adoption accelerates, some system designers are exploring the development of custom HBM solutions optimized for specific applications. A key enabler of this trend is the evolution of the HBM base die.
In earlier HBM generations, the base die was typically manufactured using a DRAM‑optimized process, well suited for capacitor structures but less optimal for high‑speed logic. With HBM4, most suppliers are transitioning to standard advanced logic processes for the base die. This shift aligns more closely with the processes already familiar to SoC designers and opens the door to customization opportunities.
Whether using standard or custom HBM4 devices, these solutions continue to rely on advanced packaging and silicon substrates—such as interposers or bridges—to accommodate the large number of fine‑pitch connections between the memory and the ASIC.
SPHBM4: Bringing HBM‑class bandwidth to organic packaging
Despite its performance advantages, traditional HBM integration requires advanced packaging, which can increase cost and complexity. Many system designers, particularly those focused on volume production and reliability, prefer standard organic substrates. To address this gap, JEDEC has announced that it is nearing completion of a new standard for Standard Package High Bandwidth Memory (SPHBM4).
SPHBM4 devices use the same DRAM core dies as HBM4 and provide equivalent aggregate bandwidth, but they introduce a new interface base die designed for attachment to standard organic substrates. Figure 5 illustrates a side view of an SPHBM4 DRAM mounted directly on an organic package substrate, alongside an ASIC. The ASIC itself may also reside on the organic substrate, or it may remain on advanced packaging such as a silicon bridge for multi‑XPU integration.
Figure 5 Side-view of an SPHMB4 DRAM and ASIC connection is shown with the SPHBM4 DRAM attached directly to the organic package substrate. Source: Eliyan
To achieve HBM4‑class throughput with fewer pins, SPHBM4 employs higher interface frequencies and serialization. While HBM4 defines 2,048 data signals, SPHBM4 is expected to use 512 data signals with 4:1 serialization, enabling the relaxed bump pitch required for organic substrates.
Because SPHBM4 uses the same DRAM stacks as HBM4, per‑stack capacity remains unchanged. However, organic substrate routing supports longer channel lengths between the SoC and the memory, which can enable new system‑level trade‑offs. In particular, longer routing distances and angled trace routing can allow more memory stacks to be placed around a given die.
Figure 6 illustrates this effect. When HBM devices are mounted on silicon substrates, they must be placed immediately adjacent to the XPU, limiting the number of stacks to two per 25-mm die edge. With SPHBM4 on an organic substrate, three memory devices can be connected along the same edge, increasing both memory capacity and bandwidth by approximately 50%.
Figure 6 This is how 12 SPHBM4 devices in example package boost capacity and total bandwidth. Source: Eliyan
Even when a silicon substrate is still used beneath the XPU—for example, to support high‑bandwidth XPU‑to‑XPU links—the overall interposer size can be significantly reduced when memory devices are moved to the organic package. This reduction can translate into meaningful benefits in system cost, manufacturability, and test complexity.
Looking ahead
AI workloads continue to push the limits of memory bandwidth, capacity, and packaging technology. JEDEC’s HBM4 standard represents a major step forward in addressing these demands, while the emerging SPHBM4 standard expands the design space by enabling HBM‑class performance on standard organic substrates.
For system architects, these technologies offer new flexibility in balancing performance, cost, and integration complexity. As memory and packaging increasingly shape overall system capability, early consideration of options such as HBM4, custom HBM, and SPHBM4 will be essential to fully unlocking the next generation of AI and HPC performance.
Kevin Donnelly is VP of strategic marketing at Eliyan.
Related Content
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- Chiplet innovation isn’t waiting for perfect standards
- Scoping out the chiplet-based design flow
- Demystifying 3D ICs: A practical framework for heterogeneous integration
- Chiplets: 8 best practices for engineering multi-die designs
- Overcoming interconnect obstacles with co-packaged optics (CPO)
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