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Photonic integration firm PHOTON IP of Eindhoven, The Netherlands has announced its new brand identity as Photon Bridge, and appointed Paul Marchal as its new chief executive officer...

Beyond 300 Layers of Memory

The race to make denser, more-powerful 3D NAND flash memory has led to huge innovation but also new manufacturing challenges. Taller devices-three-hundred-plus layers-could be threatened in yield, performance, and reliability due to constructive-tier bending and material collapse. In this sense, these challenges come from stress mismatches in alternating stacks of silicon nitride (SiN) and oxide (TEOS) layers that constitute this memory structure.

To comprehend and solve the problem, the Semiverse Solutions team used SEMulator3D virtual Design of Experiments (DOE) to replicate, measure, and analyze stress-induced deformation in the fabrication process. The outcomes emphasize the very important consideration of stress management and material properties in realizing manufacturable high-layer-count NAND architectures.

Understanding How 3D NAND Is Built

It achieves higher densities in 3D NAND by stacking SiN and oxide layers vertically in a staircase arrangement. Contacts are etched through such tall stacks to reach underlying transistors, and slit etchings divide the structure into functional memory blocks.

Until SiN can be replaced by conductive metal, an oxide cantilever is temporarily formed: it is anchored at one end while being unsupported at the other end. This rather fragile structure increasingly becomes vulnerable as the number of layers grows, expanding from ~550 nm at 200 layers to ~700 nm at 300 layers. Various contributors to tier collapse are as follows:

• Stress and strain mismatches between SiN and oxide
• Surface tension during SiN removal
• Cantilever length and geometry

What the Virtual Studies Revealed

Using SEMulator3D’s stress analysis tools, the team conducted two DOE studies to characterize how stress may evolve with tier bending and collapse.

Key findings from the first DOE:

• SiN Stiffness (Young’s Modulus, Ey) and oxide thickness are the dominant variables influencing stress-based deformation.
• Present at low Ey values (70 GPa) due to minimal displacement.
• At 125 GPa, collapse occurred at longer cantilever lengths (700 nm), especially with thinner oxides.
• At 256 GPa, severe displacement and voiding occurred across all test conditions.
• Increasing oxide thickness improved resistance but did not eliminate failure risks.

The second DOE compared the effects of intrinsic SiN stress (compressive vs. tensile). Results showed compressive SiN caused larger displacements, widening the range of potential collapse.

The manufacturing implications

These studies present obvious engineer methods that can be employed to maximize yields in ultra-high-layer NAND:

• The SiN and oxide stress values need to be matched and hopefully reduced.
• Shorten cantilever length by designing an etch profile.
• If possible, increase oxide thickness to stabilize the stack.

Through virtual simulation of these interactions, SEMulator3D engineers have the ability to realize the process changes that actually matter without being solely reliant on expensive experimental work on the actual silicon.

Conclusion

With NAND flash closing in on 300 layers and more, tier bending and collapse remain edge manufacturing threats. Stress analyses and virtual DOE studies by the Semiverse team have revealed that exacting control of material properties and stack geometry is key to both securing yields and shortening time to market.

With the SEMulator3D platform from Lam Research, chipmakers gain a powerful predictive lens helping transform potential failure points into opportunities for robust, scalable memory innovation.

(This article has been adapted and modified from content on Lam Research.)

The post How SEMulator3D Predicts and Prevents Tier Collapse in NAND Manufacturing appeared first on ELE Times.

‘Nature Electronics’ Paper Details System That Blends Best Traits Of Once-Incompatible Technologies—Ferroelectric Capacitors and Memristors

Breaking through a technological roadblock that has long limited efficient edge-AI learning, a team of French scientists developed the first hybrid memory technology to support adaptive local training and inference of artificial neural networks.

In a paper titled “A Ferroelectric-Memristor Memory for Both Training and Inference” published in Nature Electronics, the team presents a new hybrid memory system that combines the best traits of two previously incompatible technologies—ferroelectric capacitors and memristors into a single, CMOS-compatible memory stack. This novel architecture delivers a long-sought solution to one of edge AI’s most vexing challenges: how to perform both learning and inference on a chip without burning through energy budgets or challenging hardware constraints.

Led by CEA-Leti, and including scientists from several French microelectronic research centers, the project demonstrated that it is possible to perform on-chip training with competitive accuracy, sidestepping the need for off-chip updates and complex external systems. The team’s innovation enables edge systems and devices like autonomous vehicles, medical sensors, and industrial monitors to learn from real-world data as it arrives adapting models on the fly while keeping energy consumption and hardware wear under tight control.

The Challenge: A No-Win Tradeoff

Edge AI demands both inference (reading data to make decisions) and learning (updating models based on new data). But until now, memory technologies could only do one well:

• Memristors (resistive random access memories) excel at inference because they can store analog weights, are energy-efficient during read operations, and the support in-memory computing.
• Ferroelectric capacitors (FeCAPs) allow rapid, low-energy updates, but their read operations are destructive—making them unsuitable for inference.

As a result, hardware designers faced the choice of favoring inference and outsourcing training to the cloud, or attempt training with high costs and limited endurance.

Training at the Edge

The team’s guiding idea was that while the analog precision of memristors suffices for inference, it falls short for learning, which demands small, progressive weight adjustments.

“Inspired by quantized neural networks, we adopted a hybrid approach: Forward and backward passes use low-precision weights stored in analog in memristors, while updates are achieved using higher-precision FeCAPs. Memristors are periodically reprogrammed based on the most-significant bits stored in FeCAPs, ensuring efficient and accurate learning,” said Michele Martemucci, lead author of the paper.

The Breakthrough: One Memory, Two Personalities

The team engineered a unified memory stack made of silicon-doped hafnium oxide with a titanium scavenging layer. This dual-mode device can operate as a FeCAP or a memristor, depending on how it’s electrically “formed.”

• The same memory unit can be used for precise digital weight storage (training) and analog weight expression (inference), depending on its state.
• A digital-to-analog transfer method, requiring no formal DAC, converts hidden weights in FeCAPs into conductance levels in memristors.

This hardware was fabricated and tested on an 18,432-device array using standard 130nm CMOS technology, integrating both memory types and their periphery circuits on a single chip.

The post French Team Led by CEA-Leti Develops First Hybrid Memory Technology Enabling On-Chip AI Learning and Inference appeared first on ELE Times.

Microchip’s MCP9604 thermocouple conditioning IC reduces the cost and complexity of in-line production applications that operate in high and low temperature extremes

Precision four-channel temperature measurement is critical for production-line applications ranging from chemical and food processing, manufacturing process control and medical and HVAC equipment to refrigerated, cryogenic and other carefully controlled environments. With the introduction of the MCP9604 integrated thermocouple conditioning IC, Microchip Technology has overcome a thermal measurement and integration barrier with the first single-chip, four-channel  I2C thermocouple conditioning IC to deliver up to ± 1.5°C accuracy and provide an alternative to discrete and multichip thermocouple conditioning solutions that can introduce errors and add system design complexity.

“For more than two centuries, the thermocouple has been a critical tool for measuring extremely high temperatures, but the necessary precision and accuracy could not be achieved with the level of integration and cost-effectiveness that is required for today’s demanding production-line applications,” said Keith Pazul, vice president of Microchip’s mixed-signal linear business unit. “Our device now delivers a combination of precision, integration and cost-effectiveness, helping reduce the need for as many as 15 discrete components and associated system design challenges.”

The MCP9604 device delivers its advanced measurement accuracy at four thermocouple locations by using higher-order NIST ITS-90 equations rather than the single-order linear approximations of analog amplifier designs. As an example, it achieves ninth-order accuracy with K-type thermocouples, all in one integrated chip containing the ADCs, cold junction compensation temperature sensors, amplifiers and other components required for the signal chain, temperature measurement and math engine.

Removing the need for external components simplifies PCB design, reduces bill of materials costs, and can help eliminate the weeks of costly, time-consuming and complex unit-by-unit in-line validation and calibration that discrete solutions require in the thermocouple measurement signal chain before they can begin reporting data to the host system.

The MCP9604 also offers flexibility and versatility by supporting the eight most common thermocouple types including the J option as well as the K option for operating at temperatures as low as
-200°C. In addition to supporting a wide, -200°C to +1372°C temperature range across a diverse range of industrial applications, the MCP9604 also supports I2C communication to allow easy integration with microcontrollers and other digital systems.

Building on Earlier Advancements

The MCP9604 builds on the release of Microchip’s single-channel thermocouple conditioning IC, the first all-in-one device to deliver up to ± 1.5°C accuracy. The core competencies that made this device possible have paved the way for the company’s four-channel single-chip MCP9604 device that delivers its digital temperature reading with industry-high accuracy levels for an I2C thermocouple conditioning device.

The post Four-Channel Thermocouple Measurement with Integrated Conditioning Now Possible with ±1.5°C System Accuracy appeared first on ELE Times.

Of course it's not GaN and doesn't output what it says. 5 volt output at maybe 2 amps if it feels like it. Guess the case is cheap to print on. submitted by /u/junktech [link] [comments]

КПІ ім. Ігоря Сікорського у Вроцлаві: нові можливості для віддалених лабораторій kpi пн, 09/29/2025 - 01:00

submitted by /u/m_user_name [link] [comments]

In this article, we'll solidify our understanding of the reactance modulator and Armstrong modulator circuits by working through a series of design problems.

submitted by /u/AutoModerator
[link] [comments]

submitted by /u/Cautious-Ninja-000 [link] [comments]

This program gives you a database of all the discrete parts you have and allows you to browse by category, checkout the part's datasheet, product page, and more. I created this for my lab because I always knew I had previous components that I could use for new projects, but locating them and finding the specs were too time consuming. It was usually easier just to buy new parts. With this system, it's easy to store parts, locate them, evaluate them for your project, and check them out from inventory. The whole thing runs on a raspberry Pi and hosts the parts library digitally which can be accessed by anyone on the local network. The code and details can be found at the project GitHub. I have a lot more information there: github.com/grossrc/DigiKey_Organizer If you use the program, consider donating it would help me put a lot. Hope this is useful to you guys! submitted by /u/MaxwellHoot [link] [comments]

submitted by /u/Green-Pie4963 [link] [comments]

New sensing solutions, from pyroelectric infrared sensors to in-plane Hall-effect switches, help engineers improve performance and efficiency in space-constrained designs.

Рамкова угода про співпрацю та академічну мобільність між КПІ ім. Ігоря Сікорського та École Polytechnique KPI4U-2 пт, 09/26/2025 - 20:53

At the European Conference on Optical Communication (ECOC 2025) in Copenhagen, Denmark (29 September–1 October), the Optical Internetworking Forum (OIF), together with 35 participating member companies, is demonstrating how multi-vendor collaboration is delivering real-world interoperability and enabling the scale, speed and efficiency that future networks demand...

In booth C4107 at the European Conference on Optical Communication (ECOC 2025) in Copenhagen, Denmark (29 September–1 October), TRUMPF Photonic Components GmbH of Ulm, Germany (part of the TRUMPF Group) — which makes vertical-cavity surface-emitting lasers (VCSELs) and photodiodes for datacoms — is showcasing linear performance of its new PAM4 100Gbps, 850nm multimode VCSEL in collaboration with customer Optomind Inc of Suwon, South Korea, which provides optical interconnect solutions for data centers including artificial intelligence (AI) and high-performance computing (HPC) networks. Along with the VCSEL, TRUMPF also offers a 100G wideband (842–948nm) photodiode that can be used to further optimize the link...

In a live demo in booth C4107 at the European Conference on Optical Communication (ECOC 2025) in Copenhagen, Denmark (29 September–1 October), TRUMPF Photonic Components GmbH of Ulm, Germany (part of the TRUMPF Group) is unveiling its new 100G vertical-cavity surface-emitting laser (VCSEL)...

Motorola’s 68000 blended 32-bit power with a 16-bit bus, creating a balanced, orthogonal, and elegant architecture that powered everything from Macintosh to arcade machines.

Edge AI—enabling autonomous vehicles, medical sensors, and industrial monitors to learn from real-world data as it arrives—can now adopt learning models on the fly while keeping energy consumption and hardware wear under tight control.

It’s made possible by a hybrid memory system that combines the best traits of two previously incompatible technologies—ferroelectric capacitors and memristors—into a single, CMOS-compatible memory stack. This novel architecture has been developed by scientists at CEA-Leti, in collaboration with scientists at French microelectronic research centers.

Their work has been published in a paper titled “A Ferroelectric-Memristor Memory for Both Training and Inference” in Nature Electronics. It explains how it’s possible to perform on-chip training with competitive accuracy, sidestepping the need for off-chip updates and complex external systems.

 

The on-chip memory conundrum

Edge AI requires both inference for reading data to make decisions and learning, a.k.a. training, for updating models based on new data on a chip without burning through energy budgets or challenging hardware constraints. However, for on-chip memory, while memristors are considered suitable for inference, ferroelectric capacitors (FeCAPs) are more suitable for learning tasks.

Resistive random-access memories or memristors excel at inference because they can store analog weights. Moreover, they are energy-efficient during read operations and better support in-memory computing. However, while the analog precision of memristors suffices for inference, it falls short for learning, which demands small, progressive weight adjustments.

On the other hand, ferroelectric capacitors allow rapid, low-energy updates, but their read operations are destructive, making them unsuitable for inference. Consequently, design engineers face the choice of either favoring inference and outsourcing training to the cloud or carrying out training with high costs and limited endurance.

This led French scientists to adopt a hybrid approach in which forward and backward passes use low-precision weights stored in analog form in memristors, while updates are achieved using higher-precision FeCAPs. “Memristors are periodically reprogrammed based on the most-significant bits stored in FeCAPs, ensuring efficient and accurate learning,” said Michele Martemucci, lead author of the paper on this new hybrid memory system.

How hybrid approach works

The CEA-Leti team developed this hybrid system by engineering a unified memory stack made of silicon-doped hafnium oxide with a titanium scavenging layer. This dual-mode memory device can operate as a FeCAP or a memristor, depending on its electrical formation.

In other words, the same memory unit can be used for precise digital weight storage (training) and analog weight expression (inference), depending on its state. Here, a digital-to-analog transfer method, requiring no formal DAC, converts hidden weights in FeCAPs into conductance levels in memristors.

The hardware for this hybrid system was fabricated and tested on an 18,432-device array using standard 130-nm CMOS technology, integrating both memory types and their periphery circuits on a single chip.

CEA-Leti has acknowledged funding support for this design undertaking from the European Research Council and the French Government’s France 2030 grant.

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• Will Memory Constraints Limit Edge AI in Logistics?
• Two new runtime tools to accelerate edge AI deployment
• For Leti and ST, the Fastest Way to Edge AI Is Through the Memory Wall

The post Hybrid system resolves edge AI’s on-chip memory conundrum appeared first on EDN.