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Cadence announced an expansion of its broad collaboration with NVIDIA to accelerate Cadence’s Design for AI and AI for Design strategy. The next generation of agentic AI design solutions includes autonomous, long-running agents that require accelerated, trusted, physics-grounded engines to translate design intent into automated flows, generate designs and debug errors, and manage long, complex, end-to-end workflows. Cadence’s leadership in agentic AI is expanded by integrating its portfolio of industry-leading chip and system design solutions with NVIDIA’s accelerated computing stack.

“The fusion of agentic AI and physics-based design is transforming how the world’s most advanced chips are engineered,” said Anirudh Devgan, president and CEO of Cadence. “Through our expanded collaboration with NVIDIA, we’re bringing together Cadence’s expertise in agentic IC design and physics-driven optimisation with NVIDIA’s accelerated computing to advance a new era of AI-driven chip innovation. Together, we’re enabling customers to design more intelligent, efficient silicon that will power the next generation of computing and AI infrastructure.”

“AI is driving the largest infrastructure buildout in history—spurring the creation of new chips, systems, and AI factories around the world,” said Jensen Huang, founder and CEO of NVIDIA. “Together, NVIDIA and Cadence have created the Cadence Millennium M2000—a revolutionary AI supercomputer built to tackle the immense scale and complexity of designing the world’s next generation of infrastructure.”

Broadest-Ever Portfolio of Accelerated Design Solutions

To give agents and engineers the tools they need, Cadence has expanded its design solutions accelerated with NVIDIA Grace CPUs and NVIDIA Blackwell GPUs—and as a turnkey deployment on the Cadence Millennium M2000 Supercomputer—delivering up to 80X greater throughput and up to 20X lower power consumption. This expanded offering now spans analysis, optimisation, and design, with key solvers deeply optimised with NVIDIA CUDA-X. One example is the Cadence Clarity 3D Solver demonstrating that a Millennium M2000 system configured with 8X NVIDIA RTX Pro 6000 GPU servers is up to 5X faster, or 4X better cost iso-performance, compared to an equivalent CPU-based solution, when extracting complex and large-scale designs.

Cadence accelerated solutions that will be available in 2026 include:

• Electronic Design Automation (EDA): The industry’s leading place-and-route solution, Innovus Implementation System; chip, chiplet and 3D-IC analysis and optimisation with Celsius Thermal Solver and Voltus IC Power Integrity Solution; advanced memory and circuit analysis with EMX Planar 3D Solver and Liberate MX Memory Characterisation; and Spectre X Simulator and Quantus Field Solver for circuit analysis.
• System Design Automation (SDA): Industry-leading advanced package and PCB optimisation with the Allegro X Design Platform, Clarity 3D Solver, Celsius EC Solver; system-level multiphysics analysis with Fidelity CFD Software; and Cadence MSC Actran for physical AI system analysis and optimisation.
• Life Sciences / Bio: ROCS X is an AI-enabled virtual screening solution that enables scientists to conduct 3D searches of over 200 trillion drug-like molecules. Target X is a physics-based AI solution that detects potential druggable pockets, achieving a success rate of over 90%.

The Cadence Allegro X Design Platform and the Cadence Reality Digital Twin Platform also integrate with NVIDIA Omniverse libraries for photo-realistic visualisation, critical for multi-disciplinary engineering and design. Cadence’s MSC Virtual Test Drive (VTD) is being integrated with NVIDIA Cosmos and NVIDIA Omniverse NuRec for advancing the state of the art in physical AI.

Design for AI and AI for Design

Industry leaders use Cadence’s full suite of accelerated agentic solutions to design the next generation of AI infrastructure. The Cadence Reality Digital Twin Platform helps teams use physics-based models and AI to design and operate AI factories, accelerating deployment timelines and unlocking new revenue streams across the data centre portfolio.

Cadence is advancing AI-driven engineering with its agentic AI solutions, led by the Cadence ChipStack AI Super Agent, to help engineers deliver higher quality, more complex designs. Cadence and NVIDIA are also collaborating on future agentic AI innovations in custom and analogue design and building deep research and long-running agents for engineering NVIDIA NemoClaw, an open source stack that simplifies running OpenClaw always-on assistants, more safely, with a single command. As part of the NVIDIA Agent Toolkit, it installs the NVIDIA OpenShell runtime—a secure environment for running autonomous agents, and open source models like NVIDIA Nemotron.

From Silicon to Turbofan Engines, Customers Achieve the Previously Impossible

Cadence customers across semiconductors, automotive, aerospace and life sciences are using agentic AI, GPU-accelerated solutions and the Millennium M2000 Supercomputer to tackle design challenges that are not achievable with traditional approaches.

Honda is using Cadence Fidelity CFD Software, accelerated on the Millennium M2000 GB200 NVL72 system, to pursue time-accurate, full turbofan engine simulation—a grand challenge in computational fluid dynamics (CFD) previously impractical for routine design use.

“This capability opens the door to a more exploratory design methodology—one where our engineers can evaluate tradeoffs earlier and innovate with greater confidence as we develop the next generation of high-performance gas turbine engines,” said Keiji Otsu, CEO, Honda R&D.

Micron is integrating GPU-accelerated Cadence design technologies and Cadence’s agentic AI solution directly into its HBM memory design flow to accelerate iteration and maintain accuracy at leading-edge scale.

“As our HBM and next-generation memory designs grow in scale and complexity, reducing the cycle time for our most demanding verification and simulation steps has become essential,” said Sanjay Mehrotra, Chairman, president and CEO, Micron. “Through our expanded collaboration with Cadence, we’re integrating GPU-accelerated design technologies—powered by NVIDIA computing—and building agentic AI directly into our development environment.”

Larsen & Toubro Semiconductor is using the Cadence Spectre X Simulator, accelerated up to 5X with NVIDIA GPUs, to shorten design cycles for next-generation AI and data centre chips as the company advances India’s sovereign semiconductor ambitions.

“Faster design iteration and verification directly translate into competitive advantage and time to market for the highly customised AI silicon we’re building,” said Sandeep Kumar, CEO, Larsen & Toubro Semiconductor. “GPU-accelerated performance from Cadence’s Spectre X Simulator gives our teams the throughput to confidently move complex, AI-ready chips into production faster.“

The post Cadence and NVIDIA Collaborate on Accelerated Engineering Solutions for Agentic AI Chip and System Design​ appeared first on ELE Times.

Texas Instruments (TI) has unveiled new isolated power modules, helping enable increased power density, efficiency and safety in applications ranging from data centres to electric vehicles (EVs). The UCC34141-Q1 and UCC33420 isolated power modules leverage TI’s IsoShield technology, a proprietary multichip packaging solution that achieves up to three times higher power density than discrete solutions in isolated power designs. TI is showcasing these innovations at the 2026 Applied Power Electronics Conference (APEC), March 23-26 in San Antonio, Texas.

“Packaging innovation is revolutionising the power industry, with power modules at the forefront of this transformation,” said Kannan Soundarapandian, vice president and general manager, High Voltage Products at TI. “TI’s new IsoShield technology delivers what power engineers need most: smaller solutions with improved efficiency and reliability, and a faster time to market. It is the latest example of TI’s continued commitment to advance power semiconductor technology to help solve today’s engineering challenges.”

Redefining power density with TI’s packaging technology

Historically, power designers have turned to power modules to conserve valuable board space and simplify the design process. As chip sizes reach their physical limits and miniaturisation increases in importance, advancements in packaging technology are enabling further performance and efficiency gains.

TI’s new IsoShield technology combines a high-performance planar transformer with an isolated power stage, offering functional, basic, and reinforced isolation capabilities. It enables a distributed power architecture, helping manufacturers meet functional safety requirements by avoiding single-point failures. The result is a packaging advancement that shrinks solution size by as much as 70% while delivering up to 2W of power, enabling compact, high-performance and reliable designs for automotive, industrial and data centre applications that require reinforced isolation.

Advancing data centre and EV performance through power innovations

Power density innovations are nowhere more critical than in today’s evolving data centre and automotive designs. Meeting design requirements in those applications starts with advanced analogue semiconductors – the components that enable smarter, more efficient operations. As global data centres continue to scale to meet exponentially growing demand, high-performance power modules must pack more power in smaller spaces. With TI’s IsoShield packaging technology, designers can achieve higher power density in compact form factors, ensuring reliable and safe operation of the world’s digital infrastructure. Similarly, the increased power density enabled by IsoShield technology helps engineers design lighter and more efficient EVs that significantly extend range and enhance performance. 

Building on our power module innovation

For decades, TI has strategically invested in power management technology, with recent developments in power modules that feature integrated transformers and integrated inductors. Through innovative proprietary packaging solutions such as IsoShield and MagPack technologies, along with a comprehensive portfolio of over 350 power modules with optimised packages, TI’s semiconductors empower engineers to maximise performance in any power design or application.

Innovating what’s next in power at APEC 2026

In booth No. 1819 at the Henry B. González Convention Centre, TI will feature the isolated power modules with IsoShield technology in a high-power, high-performance automotive silicon carbide (SiC) 300kW traction inverter reference design. Additionally, TI will debut other advancements in data centers, automotive, humanoid robots, sustainable energy and USB Type-C® applications, including an 800V to 6V DC/DC power distribution board. This design features TI’s portfolio of gallium nitride integrated power stages, digital isolators and microcontrollers that help enable high efficiency and power density in power conversion for next-generation data center computing trays with AI processors.

The post TI unveils high-performance isolated power modules to advance power density in data centers and EVs appeared first on ELE Times.

By Shreya Bansal, Sub-Editor

STMicroelectronics introduced the Stellar P3E, a next-generation automotive microcontroller with embedded artificial intelligence (AI) acceleration, positioning it as a key enabler for software-defined vehicles (SDVs) and consolidated “X-in-1” electric vehicle architectures.

Announced during a media briefing, the Stellar P3E marks a significant step in integrating real-time AI with deterministic control, addressing the rising complexity of modern automotive systems driven by electrification and connectivity.

Powering the X-in-1 Transition

Automakers are increasingly shifting toward “X-in-1” architectures, which consolidate multiple functions, such as battery management, onboard charging, and power conversion into a single system. This reduces hardware redundancy, wiring, and overall system weight.

The Stellar P3E is designed to sit at the centre of this transition, combining high-performance computing, advanced analogue integration, and AI capabilities in a single chip.

Embedded AI for Real-Time Intelligence

A key highlight of the new MCU is its Neural ART Accelerator, a dedicated neural processing unit (NPU) that enables real-time AI inference at the edge. The accelerator is capable of significantly reducing inference time, up to 69 times faster than CPU-based implementations, while maintaining low power consumption.

This allows vehicles to process unstructured data, detect patterns, and adapt system behaviour dynamically, supporting applications such as predictive maintenance, intelligent sensing, and optimised energy management.

Addressing Industry-Wide Complexity

With vehicles evolving into software-driven platforms, the industry is facing unprecedented challenges, including exponential software growth, stricter safety and cybersecurity requirements, and ongoing supply chain uncertainties.

STMicroelectronics emphasised three key pillars behind the Stellar P3E:

• Reducing complexity and cost through hardware consolidation and software optimisation
• Enabling smarter systems with AI-driven algorithms
• Delivering high-performance computing with precise sensing and actuation

The MCU also complies with ISO 21434 cybersecurity standards and incorporates flexible safety configurations, including split-lock and lockstep modes.

High Performance, Rich Integration

The Stellar P3E delivers up to 8,000 CoreMark performance and features:

• Up to 19.5 MB of embedded non-volatile memory using phase-change memory (PCM)
• Over 300 GPIOs and more than 100 ADC channels
• Support for Gigabit Ethernet and CAN-XL communication

These capabilities enable integration of multiple powertrain components, including inverters, DC-DC converters, and battery systems within a unified architecture.

Industry Shift to Software-Defined Vehicles

The launch aligns with the broader move toward software-defined vehicles, where functionality is increasingly delivered through software updates rather than hardware changes. With support for over-the-air (OTA) updates and scalable memory, the Stellar P3E enables continuous feature upgrades over a vehicle’s lifecycle.

The company is targeting a $16 billion automotive MCU market opportunity by 2030, driven by electrification, ADAS, and SDVs.

Why 28nm Still Matters: ST Explains Its Node Strategy

When asked about ST’s decision to use a 28-nanometer process node at a time when competitors are pushing toward more advanced nodes, they clarified that while advanced nodes are typically optimised for maximum compute efficiency, they are not always cost-effective for automotive applications that require a balance of digital processing and analogue functionality.

The company stated that 28nm represents a “sweet spot” where both analogue performance and digital complexity can be efficiently integrated. It also highlighted its advantage in embedding large memory at this node, leveraging what it described as one of the densest technologies in the industry.

On the supply chain front, ST emphasised its vertically integrated manufacturing strategy. The 28nm technology used for Stellar P3E is produced at its high-capacity facility in Crolles, France, allowing the company to retain greater control over production.

Unlike reliance on external foundries, which are currently under pressure from AI-driven demand, ST’s in-house manufacturing enables it to prioritise automotive and industrial customers. The company also noted its dual-sourcing strategy for automotive MCUs at every stage of production to enhance resilience.

The post STMicroelectronics Unveils AI-Enabled ‘Stellar P3E’ MCU, Backs 28nm Strategy for Cost and Supply Chain Stability appeared first on ELE Times.

Infineon Technologies AG of Munich, Germany and solid-state transformer (SST) solutions firm DG Matrix are partnering to enhance the efficiency of power conversion required to connect AI data centers and industrial power applications to the public grid. As part of the collaboration, DG Matrix will source latest-generation silicon carbide (SiC) technology from Infineon for use in its Interport multi-port solid-state transformer platform. This should strengthen DG Matrix’s semiconductor supply chain and enhance the efficiency, power density and reliability of its SST systems, which are deployed worldwide...

I've been designing this 6-stage symmetrical half-wave voltage multiplier build. I was planning to build it like this: battery->zvs circuit for getting ac and proper 50kHz frequency->small transformer for upping the voltage to 10kV->multiplier. The lower part generates negative voltage, and the upper part positive, both 120kV so combined they give a 240kV spark. submitted by /u/CountCrapula88 [link] [comments]

Power Integrations Inc of San Jose, CA, USA (which provides high-voltage integrated circuits for energy-efficient power conversion) has introduced a flyback topology that extends the power range of flyback converters to 440W — well beyond the limits that traditionally required more complex resonant and LLC topologies. The new TOPSwitchGaN flyback IC family unites the company’s PowiGaN technology with its TOPSwitch IC architecture, reducing complexity, eliminating heat-sinks in many cases, shortening design time, improving manufacturability, and lowering total system cost...

Power Integrations Inc of San Jose, CA, USA (which provides high-voltage integrated circuits for energy-efficient power conversion) has introduced a flyback topology that extends the power range of flyback converters to 440W — well beyond the limits that traditionally required more complex resonant and LLC topologies. The new TOPSwitchGaN flyback IC family unites the company’s PowiGaN technology with its TOPSwitch IC architecture, reducing complexity, eliminating heat-sinks in many cases, shortening design time, improving manufacturability, and lowering total system cost...

In booth #1753 at the Applied Power Electronics Conference (APEC 2026) at the Henry B. Gonzalez Convention Center in San Antonio, Texas, USA (22–25 March), Toshiba America Electronic Components Inc – the North American semiconductor and storage business of Tokyo-based semiconductor maker Toshiba Corp – is highlighting its latest power semiconductor technologies enabling more intelligent, efficient and sustainable system designs...

In booth #1753 at the Applied Power Electronics Conference (APEC 2026) at the Henry B. Gonzalez Convention Center in San Antonio, Texas, USA (22–25 March), Toshiba America Electronic Components Inc – the North American semiconductor and storage business of Tokyo-based semiconductor maker Toshiba Corp – is highlighting its latest power semiconductor technologies enabling more intelligent, efficient and sustainable system designs...

Renesas Electronics Corp of Tokyo, Japan has introduced what is claimed to be the industry’s first bidirectional switch using depletion-mode (d-mode) GaN technology, capable of blocking both positive and negative currents in a single device with integrated DC blocking. Targeting single-stage solar micro-inverters, AI data centers and onboard electric vehicle chargers, the high-voltage TP65B110HRU simplifies power converter designs and replaces conventional back-to-back FET switches with a single low-loss, fast-switching, easy-to-drive device...

Renesas Electronics Corp of Tokyo, Japan has introduced what is claimed to be the industry’s first bidirectional switch using depletion-mode (d-mode) GaN technology, capable of blocking both positive and negative currents in a single device with integrated DC blocking. Targeting single-stage solar micro-inverters, AI data centers and onboard electric vehicle chargers, the high-voltage TP65B110HRU simplifies power converter designs and replaces conventional back-to-back FET switches with a single low-loss, fast-switching, easy-to-drive device...

💡 Молодих науковців запрошують взяти участь у Фестивалі молодіжної науки – 2026 kpi вт, 03/24/2026 - 15:29

In process industries, field contacts from pressure, temperature, flow switches, limit switches, push buttons, etc., are read by programmable logic controllers and/or distributed control systems (PLC/DCS) through digital input modules.

They are located in the unit control room, which is at least 100 meters away from the field. Long cables run between them. They supply 24 VDC to these contacts and measure the current through them to determine status, such as open or closed.  With so many rodents and creatures around the plant, a cable cut can happen at any time, even if adequate precautions are taken.

Wow the engineering world with your unique design: Design Ideas Submission Guide

A PLC/DCS cannot distinguish between contact open and cable open. A wrong decision may be made by PLC/DCS if a cable open is read as a field contact open, which may still be closed. Solutions currently available commercially are very expensive and therefore not adopted across all industries. Running parallel wires is also done for some critical contacts.

Figure 1’s circuit provides an economical and reliable solution for distinguishing between a cable open and a field contact open. This circuit outputs 4 mA for contact open, 20 mA for contact closed, and 0 mA for cable open. This small module may be placed very close to the field contact. The contact status may be read by an analog input module instead of a digital input module.

Figure 1 The current output (Io) is given to the analog inputs of the DCS/PLC. R7 is the load inside of the analog input module of the DCS/PLC.

How does the circuit work?

1. When the field contact is open:

• Current at pin3 of U1A=0= (Vr/R2) –( Io*R6/(R4+R6))
• Hence, (Vr/R2) = ( Io*R6/(R4+R6)

Vr is the output of the voltage regulator U3, which is 5 V. When substituting the component values shown in Figure 1, Io is approximately 4 mA.

2. When the field contact is closed:

• Current at pin3 of U1A =0= ((Vr/R2) +(Vr/R3))–( Io*R6/(R4+R6))
• Hence, ((Vr/R2) +(Vr/R3)) = ( Io*R6/(R4+R6))

Substituting the component values, Io comes out to around 20 mA. Q1 adjusts the current flowing through R6, which is Io, the output of this circuit. The circuit around Q2 limits the maximum output current to around 30 mA.

The circuit in Figure 1 is for testing. SW1 can be operated to set the field contact to closed or open. The output current (Io) is around 4 mA for open field contact, 20 mA for a closed field contact, and 0 mA for cable open. SW2 is operated to create an open cable condition.

Precise values are not necessary; hence, precision components are not needed. The PLC/DCS needs to be programmed to read around 0 mA, 4 mA, and 20 mA to decode cable open, contact open, and contact closed conditions.

Figure 2 shows the interface module housing the above circuitry. You do not need a separate power supply for this module, as it takes power from PLC/DCS. The connection of this module to the field contact and the analog input of the PLC/DCS is shown here.

Figure 2 The interface module circuit and connection to the field contact. The DCS/PLC’s analog input is also shown. 

A thorough explanation of this circuit can be viewed in the embedded video below. 

 

Jayapal Ramalingam has over three decades of experience in designing electronics systems for power & process industries and is presently a freelance automation consultant.

Related Content

• A 0-20mA source current to 4-20mA loop current converter
• Silly simple precision 0/20mA to 4/20mA converter
• A two-wire temperature transmitter using an RTD sensor

The post Is your PLC/DCS reading the field contacts reliably? appeared first on EDN.

IBL Lab GmbH, the DAkkS (Deutsche Akkreditierungsstelle GmbH) accredited EMC test laboratory of IB Lenhardt AG, has significantly expanded its high-field immunity testing capabilities with a substantial investment in a suite of high-power amplifier systems from Rohde & Schwarz. This upgrade directly addresses increasing demands from the defence sector for rigorous and realistic testing compliant with standards like MIL-STD-461, AECTP-500, VG 95373 and VG 95370.

The core of this optimisation lies in the deployment of the R&S BBA300-FG180 amplifier (6-18 GHz), coupled with a Schwarzbeck HWRD650 EMS antenna through a direct-mount configuration. This approach eliminates RF cable losses, enabling IBL Lab to achieve field strengths exceeding 400 V/m – a level rarely attained – with a target of surpassing 600 V/m.

The integration of Rohde & Schwarz equipment provides several key advantages for IB Lenhardt. A comprehensive testing range from 9 kHz to 18 GHz is now supported by the integrated system comprising the R&S BBA300-FG180, R&S BBL200A-A5000, R&S BBA150-BC2000, and R&S BBA300-DE1000 amplifiers. Direct antenna mounting on the BBA300-FG180 maximises power transfer and significantly boosts field strength in the 6-18 GHz range, a capability crucial for demanding defence applications.

As Florian Schmidt, Head of Department EMC at IBL Lab GmbH, explains: “Direct antenna mounting on the BBA300-FG180 was the key to achieving field strengths exceeding 400 V/m in the 6–18 GHz range. Combined with our other amplifiers, this setup enables high-field immunity testing across the entire frequency range from 9 kHz to 18 GHz for demanding defence applications.”

Furthermore, amplifiers like the R&S BBA300-FG180 and R&S BBA300-DE1000 offer wide frequency coverage alongside high linearity, while the R&S BBL200A-A5000 delivers 5 kW of continuous power with 100% mismatch tolerance. Leveraging Rohde & Schwarz’s reputation for precision and reliability reinforces IBL Lab’s DAkkS accreditation (ISO/IEC 17025) and NATO CAGE Code (CNH80), bolstering confidence in test results.

Finally, IBL Lab’s position as one of the first laboratories globally to operate the R&S BBA300-DE1000 demonstrates a commitment to utilising cutting-edge testing capabilities. Daniel Lenhardt, CEO of IB Lenhardt AG, says: “High field strengths and stable RF signals are essential for realistic and reliable immunity testing, underscoring the strategic importance of this investment. The combination of high performance and broad frequency coverage positions IBL Lab to effectively serve manufacturers of defence, aerospace, automotive, and industrial electronics requiring advanced RF immunity validation.”

The post R&S amplifiers enable high-field immunity testing expansion at IB Lenhardt Lab appeared first on ELE Times.

Турклуб "Глобус": змагання, перемоги і донати Інформація КП вт, 03/24/2026 - 12:00

India’s electronics and semiconductor sector is currently experiencing a significant turning point in its trajectory. This transformation is primarily fuelled by key government initiatives such as the Production Linked Incentive (PLI), Electronic Manufacturing Clusters Scheme (EMCS), and Design Linked Incentive (DLI) schemes. In addition, the sector is benefiting from the realignment of global supply chains towards India and the anticipated growth in domestic demand. As a result of these factors, industry projections indicate that the sector is on track to reach a market value of US$500 billion by the year 2030. This rapid evolution signifies India’s transition from being a consumption-driven market to emerging as a prominent global centre for innovation, manufacturing excellence, and intellectual property (IP) development.

At the core of this momentum are events such as Electronica India and Productronica India, which are organised by Messe Muenchen India. These platforms have transformed beyond mere trade shows and have become pivotal drivers of industry advancement. By bringing together policymakers, international investors, pioneers, suppliers, and producers in a single setting, these events facilitate more than just conversations. They lead to tangible results such as establishing new collaborations, transferring technology, integrating supply chains, and translating policies into market opportunities that enhance India’s electronics value chain.

In a highly insightful discussion, the President of IMEA (India, Middle East, Africa) at Messe München, along with the CEO of Messe München India, sheds light on India’s remarkable journey from a consumption-oriented market to a prominent global electronics manufacturing hub. Recognising the imperative need to keep pace with the swiftly evolving industry landscape, electronica India and productronica India are making a strategic shift to a biannual schedule commencing from April 2026 in Greater Noida. These cutting-edge platforms, revered as “decision-grade” marketplaces, are strategically designed to streamline the supply chain operations, showcasing over 400 exhibitors and fostering collaborative partnerships, technological advancements, and bolstering domestic production capabilities.

In a recent conversation with Bhupinder Singh, President of India, Middle East, and Africa at Messe München, as well as the Chief Executive Officer of Messe München India, we discussed…

ELETimes: India’s electronics landscape has evidently undergone a significant transformation. In your opinion, which pivotal shift do you believe is driving the market trends presently?

Bhupinder Singh:  The crucial transition happening in the current landscape, shifting from intent to execution at a large scale. With capacity increasing, compliance becoming stricter, and decision-making processes becoming more efficient, the market must enhance its capability to assess technologies, validate partners, and smoothly progress from planning to implementation without delays caused by evaluating multiple vendors. In such a dynamic setting, business platforms should not only bring stakeholders together but also facilitate productive outcomes.

ELETimes: What sets electronica India and productronica India apart as marketplaces in 2026?
Bhupinder Singh: Our role is to simplify a complex supply chain by reducing friction. Given the deeply interconnected nature of electronics manufacturing, Electronica India and Productronica India bring the entire value chain into a single, focused environment—enabling companies to evaluate solutions end-to-end, align cross-functional stakeholders, and make more confident decisions. Ultimately, this is not just a showcase, but a purpose-built, decision-grade marketplace.

ELETimes: What level of scale and participation can the industry anticipate from the April 2026 editions?

Bhupinder Singh: Scale matters—but what truly drives outcomes is decision density. The April 2026 edition is built around high-intent engagement, bringing together 400+ exhibitors representing over 1,000 companies from 20+ countries, connecting with an expected 30,000+ trade attendees. Through live demonstrations, operational equipment, supplier interactions, and structured meetings, participants can evaluate solutions in a focused setting. With multiple options available in one place, teams can benchmark more efficiently, compare with greater accuracy, and accelerate decision-making. In effect, the event condenses months of fragmented vendor assessments into a few days of meaningful, high-value evaluation—because attendees don’t come to browse; they come to make decisions.

ELETimes: What prompted the shift to hosting two editions each year at this point?
Bhupinder Singh: The pace of the industry has fundamentally shifted. Product cycles are shorter, supplier qualification is more stringent, and project timelines leave far less room for delay. A single annual—or even biennial—touchpoint no longer reflects how companies make decisions, build, and scale today.

This transition also aligns with the momentum driven by India’s PLI and ECMS schemes, which are accelerating investments across electronics components, products, and systems manufacturing, while enabling faster capacity expansion across regions.

Taking all of this into account, from 2026 we are moving to a biannual format: Greater Noida in April and Bengaluru in September—two key markets, two distinct buying cycles, and two strategic opportunities each year to evaluate solutions, strengthen partnerships, and fast-track implementation.

ELETimes: What new opportunities does a biannual format create for exhibitors?

Bhupinder Singh: It creates three distinct advantages: speed, precision and responsiveness.
First, pipeline velocity improves—exhibitors can engage buyers more frequently, which directly supports conversion.
Second, regional precision—North and South are both high-opportunity, but they operate differently in procurement cycles and ecosystem density.
Third, market responsiveness—brands can launch updates, gather feedback and recalibrate strategy with far less lag. In electronics, speed is not a nice-to-have. It’s a competitive advantage.

And for visitors, it means access. If you’re sourcing, building, or scaling in India, you don’t have to wait for a single annual sourcing window. You can qualify suppliers, shortlist faster and keep projects moving with a six-month rhythm.

ELETimes: The April edition is being hosted in Uttar Pradesh—what new value or advantage does this bring to the event?

Bhupinder Singh: Hosting changes the quality of engagement. With Uttar Pradesh as host, the presence of relevant government departments and institutional stakeholders becomes structural—not optional. For international and domestic participants, a host state context brings sharper visibility on facilitation and readiness—so expansion conversations move from exploratory to executable

ELETimes: The event will be inaugurated by Hon’ble Chief Minister of Uttar Pradesh, Shri Yogi Adityanath—what message does this send to the broader industry?

Bhupinder Singh: It reflects a clear strategic commitment. Electronics sits at the core of national competitiveness and industrial growth, and the strength of state ecosystems increasingly determines the pace of progress. An inauguration led by the Chief Minister underscores electronics as a priority growth engine. For the market, this sends a strong signal—it boosts confidence and enhances the overall business environment surrounding the marketplace.

ELETimes: Uttar Pradesh has also unveiled targeted initiatives at Electronica India and Productronica India 2026. What makes these events the right platform for such announcements?
Bhupinder Singh: The aim is to elevate engagement beyond generic networking and create structured access. These initiatives are designed to raise the signal-to-noise ratio and make engagement more purposeful:

• UP Electronics Leadership Summit: A closed-door gathering of 100+ CEOs to accelerate top-level partnership and investment conversations
• CM-Meet: An invite-only leadership roundtable to align on priorities and collaboration themes
• 1: 1 meeting with international companies: To foster and accelerate alliances, JVs and market-entry conversations.
• Startup Showcase: 20+ startups to connect innovation with adoption and manufacturing capability

ELETimes: How international is the 2026 edition—practically speaking?

Bhupinder Singh: You’ll see a genuinely global footprint—strong participation across Asia, Europe and the US—bringing better benchmarking and more partnership options. As we progress toward the event, we are building toward the planned scale of 400+ exhibitors from 20+ countries.

For visitors and exhibitors alike, this matters because international presence improves benchmarking, expands partnership options, and raises the standard of technical and commercial discussions.

ELETimes: What does “end-to-end ecosystem” actually translate to on the show floor?
Bhupinder Singh: It translates to a complete, decision-ready view of electronics manufacturing—where stakeholders can assess both upstream and downstream implications and qualify partners with confidence. That includes components and modules, SMT and assembly, automation, test and inspection, embedded hardware and connectivity, EMS capabilities, and the factory disciplines that protect yield and reliability—cleanroom readiness, ESD control, safety systems and process consistency. The point isn’t variety. The point is readiness because electronics outcomes are not driven by one technology choice—they are driven by how choices perform together across the production flow.

ELETimes: You also announced a significant milestone for India’s PCB ecosystem—BPCA 2026 in collaboration with ELCINA. What shift does this represent?

Bhupinder Singh: We’ve formally launched the next phase of BPCA 2026—Bharat’s dedicated platform for Printed Circuit Boards and Assemblies—in partnership with ELCINA (Electronic Industries Association of India). As part of this transition, the India PCB Tech Conference will be rebranded as the Bharat PCB Tech Conference, creating a stronger national platform aligned with global standards and manufacturing readiness. With BPCA joining Electronica India and Productronica India 2026, we are shaping a more focused, future-ready PCB ecosystem under one roof.

ELETimes: Where does the Bharat Electronics Yatra fit into the larger strategy?

Bhupinder Singh: The Yatra is about building market readiness before the event and expanding engagement beyond the venue. It takes the conversation directly to the clusters and decision-makers, captures on-ground perspectives, and drives awareness across the broader production chain. The outcome is better participation quality: a more informed audience, sharper buyer intent and a show floor aligned to real needs. It’s a pipeline builder, pulling the ecosystem in—focused on relevance and ensuring this trade forum remains connected to the market between editions.

ELETimes: Final message—what makes the April 2026 editions of electronica India 2026 and productronica India 2026 essential fixtures on every serious industry calendar?
Bhupinder Singh: Because India is no longer “next”—it is now. Capacity is expanding, standards are sharpening, and scale is accelerating faster than most markets can track. In such a cycle, advantage belongs to those who evaluate rigorously and secure the right partners early. electronica India and productronica India are designed as decision-grade marketplaces—where technologies are benchmarked live, and partnerships move swiftly from discussion to commitment. And in April 2026, Greater Noida is where market leaders go not just to get ahead—but to stay ahead.

The post India’s Electronics Powerplay: Why 2026 Will Lead the Way for the Industry appeared first on ELE Times.

OXIDE Corp of Yamanashi, Japan (which specializes in optical crystals and frequency-conversion technology) and Finland-based laser developer and manufacturer Vexlum (which was spun off from Tampere University of Technology’s Optoelectronics Research Centre in 2017) have officially entered into a strategic partnership agreement. The collaboration focuses on the development and manufacturing of high-power laser systems designed to overcome primary scaling bottlenecks in the quantum computing and semiconductor industries...

For decades, the semiconductor industry has relied on the relentless pursuit of Moore’s Law—the doubling of transistors on an IC every two years—to deliver ever-increasing performance and functionality. This traditional approach, primarily focused on scaling individual transistors and integrating more components onto a single, monolithic 2D die, has driven innovation across countless industries.

However, as we approach the physical limits of silicon, and the economic realities of advanced process nodes become increasingly prohibitive, the conventional path of monolithic scaling is facing significant roadblocks. Companies are encountering diminishing returns in terms of performance gains, escalating design and manufacturing costs, and challenges in integrating diverse functionalities onto a single chip without compromising yield or power efficiency.

In response to these growing pressures, a fundamental shift is occurring in chip design: the move toward 3D ICs and heterogeneous integration. This paradigm offers a compelling alternative, allowing companies to overcome the limitations of traditional 2D scaling by integrating multiple specialized chiplets—each potentially manufactured on different process technologies and optimized for specific tasks—into a single, advanced package.

Beyond raw performance, the shift to 3D IC offers benefits in design flexibility, manufacturing economics, and form factor by mixing dies manufactured on different process nodes. This modularity enables the use of cutting-edge processes only where absolutely necessary for performance, while leveraging more mature, cost-effective nodes for other functions. This approach also facilitates the creation of smaller, more integrated systems, crucial for devices where space is at a premium.

The unique challenges of advanced packaging

The shift to 3D IC advanced packaging isn’t without its complexities. Heterogeneous integration introduces a new set of design challenges that traditional monolithic approaches simply didn’t encounter. Existing design tools and methodologies are insufficient for the scale and complexity of heterogeneous integration.

With 3D IC design now featuring hundreds of thousands to millions of connections, it’s impractical to use manual methods like spreadsheets to manage the intricate connectivity and interactions between 3D layers.

3D IC designers also face the daunting task of managing a myriad of diverse IP and data formats. Source data for connectivity is supplied in a multitude of formats, including CSV files, LEF/DEF, GDS, Verilog RTL, and plain text files.

Integrating multi-vendor chiplets exacerbates the need for standardized, machine-readable design-models to ensure operability across different EDA tool design workflows. Furthermore, 3D IC designs typically include multiple dies from different foundries and processes, increasing the risk of failure and making them harder to identify and fix.

Because data is often dynamic, with updates received throughout the design process, incorporating new versions of design IP threatens to obliterate existing data, especially when IC and package designers work concurrently. So, designers must be able to accept input from various stakeholders—often designing their content concurrently—to create a design that is both electrically and physically correct.

Ensuring the integrity and functionality of these complex systems demands comprehensive system-level verification, not individual component checks. To truly harness the immense power of heterogeneous integration and confidently navigate these multifaceted challenges, a robust, systematic, and proven framework is not just beneficial—it’s foundational. Otherwise, without a clear roadmap, design teams risk costly iterations, delayed time-to-market, and sub-optimal product performance.

System technology co-optimization: The key to efficient 3D IC design

System technology co-optimization (STCO) is exactly that foundational framework: an advanced, holistic methodology that elevates optimization beyond the considerations of a single die. Instead of narrowly tuning devices at the wafer or chip level—a practice known as device technology co-optimization (DTCO)—STCO allows for the optimization of power, performance, area, cost, and reliability across various components as a unified whole, including silicon, packages, interposers, PCBs, and even mechanical components.

Thus, STCO provides the system-centric framework needed for organizations to stay ahead of the curve in 3D IC design, maximizing value, minimizing risk, and unlocking new levels of competitive differentiation.

STCO breaks down silos that historically separated silicon, package, and board design, and it leverages system-level analysis to guide critical decisions—such as chiplet partitioning, placement, interconnect planning, and assembly verification—early in the design flow. This integrated approach not only reveals downstream issues much sooner but also enables “shift-left” validation and optimization, preventing costly respins and delays.

The strategic benefits of STCO are profound for organizations embracing 3D IC design. Companies can realize shorter design cycles with fewer iterations and handoffs, thanks to continuous verification and ongoing feedback between domains.

Cross-functional teams—from system architects to packaging, DFT, and manufacturing engineers—can observe interdependencies and work together to resolve them proactively. This leads to faster time-to-market, improved first-pass yield, and the ability to confidently deliver innovative, heterogeneous products that meet aggressive performance requirements.

Mastering heterogeneous integration: Your expert guide

This is precisely where the Heterogeneous Integration eBook series becomes a handy guide. This eBook series doesn’t just describe the challenges, it provides a comprehensive, actionable methodology to overcome them.

This robust 10-step methodology for heterogeneous integration, formulated by author of this article, guides designers through the entire process: from the initial creation of the 3D digital twin and system-level planning to detailed design optimization, rigorous verification, and final sign-off. By following this methodology, designers are ensured a streamlined and predictable path to robust advanced package development.

Designers gain expert insights into building a complete digital model, optimizing physical layouts, ensuring robust verification, and preparing designs for successful manufacturing. The series is structured into four eBooks, each focusing on a critical stage of the heterogeneous integration journey—from initial 3D Digital Twin Creation and Assembly Floorplanning, through Scenario Completion, and finally to the crucial Signoff phase—empowering design teams with the knowledge and best practices to confidently lead the next wave of chip innovation.

If you’re ready to move beyond outdated methodologies and truly unlock the power of 3D IC and heterogeneous integration, now is the time to act. The Heterogeneous Integration eBook Series offers not just theory, but a proven framework to help conquer the formidable challenges of advanced packaging.

Don’t let complexity stand in the way—arm yourself with strategies for system-level optimization, cross-domain collaboration, and predictable first-pass success.

Keith Felton is marketing manager for Xpedition IC packaging solutions at Siemens EDA. Working extensively in IC package design since the late 1980s, Keith drove the launch of the industry’s first dedicated system-in-package design solution in the early 2000s and led the team that launched Siemens OSAT Alliance program.

Special Section: Chiplets Design

• What the special section on chiplets design has to offer
• Chiplet innovation isn’t waiting for perfect standards
• Scoping out the chiplet-based design flow

The post Demystifying 3D ICs: A practical framework for heterogeneous integration appeared first on EDN.

Renesas Electronics Corporation, a premier supplier of advanced semiconductor solutions, unveiled the industry’s first bidirectional switch using depletion-mode (d-mode) GaN technology, capable of blocking both positive and negative currents in a single device with integrated DC blocking. Targeting single-stage solar microinverters, AI data centres, and onboard electric-vehicle chargers, the high-voltage TP65B110HRU dramatically simplifies power-converter designs. It replaces conventional back-to-back FET switches with a single low-loss, fast-switching, easy-to-drive device.

Single-Stage Topology Boosts Efficiency, Reduces Components

Today’s high-power conversion designs use unidirectional silicon or silicon carbide (SiC) switches, which block current in only one direction when in the off state. As a result, power conversion must be divided into stages with multiple switched bridge circuits. For example, a typical solar microinverter uses a four-switch full bridge to convert from DC to DC for the first stage, followed by a second stage to produce the final AC output to the grid. Even as the electronics industry moves toward more efficient single-stage converters, engineers must work around inherent switching limitations. Many of today’s single-stage designs use conventional unidirectional switches back-to-back, resulting in a fourfold increase in switch count and reduced efficiency.

Bidirectional GaN changes this landscape entirely. By integrating bidirectional blocking functionality on a single GaN product, power conversion can be achieved in a single stage using fewer switching devices. A typical solar microinverter, for example, will require only two high-voltage Renesas SuperGaN® bidirectional devices, eliminating the intermediary DC-link capacitors and cutting the switch count by half. In addition, GaN products switch fast, with low stored charge, enabling higher switching frequencies and higher power density. In a real-world single-stage solar microinverter implementation, the new GaN architecture demonstrated higher than 97.5 per cent power efficiency with the elimination of back-to-back connections and slow silicon switches.

Combining Robust Performance and Reliability with Silicon-Compatible Drivers

Renesas’ field-proven 650V SuperGaN devices are based on a proprietary normally-off technology that is simple to drive and highly robust. The TP65B110HRU combines a high-voltage bidirectional d-mode GaN chip co-packaged with two low-voltage silicon MOSFETs with high threshold voltage (3V), high gate margin (±20V), and built-in body diodes for efficient reverse conduction. Compared with enhancement-mode (e-mode) bidirectional GaN devices, the Renesas bidirectional GaN switch offers compatibility with standard gate drivers that require no negative gate bias. This translates to a simpler, lower-cost gate loop design and fast, stable switching in both soft and hard switching operation without a performance penalty. Power conversion topologies that require hard switching, such as the Vienna-style rectifier, can benefit from its high dv/dt capability of >100 V/ns, with minimum ringing and short delays during on/off transitions. The Renesas GaN device enables true bidirectional switching with high robustness, high performance and ease of use.

“Extending our SuperGaN technology to the bidirectional GaN platform marks a major shift in power conversion design norms,” said Rohan Samsi, Vice President, GaN Business Division at Renesas. “Customers can now achieve higher efficiency with fewer switching components, smaller PCB area and lower system cost. At the same time, they can accelerate design by leveraging Renesas’ system-level integration with gate drivers, controllers and power management ICs.”

Key features of the TP65B110HRU:

• ±650V continuous peak AC and DC rating, ±800V transient rating
• 2kV Human Body Model ESD protection rating (HBM and CDM)
• 110 mΩ typical RSS,ON @ 25⁰C
• 3V typical Vgs(th)
• No negative drive required
• ±20V maximum Vgs
• >100 V/ns dv/dt immunity
• 1.8V, VSS,FW freewheeling diode voltage-drop
• TOLT top-side cooled package with industry standard pin-out

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