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How AI is driving a new paradigm in test distribution
Artificial intelligence (AI) is accelerating semiconductor innovation at a pace that is forcing a rethinking of conventional production test strategies. The rapid scaling of graphics processing units (GPUs), AI accelerators, and heterogeneous compute architectures is increasing not only device complexity, but also the amount of test content required to validate performance, reliability, and quality across the manufacturing flow.
As AI infrastructure investments continue to expand, semiconductor manufacturers are building increasingly sophisticated devices that combine massive transistor counts, advanced packaging, high-bandwidth memory (HBM), chiplet architectures, and emerging co-packaged optical (CPO) interfaces. These devices are redefining the relationship between design, validation, and production test.
The result is a new test paradigm in which test content, infrastructure, and analytics are distributed dynamically across multiple insertions—from wafer sort through system-level test (SLT)—to balance cost-of-test, defective-parts-per-million (DPPM), and time-to-market objectives.
AI devices driving a step change in test requirements
The transition from monolithic devices to heterogeneous multi-die systems has substantially increased the burden on automated test equipment (ATE). AI processors now incorporate far more compute engines, memory bandwidth, and power-delivery complexity than previous generations of high-performance devices.
At the same time, traditional transistor scaling no longer delivers the same gains once associated with Moore’s Law. To continue improving system performance, designers are adopting More-than-Moore integration strategies that combine chiplets, 3D packaging, integrated voltage regulation, and advanced interconnect technologies within increasingly dense package architectures. These changes are producing several cascading effects on tests.
First, scan and functional test workloads are growing dramatically as transistor counts increase. Modern AI devices require extremely large volumes of scan vectors that must be delivered at gigabit-per-second speeds through either massively parallel digital channels or high-speed serial interfaces such as PCIe and USB.
Second, power requirements are rising rapidly. Device power supplies must now support kiloamp-class current delivery while maintaining tight regulation and accuracy under highly dynamic loading conditions. Flexible power architectures capable of extensive channel ganging are becoming increasingly important as final-test power envelopes continue to climb.
Thermal management is becoming equally critical. AI devices entering production are expected to push package-level power dissipation into multi-kilowatt ranges, making active thermal control essential throughout the test flow. In advanced environments, thermal systems are increasingly paired with predictive analytics capable of anticipating thermal excursions before they occur, enabling proactive cooling and tighter junction-temperature management.
Advanced packaging complicates multisite test
Migration toward larger 2.5D and 3D packages is also changing the physical realities of production test. As package sizes expand to accommodate more chiplets, HBM stacks and photonic components, device handling and multisite efficiency become more difficult to optimize. Larger sockets consume increasing amounts of device-under-test (DUT) board real estate, constraining routing resources and limiting tester scalability.
In parallel, manufacturers are moving toward larger tray formats carrying fewer devices per tray because of package dimensions and handling constraints. These shifts reduce some of the traditional efficiencies associated with high-parallelism production environments.
The addition of photonic and CPO technologies introduces another layer of complexity. Optical interfaces require integrated electro-optical validation across multiple stages of manufacturing, extending test coverage well beyond conventional electrical characterization. As a result, optical instrumentation is increasingly being introduced at wafer probe, optical-engine test, final package test, and SLT insertions.
Test engineering becoming more software- and data-centric
The growing complexity of AI devices is changing not only hardware requirements, but also the nature of test engineering itself. In other words, engineering organizations are under pressure to accelerate bring-up, reduce debug cycles, and maintain quality targets despite rapidly increasing test content volumes. This is driving tighter integration between design, silicon validation, and manufacturing teams.
As a result, AI-assisted software tools are beginning to play a larger role in test-program generation, debug optimization, and adaptive workflow management. Real-time analytics platforms can now aggregate data across multiple insertions, enabling faster correlation of failures and more intelligent allocation of test coverage throughout the production flow.
In these environments, test content is no longer statically assigned to a single insertion. Instead, coverage increasingly shifts throughout the flow depending on where defects can be detected most efficiently and economically. This distributed approach to test is becoming essential as AI devices scale toward trillion-transistor complexity.
Shifting test left reduces packaging risk
One major trend is the movement of more test content earlier in the manufacturing flow. For advanced AI devices, packaging costs now represent a substantial portion of total product cost because of technologies such as HBM and chip-on-wafer-on-substrate (CoWoS) integration. Packaging defective die into expensive multi-die assemblies can significantly increase material waste and reduce yield.
To mitigate this risk, manufacturers are pushing more coverage to wafer-level and die-level test insertions to improve known-good-die confidence before assembly. Figure 1 illustrates how test distribution increasingly spans the entire workflow, with tighter interaction between design, validation, and production environments.
Figure 1 Test distribution has expanded to accommodate growing need for test across the manufacturing ecosystem—beginning with silicon validation and extending through system-level test. Source: Advantest
This shift-left strategy (Figure 2) includes broader scan coverage and expanded fault modeling at speed testing, and increasingly system-aware functional validation at the die level. Some workflows also incorporate calibration, trimming, and memory repair operations prior to package assembly.
Figure 2 Shifting test content left enables more coverage at wafer and die test stages to improve known-good-die screening before package assembly. Source: Advantest
In more advanced implementations, active thermal control capabilities are also migrating closer to singulated-die test stages. The objective is straightforward: identify marginal or defective components before they enter expensive advanced-packaging flows.
System-level test expanding
At the same time, other forms of coverage are shifting later in the process. As devices become more heterogeneous and application-specific, certain failure mechanisms emerge only under realistic operating conditions involving software execution, thermal loading, timing interactions, or high-bandwidth traffic patterns.
These conditions are often difficult—or impossible—to replicate during traditional structural or functional test insertions. Consequently, SLT is becoming increasingly important for AI and HPC devices. System-level environments can expose defects associated with workload execution, protocol interactions, and real-world operating states that are not observable during earlier production stages.
New approaches, including scan-over-PCIe methodologies and highly parallel SLT architectures, are helping manufacturers improve coverage while attempting to control the significant test times associated with these environments. Figure 3 illustrates the corresponding shift-right strategy.
Figure 3 Shifting test content right enables additional test coverage to be executed after packaging to further reduce DPPM before shipment. Source: Advantest
Real-time analytics enabling adaptive test distribution
The increasing fragmentation of test insertions is creating demand for tighter orchestration across the production floor. Modern test infrastructures are evolving toward highly connected environments in which data streams continuously between validation, wafer sort, final test, and SLT operations. Real-time analytics platforms can then use this data to optimize insertion decisions, adapt test limits, and improve yield-learning cycles.
GPU-accelerated edge inferencing and AI-based decision engines are also enabling faster adaptive responses during production. In some cases, computation can be offloaded from the tester itself to remote compute infrastructure, allowing more sophisticated analytics without compromising throughput.
This level of coordination requires consistent software frameworks and portable test content capable of moving seamlessly between insertions and platforms. So, shared execution environments and unified debug tools are becoming increasingly important as manufacturers attempt to reduce engineering overhead while accelerating deployment.
Optical test adds new workflow stages
CPO and photonic integration introduce additional challenges because optical functionality must be validated alongside traditional electronic behavior. Unlike conventional semiconductor devices, photonic systems often require multiple dedicated insertion points throughout manufacturing. These may include photonic wafer test, dual-sided probing of electronic and photonic die, optical-engine characterization, and additional packaged-module validation after integration with ASICs.
As with electrical tests, much of this optical validation is shifting earlier in the flow to ensure known-good optical engines prior to final assembly. However, full electro-optical verification often still requires additional socketed final-test and SLT insertions after system integration.
Figure 4 highlights how optical test introduces additional insertion points spanning photonic wafer test, optical-engine validation, final package test, and SLT.
Figure 4 For testing CPO devices, test content shifts left for three insertions and right for final socketed device test. Source: Advantest
Test distribution is becoming a strategic optimization problem
AI is transforming semiconductor tests from a relatively linear production step into a highly distributed optimization challenge involving power, thermal management, data analytics, packaging economics, and workflow orchestration. Meeting future quality and throughput requirements will require closer collaboration across the semiconductor ecosystem, including design teams, ATE suppliers, packaging providers, and system integrators.
As AI devices continue scaling in complexity, test infrastructure must evolve from traditional defect screening toward intelligent, adaptive validation environments capable of making real-time decisions across the manufacturing flow. In that sense, the future of semiconductor test may depend as much on data movement and workflow intelligence as on the tester hardware itself.
Fabio Pizza is business segment manager at Advantest Europe.
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- Optimizing Automated Test Equipment for Quality and Complexity
- Advanced verification: unlocking the door to a new era of AI chips
- AI test chip offers proof of concept for digital in-memory compute design
- From Defect Images to Die Prediction: How Intel Is Scaling AI in Advanced Manufacturing
The post How AI is driving a new paradigm in test distribution appeared first on EDN.
У КПІ відкрили оновлену навчально-наукову лабораторію технології та модифікування біополімерів
Новий простір для навчання й підготовки кваліфікованих фахівців целюлозно-паперової галузі з’явився на Факультеті автоматизації, промислової інженерії та екології (ФАПІЕ) КПІ ім. Ігоря Сікорського.
My first ever PCB
 | Hey guys I just made my first ever PCB at college. I designed it online and then cut it out with a PCB-CNC machine. We didn’t have time for the teachers to show me the masking process so we just did it without. \\ The red wire is because I made a mistake with the design but it worked out in the end. [link] [comments] |
Capacitive position sensor with linearized output
An only slightly less simple followup circuit also ratios sensor capacitance to a reference capacitor to measure micrometers…this time linearly.
A few weeks ago, Design Ideas published a simple circuit of mine that provides an analog interface to capacitive position sensors. Figure 1 shows that basic design with its separate complementary outputs: Out and –Out.
Wow the engineering world with your unique design: Design Ideas Submission Guide
Figure 1 The U1a and U1b cross-coupled Schmidt trigger timers form a ~1MHz RC multivibrator. The Tsense pulse width is inversely proportional to sensor displacement (Tref/Tsen= Cref/Csen = d).
Figure 2 shows the “Simple Simon” method it offered for acquisition of the sensor position signal: passive RC averaging of the Tsense pulse train.
Figure 2 Passive RC averaging of the Tsense output yields the analog position output.
The resulting analog output, as shown in figure 3, provides good range and resolution but is nonlinear.
Figure 3 This graph shows the sensor performance when Out is connected to a 12bit ADC using +5V for its reference. The black curve (left axis) equals the plate separation (d) in millimeters. The red curve (right axis) equals the ADC lsb resolution in micrometers.
So, I got to thinking about linearization and the advantages it would provide, and wondering how tough it would be. It turned out to be not that difficult.
Figure 4 shows the resulting interface with added linearization circuitry. Just an added opamp, three resistors, and two non-critical caps did the trick. Here’s how it works.
Figure 4 Averaging integrator A1 linearizes the displacement sensing response. R5 is shown as a precision type, albeit just out of force of habit. It, like the ON resistances of U2’s switches, actually cancels out.
Each capacitance measurement cycle, the 500ns Tref pulse causes 4066 switch U2d to deposit a quantum of charge on integrator A1’s summing node of Qref = Tref/R5. Meanwhile the sensor-capacitance proportional Tsen pulse subtracts Qsen = Tsen(Vout – 1)/R5. The charge balance is forced by A1 to maintain Qsen = Qref, therefore Tsen(Vout – 1)/R5 = Tref/R5, and Vout – 1 = Tref/Tsen = Cref/Csen = d. Note that R5 magically (?) disappears from the math.
Figure 5 shows the straight-as-an-arrow-in-zero-gravity result.
Figure 5 In this graph of the enhanced circuit results, the black curve equates to the sensor readout d in mm, with red at a constant 1 mV per micron resolution.
Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974. They have included best Design Idea of the year in 1974 and 2001.
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- From gap to signal: Non-contact capacitive displacement sensors
- Simple circuit interfaces differential capacitance sensor
The post Capacitive position sensor with linearized output appeared first on EDN.
TNO and ASML join forces to scale European photonic chip manufacturing
I made my version of low power binary watch !
 | This is my version of qron0b. Meet takku:b, a BCD wristwatch which uses CR2032. It uses 0.6uA during sleep and when awake uses around 4mA - 4.5mA depending on the amount of LED is turned on. It is made using STM32L010C6 It currently displays following info on each cyclic display:
Will be adding alarm soon. [link] [comments] |
Infineon’s GaN technology boosts efficiency and power density in BRC Solar’s Power Optimizer
Міжнародна конференція "Прикладна геометрія, інженерна графіка та об'єкти інтелектуальної власності" 2026
14 травня 2026 р. відбулася ХV Міжнародна науково-практична конференція "Прикладна геометрія, інженерна графіка та об'єкти інтелектуальної власності". Проходила вона в онлайн-режимі.
ClassOne secures record follow-on Solstice S8 orders from AOI
Universal Control Solution for Endurance Tests of Vehicle Components
In the automotive sector, individual components such as vehicle seats often need to be tested or demonstrated independently of the overall configuration to ensure functions such as adjustment ranges, massage, heating, and ventilation. However, the control elements and power supply configured for the final vehicle are not available for this purpose. GÖPEL electronic has developed the SmartController for this application. This universal control solution is designed for demanding individual or endurance tests, presentations, and functional demonstrations, as well as laboratory applications. The powerful platform combines modern hardware, flexible software architecture, and intuitive operating concepts in a compact system.
The SmartController is based on the proven Serie62 G CAR 6281 hardware platform and offers a modular architecture with versatile interfaces. With this, GÖPEL electronic has created a universal hardware foundation that can be used across projects and customized as needs a clear advantage for test environments with changing requirements. Thanks to its high scalability, the SmartController supports up to eight bus interfaces, providing comprehensive support for automotive communication standards such as CAN, CAN-FD, LIN, and Automotive Ethernet, including residual bus simulation, diagnostics, and monitoring. The integrated Ethernet and Wi-Fi connectivity enables seamless networking and easy integration. This makes the SmartController suitable for both long-term endurance tests and dynamic development and presentation environments.
A key feature is the tablet control framework, which enables modern and convenient operation. Its uniform structure allows for use in various projects while maintaining a consistent user experience. Features such as the “Sticky Keys” input assistance (“Touch ’n’ Click / Make ’n’ Break”) support ergonomic and safe operation regardless of the hardware used. With the SmartController, GOEPEL electronic underscores its commitment to providing future-proof, modular, and practical solutions for vehicle development and industrial test applications.
The post Universal Control Solution for Endurance Tests of Vehicle Components appeared first on ELE Times.
Vishay Launches High-Accuracy Automotive Light Sensors
Vishay Intertechnology, Inc. expands its optoelectronics portfolio with the introduction of two Automotive Grade PIN photodiode ambient light sensors that deliver enhanced optical accuracy and long-term reliability in harsh environments. AEC-Q102 qualifies; the Vishay Semiconductors VEMD4210FX02 and VEMD5525FX02 feature spectral sensitivity closely matched to the human eye response with a peak wavelength of 530 nm and no infrared (IR) bump.
The devices are designed for automotive applications, including automatic light control in Center Information Displays (CID), Head-Up Displays (HUD), and Rain Light Tunnel (RLT) systems, as well as backlight dimming in industrial equipment. By eliminating the IR bump in the spectral sensitivity curve, the devices ensure precise visible light measurement without unwanted IR influence in these applications. In addition, the devices’ superior angular characteristics ensure stable spectral accuracy regardless of the angle of incoming lighting for consistent and reliable light measurement performance.
For space-constrained applications, the VEMD4210FX02 offers a typical reverse-light current of 0.014 μA and a sensitivity range from 470 nm to 610 nm in a compact 0805 package with a radiant-sensitive area of just 0.42 mm². For applications requiring enhanced sensitivity, particularly in low-light conditions, the VEMD5525FX02 offers a reverse-light current of 0.11 μA and a sensitivity range from 480 nm to 590 nm in a top-view QFN package with a large 7.5 mm² radiant-sensitive area. Both parts also feature wettable flanks for optical solder joint inspection.
RoHS-compliant, halogen-free, and Vishay Green, the sensors feature a moisture sensitivity level (MSL) of 4 in accordance with J-STD-020 for a floor life of 72 hours. The devices support lead (Pb)-free reflow soldering and operate over an ambient temperature range of -40 °C to +110 °C.
Device Specification Table:
| Part number | VEMD4210FX02 | VEMD5525FX02 |
| Typical reverse light current at EV = 100 lx (µA) | 0.014 | 0.11 |
| Angle of half sensitivity (°) | ± 52 | ± 58 |
| Range of spectral bandwidth (nm) | 470 to 610 | 480 to 590 |
| Wavelength of peak sensitivity (nm) | 530 | 530 |
| Package | 0805 | Top-view QFN |
| Dimensions (mm) | 2.0 x 1.25 x 0.7 | 5.0 x 4.0 x 0.9 |
| Radiant sensitive area (mm²) | 0.42 | 7.5 |
The post Vishay Launches High-Accuracy Automotive Light Sensors appeared first on ELE Times.
I made a simple 5 bit CPU that works with my 3 bytes of SRAM
 | submitted by /u/KrisMakesRandomStuff [link] [comments] |
EEVblog 1755 - Tolicore Femtoammeter TEARDOWN + REVERSE ENGINEER
From GAA to 3D Stacked FET: Expanding the Transistor into the Third Dimension
 | submitted by /u/Linker3000 [link] [comments] |
MIT Lincoln Lab buys Aixtron Hyperion 300mm MOCVD systems
Relationship between architecture and validation in system design
In high-volume consumer electronics, the margin between a feature and a failure mode is increasingly narrow.
As the architecture of form-factor constrained devices becomes more tightly integrated, the traditional modularity of hardware systems breaks down. Thermal behavior, RF performance, mechanical tolerances, and power delivery are no longer independent domains because small sub-system shifts cascade across the entire system.
When the thermal envelope of a system-on-chip (SoC) directly impacts the signal integrity of a nearby 5G antenna, or when a mechanical tolerance stack-up in a camera module creates parasitic capacitance on a display flex, validation can no longer be a post-design activity.
Today, the complexity of modern hardware validation is a direct consequence of early architectural decisions. As highlighted in McKinsey’s analysis on handling technical complexity, upfront product architecture misjudgements inevitably compound into severe downstream bottlenecks during the integration phase.
Cost of coupling: Architectural debt
In loosely coupled systems, validation scales linearly. Components can be tested independently, and integration risk is bounded. However, in tightly coupled systems, validation scales exponentially. For instance, in a loosely coupled architecture where the display, power management IC (PMIC), and RF modem operate within encapsulated boundary interfaces, validating state transitions across 4 operating modes requires an additive test matrix, totaling 12 unique test permutations.
However, when these 3 subsystems are tightly coupled, where transient voltage drops from a 5G RF burst could force dynamic updates to the display’s refresh logic and PMIC power rails, the test matrix explodes up to 48 unique test permutations for the same feature set, a 4x increase in test overhead.
Decisions to integrate a new module, compress an existing subsystem, or optimize the overall system introduce a new set of interdependencies to be de-risked. For example, a custom-design ASIC may require entirely new silicon-level validation infrastructure in collaboration with the chip manufacturer before meaningful system integration can begin.
In parallel, a complex PCB stack-up can increase the risk of parasitic coupling and desense, requiring exhaustive EMI testing. Furthermore, high-density packaging may compress thermal margins, necessitating sophisticated workload throttling to maintain performance metrics.
When architecture teams prioritize power, performance, and area (PPA) without explicitly accounting for validation and verification, they incur architectural debt. This simply refers to an acceptance of long-term trade-offs (the debt) in exchange for immediate product architecture wins.
This debt is often paid off during engineering validation builds and volume ramp. Gamliel and Barron (2026) empirically analyzed high-complexity new product introduction (NPI) environments and found that early organizational and architectural blind spots are the primary upstream drivers that later materialize as volatile downstream ‘non-quality costs,’ directly yielding schedule deviations, material waste, and collapsed margins during volume manufacturing transitions.
Figure 1 In loosely coupled systems, validation effort grows linearly with added complexity. In tightly coupled systems, interdependencies cause exponential growth. The gap is architectural debt. Source: Author
Supplier co-development: Moving handshake upstream
At flagship scale, global supply chain provides co-engineering support in addition to its legacy logistics execution function. Supply chain is tightly integrated with system architecture. Here, a common failure mode in NPI treats suppliers strictly as a black box expected to deliver components to fixed specifications.
Meanwhile, in tightly coupled systems, critical risks are bound to emerge from sub-components within the system. Mitigating these risks require moving validation alignment upstream and creating an earlier validation handshake during system architecture. This includes:
- Joint validation planning between system teams and suppliers to align on defining success at component and system levels.
- Infrastructure sharing where suppliers are provided with realistic system conditions, enabling them to test and de-risk components in system-level simulation models.
- Transparent yield modeling between system teams and suppliers to accommodate the supplier’s manufacturing variance in system design.
If this handshake happens later, validation becomes reactive. If earlier, architecture becomes more robust and more tolerant to real-world variations.
Validation infrastructure as a design tool
In leading programs, the minimum viable product (MVP) for validation comes much earlier than the first system hardware. Validation infrastructure is set up to serve as a de-risking tool prior to the first prototype build. This infrastructure includes the employment of virtual systems that enable high-fidelity simulations for validating system behavior in digital twin environments.
Digital models can uncover thermal coupling, signal integrity issues, and power interactions early in the design cycle. Modular breadboards and development platforms also enable early development of firmware, software, and tests while final mechanical enclosures are still being designed.
Additionally, pre-silicon emulation allows teams to explore system behavior early in the loop with accelerated simulation layers, even before physical prototypes exist. Pre-silicon environments allow software and power-state validation before tape-out. This is particularly essential because silicon tape-out schedules often come in advance of overall system readiness.
By the time the first “steel-tooled” builds are available, most integration risks should already be understood, bounded, or mitigated. Programs that rely on physical builds to discover system behavior are effectively deferring architectural decisions into the most expensive phase of development.
However, even with the right infrastructure, organizations still need a decision framework to ensure validation is treated as a first-class architectural constraint. That’s where governance comes in.
Governance: Where architecture and validation converge
Enforcing validation as a first-class architectural priority is more of a leadership mandate than a technical hurdle. System engineering program managers and technical leaders must establish the structural authority to elevate validation readiness to a non-negotiable, first priority directive within early architectural decision-making.
When new features are proposed, the validation path required to support them must also be considered. If a design introduces dependency on new validation infrastructure that cannot be developed within the program timeline, an architectural risk and debt has just been introduced.
Validation should be shifted from a milestone to a gating function. Architectural reviews should explicitly evaluate validation complexity, infrastructure readiness, and integration risk alongside performance and cost. Below is a simple governance checklist:
- Is the validation path defined before architecture sign-off?
- Are suppliers’ validation plans aligned with system-level requirements?
- Is there a rollback option if validation reveals unmanageable complexity?
Without this shift, teams unintentionally accept risk that will surface later as schedule slips, yield instability, or late-stage redesign.
Figure 2 With making validation a gating function, every architectural decision must include a credible validation plan before approval. Source: Author
From validation to architecture
As systems become more integrated, the relationship between architecture and validation becomes inseparable. Validation is no longer the mechanism that ensures a design works. It’s the lens through which architectural risk is exposed.
Organizations that recognize this shift can realize design systems that are inherently more testable, more manufacturable, and more predictable at scale. And those that don’t, continue to discover risk at the point where it’s most expensive to resolve.
When you sit in an architecture review next time, ask one question before approving any new feature: ‘What is the validation path, and is it ready today?’ If the answer is anything but ‘yes,’ you are already in debt.
Ayokunle Oni is a system engineering program manager at Apple, where he helps coordinate the iPhone hardware design and engineering process across cross-functional teams. He specializes in system integration and validation and has led complex engineering programs from concept through production, working closely with global manufacturing and vendor partners.
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- Basics of Bench Silicon Validation – PCB Passives
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- Design Constraint Verification and Validation: A New Paradigm
- How system-level validation compresses schedule risk in device design
- Design-Stage Analysis, Verification, and Optimization for Every Designer
The post Relationship between architecture and validation in system design appeared first on EDN.
A pot of many colors
Here’s a neat and novel way of using a long-tailed pair to drive not just two but three LEDs.
As everyone knows, rainbows always have pots of gold at their ends. This Design Idea reverses that, starting with a pot (no gold, alas) and ending with a rainbow.
Wow the engineering world with your unique design: Design Ideas Submission Guide
Bi-color LEDs can be useful animals for indicating circuit balance or battery condition, and the common-cathode types are easily driven with a long-tailed pair, with various proportions of red and green giving oranges and yellows. Tri-color (RGB) types, capable of producing a much wider spectrum, usually need three separate drive sources.
So what happens if we drive drive the red and blue LEDs with a modified long-tailed pair, adding in the green as some function of the other two? Read on to find out.
Figure 1 shows the first attempt.
Figure 1 The red and blue LEDs are driven by a long-tailed pair and controlled by pot (potentiometer) R4, whose wiper voltage varies according to its position and is used to control the green LED’s drive, producing a decently wide spectrum.
Figure 2 gives plots of the three LED currents as calculated by LTspice, which did most of this Design Idea’s heavy lifting. When pot R4’s wiper is at either end of its travel, Q1 or Q2 will be fully on and the voltage across R5 will be high (~3 V). When it’s centered, Q1 and Q2 and thus the red and blue LEDs will be largely off, but the top of R5 will fall to ~1.7 V. That 3 V is enough to hold the Darlington-pair current source Q3/4 off, while reducing it towards 1.7 V gently turns it on, proportionately driving the green LED.
Figure 2 This graph plots the LED currents against pot rotation.
This result is optimized, meaning it’s the best that Figure 1 can do, but is still rather unsatisfactory because the drives for intermediate colors—oranges, lemons, and the interesting cyans and turquoises—are badly matched, giving rather sludgy shades compared with the pure ones. Breadboarding confirmed the problem.
Take two
Some thought and a rearrangement of the circuit gave Figure 3.
Figure 3 Rearranging the circuit and adding an op-amp to drive the green LED gives better, more linear control of the LED currents.
The pot now gives a lower, more linear, drive to Q1/Q2, the green-controlling voltage being picked off from the tail resistor R1. Obviously, the voltage across R1 is at a maximum with the pot at either extreme and falls to near zero with the pot centered, when red and blue LEDs are off. A1 amplifies that voltage and drives the green LED through R7.
Figure 4 shows the sim plot, which implies that it should work much better when built…
Figure 4 The response of the revised design has more linear curves, giving a smoother spectrum.
…as indeed it does! Owing to brightness mismatches in my 10 mm diffused LEDs (common to most tri-color types) I had to drop the green drive by increasing R7 to 1k2. That drive is also affected by LED1_G’s forward voltage; turning A1 into a proper current source worked well but added more components and didn’t look any better. After fixing R7, the brightness was fairly constant over the whole available spectrum.
A rainbow, or only a portion thereof?Ah, that weasel word “available”! This can never quite match a real rainbow or other white-light spectrum because the deepest reds and the furthest indigos and violets are outside its range—even rainbows have rather a limited palette compared with a full RGB mix. Swapping the LEDs around gives some interesting spectra (to use the word loosely) in other parts of the chromaticity diagram.
A digital departureWhile the basic analog circuit may find applications where three interdependent values need to be controlled by a single pot, there is a better way to drive LEDs like this: use a micro that can read the voltage tapped from a pot and generate appropriate PWM signals to drive the LEDs, perhaps indirectly should you need kilo-lumen rainbows. This approach would also allow direct voltage control of the effects.
I have some solar-powered garden lights that use this principle to span the whole (again, “available”) RGB gamut, using what looks like my my favorite PIC 12F1501 nanocontroller containing a mere 64 bytes of RAM, but more peripherals than pins. Internal demons crank three virtual pots up and down, although low-powered operation means a low and flickery PWM rate. Time to put on the coding hat—waterproof, because rainbows imply rain—and have some digital fun doing it properly.
—Nick Cornford built his first crystal set at 10, and since then has designed professional audio equipment, many datacomm products, and technical security kit. He has at last retired. Mostly. Sort of.
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The post A pot of many colors appeared first on EDN.
Women in engineering: Helen Duncan’s journey from design engineer to CEO
Helen Duncan’s father took her to a trade show in London when she was 10 years old. She was fascinated by watching CNC machines make large mechanical parts without human involvement. Her father worked in mechanical engineering as a skilled toolmaker and later as an estimator, and he encouraged Helen to help him with car maintenance.
Helen Duncan is CEO of Blueshift Memory, a Cambridge, England-based design outfit that optimizes memory architecture to more efficiently handle large datasets and time-critical data. Its Cambridge Architecture for stored-program machines is designed to replace the current modified Harvard architecture and to overcome the traditional constraints of the von Neumann bottleneck.
Helen was talking to EDN on the eve of “International Women in Engineering Day,” which is celebrated on 23 June this year. When asked what motivated her to enter the engineering world, she pointed to physics being one of her favorite subjects in high school. “When we had to make an electric motor from scratch in a practical lesson, mine was the only one in the class that worked,” she recalled. “I was thrilled by this.”
At 13, Helen decided that electrical and electronic engineering was what she wanted to study. The more some of her teachers tried to discourage her, the more determined she became to pursue that course. “My wonderful physics teacher, Mr. Wood, a Star Trek fan, was unfailingly supportive though,” Helen acknowledged.
In the field
Helen joined the workforce in the late 1970s when only 1-2% of electronics engineers were women. “With a good degree, I had a choice of several jobs, and I accepted a position as an R&D engineer with Plessey, working on RF and microwave projects for both defense and commercial applications,” she told EDN.
Over there, direction-sensing Doppler radar modules for automatic door openers were an early design project. Later, she became a product engineering manager and hence the design authority for all the company’s microwave source products, including two mmWave subsystems for airborne radar. During those days, there was only one other female engineer working alongside Helen: a Turkish lady a few years older than her, who had a PhD from Oxford University.
Figure 1 Helen Duncan began her design work on RF and microwave projects for defense and commercial applications.
By the mid-1980s, Plessey had recruited several new graduate engineers, and surprisingly, women then made up around 25% of the engineering department, much more than the national average, which was still less than 10% at that time. “I like to think that, as I was a member of the interview panel, they were encouraged to see me as a role model who was already in a management position,” Helen recounted.
Mistaken as a caterer
When asked about the challenges of being a minority in those early days and the advantages as well, Helen said she was incredibly lucky to have some very supportive managers. “Within the company, I was unfailingly treated with respect.”
However, sometimes it was more of a problem with outsiders meeting her for the first time. Helen recalled a senior Royal Air Force officer visiting with a defense procurement team; he mistook her for a member of the catering staff, but then instantly recognized his mistake when she stood up to give a presentation.
When asked for a piece of advice she could give to young female engineers entering the electronics industry, Helen said: Believe in yourself and your abilities, and don’t allow others to undermine you or try to mansplain. “Always remain open to any opportunities that may come along, as your career may not always take the course you would expect,” she added.
Figure 2 EDN spoke with Helen Duncan, CEO of Blueshift Memory, on the eve of the “International Women in Engineering Day,” observed on June 23, 2026.
Career advice for female engineers
EDN concluded the talk with Helen by asking her which areas and disciplines female engineers should consider for long-term career prospects. “In general, I would say that no disciplines are off limits for female engineers,” she said. “However, it can be easier to progress in some of the areas that require better communication skills or a more consultative management style.”
She recalled her career trajectory over the years: she has worked in marketing at both Plessey and Rohm, and then in journalism as editor-in-chief of Microwave Engineering. “I have also been a semiconductor market analyst, a technical conference organizer, and a marketing consultant,” she said. “And I managed some of these roles concurrently.”
Most recently, Helen was headhunted for a marketing role at Blueshift Memory and later became CEO. Blueshift targets its smart memory architecture at CPU vendors, AI chip companies, and memory manufacturers; it can be used in combination with GPUs or AI accelerators, or anywhere the von Neumann bottleneck is a problem.
Figure 3 Blueshift Memory appointed Helen Duncan as its CEO in October 2024.
My career has been full of surprise opportunities and unexpected role changes, but it’s been an exciting journey,” she concluded. “And if I were starting today, I wouldn’t change anything.” That’s quite a career statement.
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- A Female Analog Designer Shares Traits for Career Success
- Blueshift Breaks Memory Wall in Data-Intensive Applications
The post Women in engineering: Helen Duncan’s journey from design engineer to CEO appeared first on EDN.
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