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Agilex 9 FPGAs power COTS VPX boards

Altera has partnered with Mercury Systems and VadaTech to expand its Agilex 9 FPGA ecosystem with COTS VPX boards for mission-critical defense platforms. These solutions integrate Agilex 9 medium-band Direct RF FPGAs into VPX architectures, including SOSA-aligned OpenVPX, to help defense customers accelerate time-to-market, reduce SWaP, and enable flexible software-defined RF capabilities.

The Agilex 9 FPGAs combine RF data converters, FPGA fabric, and high-speed transceivers into a unified, programmable architecture, enabling real-time processing of large volumes of RF data at the edge. This integration supports distributed, multi-domain operations that require rapid decision-making and adaptation to changing mission requirements. The devices deliver the bandwidth, performance, and I/O needed for demanding embedded applications such as adaptive radar, cognitive electronic warfare, and secure, software-defined communications.
Mercury Systems’ DRF5660 boards and VadaTech’s VPX540 boards with Agilex 9 Direct RF AGRM027 FPGAs are available for order today.
The post Agilex 9 FPGAs power COTS VPX boards appeared first on EDN.
Value DSCs streamline embedded control

Digital signal controllers (DSCs) in Microchip’s dsPIC33CK Value Line provide real-time control for cost-sensitive designs. Starting at $0.51 each, they offer consistent pricing regardless of order size. The 16-bit controllers deliver 100-MHz deterministic processing, high-resolution PWM, and a 12-bit ADC supporting motor control, precision sensing and control, and touch/HMI applications.

A balanced set of peripherals helps reduce external component count, PCB footprint, and overall BOM cost. With flash memory ranging from 32 KB to 256 KB and compatibility across the dsPIC33CK family, the Value Line DSCs enable scalability and migration to future designs. The devices integrate a 12-bit ADC capable of up to 2 Msamples/s, four PWM pairs with resolution down to 2 ns, and on-chip analog comparators with a 12-bit DAC. Communication interfaces include CAN FD, LIN, SENT, UART, SPI, and I2C.
To accelerate evaluation and development, Microchip offers the dsPIC33CK Value Line Curiosity Nano evaluation kit with an onboard debugger. The evaluation platform supports the Curiosity Nano base for Click Boards and a touch adapter board for touch applications. A motor control DIM is also available for rapid prototyping of motor control designs.
Value Line DSCs are available directly from Microchip, its sales representatives, or authorized distributors.
The post Value DSCs streamline embedded control appeared first on EDN.
RF tool captures reusable design workflows

Keysight’s RF Circuit Simulation Professional software now enables engineers to document their design workflow on an executable whiteboard. The software replicates design decisions while capturing simulations, optimizations, decision trees, and parameters derived from prior analyses. Each step generates editable Python code that can be saved, shared, replayed for design reviews, and redeployed across the Keysight Advanced Design System (ADS), Cadence Virtuoso, and Synopsys Custom Compiler environments with full design data traceability.

Design teams often face workflow inefficiencies, simulation bottlenecks, and knowledge-transfer challenges. Engineers can build workflows visually on an executable whiteboard while the software automatically generates corresponding Python scripts. The platform executes simulations, optimizations, and design decisions in sequence, with support for decision-based loops and parameter settings.
Each workflow becomes a repeatable methodology that can be shared across teams, reused, and driven by AI. Captured workflows help preserve RF design expertise while creating structured design data that can support future AI-driven automation and training. Design review and tapeout tasks that previously required manual configuration now execute automatically.
RF Circuit Simulation Professional
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Buck controller streamlines in-vehicle USB charging

Diodes’ APK43070Q synchronous buck controller integrates a USB Type-C PD 3.1 source controller, simplifying automotive single- and multi-port charging designs. Operating from a 4-V to 36-V input, it enables USB Type-C charging up to 140 W. The device supports USB extended power range (EPR) and adjustable voltage supply (AVS) up to 28 V, along with standard power range (SPR) and programmable power supply (PPS) up to 21 V.

The constant-frequency controller features integrated drivers, optimized dead time, and elevated gate drive voltage for efficient mid- to high-power charging using external N-channel MOSFETs. This allows flexible MOSFET selection to balance thermal performance and power loss. A VIN DC pass-through mode further improves converter performance by enabling the high-side MOSFET to act as the VBUS switch, eliminating the need for an additional output switch.
An I2C interface with a controller/target addressing scheme enables power sharing across up to eight USB Type-C ports via resistor selection without an external MCU. The APK43070Q also includes overvoltage, overcurrent, undervoltage, and thermal protection.
The APK43070Q is priced at $0.80 each in 1000-unit quantities.
The post Buck controller streamlines in-vehicle USB charging appeared first on EDN.
Low-noise USB scopes deliver 16-bit resolution

Pico Technology has launched the PicoScope 5000E series of USB-C oscilloscopes for analog, digital, and mixed-signal debugging. The four-channel scopes provide true 16-bit resolution with bandwidths to 200 MHz, sample rates to 2.5 Gsamples/s, and up to 1 GS of memory. PicoScope 5000E Plus models also offer a switchable 8-bit high-speed mode that raises bandwidth to 500 MHz, sample rates to 5 Gsamples/s, and memory to 2 GS.

With an ultra-low-noise front end, the oscilloscopes achieve a noise floor below 22 µV RMS and total harmonic distortion better than -73 dB. The resulting dynamic range helps reveal small-amplitude components, ripple, distortion, and other anomalies that lower resolution or noisier instruments can miss.

The compact, portable scopes connect to a host computer through a SuperSpeed USB 3.0 Type-C interface. For debug and validation, Pico 7 software provides more than 40 serial protocol decoders, advanced math channels, automated measurements including power analysis, multi-capture analysis, and measurement and mask limit testing. The Pico SDK supports custom application development using C, C#, C++, Python, MATLAB, and LabVIEW.
The PicoScope 5000E series is available in four-channel and 4+16-channel mixed-signal oscilloscope variants, with bandwidth options from 60 MHz to 500 MHz depending on model and operating mode. Units are sold through authorized distributors worldwide and directly from Pico Technology.
The post Low-noise USB scopes deliver 16-bit resolution appeared first on EDN.
🏆 Міжнародний конкурс студентських наукових робіт зі штучного інтелекту 2026
КПІ ім. Ігоря Сікорського запрошує взяти участь у Міжнародному конкурсі студентських наукових робіт зі штучного інтелекту. Учасники зможуть представити власні дослідження у сфері ШІ та долучитися до міжнародної наукової спільноти.
EPC targets high-density motion systems with GaN ePower Stage technology
Navitas collaborates with NVIDIA MGX Ecosystem to accelerate 800VDC AI infrastructure
From road to rack: 800V EV innovations redefining AI data-center power architecture
Finished DIY Vacuum Tube Oscilloscope
| On the bottom left it is shown next to its accompanying vacuum tube power supply, not a single semiconductor used in the whole setup. Wiring is horrible, and its performance reflects that. But at least it looks nice. Uses a 2" diameter 902 CRT, and is based mostly on a 1945 RCA schematic for this tube. The CRT only runs at <600V (schematic specifies 577V, mine only runs on ~400V), which is remarkably low for a CRT but it definitely still hurts. Uses two 6SJ7 pentodes for vertical and horizontal amplification with a Type 884 thyratron for sawtooth generation. Has x-y mode and internal/line/external sync. Rectification is done with a Type 80 for B+ and a 6AU4 for the negative CRT supply (grounded anode). The tube could maybe use some magnetic shielding and I am trying to figure that out, but for now I just keep the power supply away from it to eliminate the interference. Whole thing uses a little over 60W when running and is fused accordingly. This is by far my highest-effort electronics project ever, and I am very glad to be done with it! I started this project over a year ago before, I got my real oscilloscope. Whadaya think? [link] [comments] |
🎥 КПІ ім. Ігоря Сікорського об’єднав Київ і Кіото піснею
Уже втретє з початку повномасштабного вторгнення Міжнародний хор Кіото організовує на День Києва пісенний телеміст між містами-побратимами — як знак підтримки киян і солідарності з Україною.
Figured out why my Xbox controller adapter burned me
| It wasn't working, so unplugged it and the metal was hot as hell. So took it apart, soldered some leads for power and gave it some juice. Got a lot hotter than I was expecting. Resistor was reading as .5Ω [link] [comments] |
I’ve never seen capacitors that look like this before.
| I’m a graduate electrical engineer with over 12 years of experience in electronics. I’ve worked on a wide range of projects, and I thought I had seen most things by now… but I’ve never seen capacitors that look like this. [link] [comments] |
Made this water level indicator as my college project.
| submitted by /u/Public_Ice_736 [link] [comments] |
Triply simply sequence supply voltages

This circuit design for power supply on/off sequencing uses Schmidt triggers for triple-positive-rail timing purposes.
Recent design ideas have explored the utility of timed power supply ON/OFF sequencing and provided circuit designs to implement it. Figure 1 shows a simple topology using Schmidt triggers for timing the turn ON and OFF of triple positive supply rails. Here’s how it works.
Wow the engineering world with your unique design: Design Ideas Submission Guide

Figure 1 This significantly simple supply sequencing scheme leverages Schmidt triggers.
Switching action begins with SPDT S1 in the OFF position which holds the C1 and C2 timing caps discharged. The latter holds U1 pin 1 at 15v and therefore its pin 2 and the NFET Q2’s gate at zero, forcing the 5Vout rail OFF.
Meanwhile, C1’s discharged state holds U1’s pins 3 and 5 low so pins 4 and 6 sit high. The former holds enhancement mode PFET Q1 and the 15Vout rail OFF, while the latter does the same for level shifter Q3, PFET Q4, and the 24Vout rail.
Therefore no power flows to the connected loads. Yet, at least. Figure 2’s left side graphs the sequence of events initiated by actuating S1.

Figure 2 This plot shows power sequence timing when S1 is flipped ON and later flopped OFF.
C2 connects to ground through R3, quickly charging it to the Schmidt trigger low-going threshold in about R3C2 = 1mS. This inverts U1 pin 2 to 15v, placing a net forward bias of 15 – 5 =10V on NFET Q2, turning it and the 5Vout rail ON. Thus they will remain as long as S1 stays ON.
Meanwhile, reset of C1 has been released, allowing it to begin charging through R1 + R3. The first thing that happens occurs at the end of T1 when U1 pin 3 reaches the ~9V Schmidt threshold. Since the timeout duration is proportional to C1, any desired interval can be chosen with an appropriate RC product. U1 pin 4 then snaps low, PFET Q1 turns ON and 15Vout goes active.
Of course C1 continues to charge, so at T2 U1 pin 5 also reaches its triggering threshold. Then its pin 6 snaps low, turning ON Q3, Q4 and 24Vout. The ratio R4 = 10 R5/(15 – 0.7) was chosen to apply an adequate and safe ~10V drive to Q4’s gate, independently of 24Vin. The S1 flip ON sequence is now complete.
The right side of Figure 2 shows what happens when S1 subsequently flops OFF. First, C1 is promptly discharged through R3, turning OFF Q1, Q3, Q4 and thereby 15Vout and 24Vout, putting them and whatever they power to sleep. Meanwhile C2 begins ramping up, taking T3 to get to U1’s threshold. When it completes the trip, pin 2 goes low, turning Q2 and 5Vout OFF.
Turnoff sequencing is therefore complete. Nighty night.
Details of the design include D1 and D2. Their purpose is to make the sequencer’s response to losing and regaining of the input rail voltage orderly, and to do it regardless of whether S1 is ON or OFF. If S1 is OFF, then all output rails remain low and (a safe) nothing occurs when the supply voltages return. If it’s ON, then a normally timed (and therefore safe) power-up sequence is executed.
Note that the MOSFETs should be chosen for adequate voltage and current handling capacities. Because Q1 has 15v of gate drive and Q2 and Q4 get 10v, none need be sensitive logic-level types.
Okay. But what if you also need to sequence a negative supply rail? Figure 3 shows how.

Figure 3 This power switching circuit works with a negative rail.
When the U1 inverter’s input rises above the Schmidt trigger voltage, its output snaps low, causing the 2N3906 to pass Ic = (+15Vin – 0.6)/15k = 0.96mA. This develops a 10.6V that’s independent of –Vin across the 11k resistor, saturating the NFET. If symmetrical polarity rails (e.g. +/-15v) are needed, Figure 3 can be added to Figure 1 to provide the negative side with no other modifications required.
Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974. They have included best Design Idea of the year in 1974 and 2001.
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Ayar Labs joins NVIDIA NVLink Fusion ecosystem to bring CPO to rack-scale AI infrastructure
Rohde & Schwarz Secures Critical Certification for Next-Gen eCall Compliance
The hybrid eCall test specification EN 18052 states that a hybrid system must combine different transmission paths and protocols to make sure an eCall reliably reaches its destination. In practice, this means a vehicle uses NG eCall functions (IP/IMS-based voice and data over 4G/5G) but can automatically fall back to available classic CS eCall (2G/3G) transport paths when coverage or service quality degrades. Manufacturers need to validate hybrid implementations to ensure they can trigger calls, transmit the minimum set of data (MSD), maintain GNSS positioning, and deliver intelligible voice quality across multiple network scenarios, including voice over New Radio (VoNR), voice over LTE (VoLTE), and circuit-switched fallback. Tests must demonstrate that a system remains robust during handovers and under degraded radio conditions, while also complying with relevant CEN, ETSI, 3GPP, and national requirements.
“We use the solution for functional tests and protocol conformity tests as well as for the type-approval of In-Vehicle Systems (IVS) that implement hybrid eCall and NG eCall,” says Thomas Reschka, Senior Technical Consultant at cetecom advanced.
Rohde & Schwarz has updated its eCall evaluation solution, CMX-KA09x, to support compliance with EN 18052:2025 and EN 17240:2024+A1:2026. The CMX-KA099 option completed Public Safety Answering Point (PSAP) test scenarios in accordance with EN 18052:2025, while the CMX-KA098 option completed PSAP test scenarios in accordance with EN 17240:2024+A1:2026. This marks an important step toward meeting European requirements for NG eCall test systems. The test environment allows the simulation of the real world mobile network conditions and the emulation of various network scenarios. This is a significant advantage in preparing for certifications or the market launch of new vehicle models.
The post Rohde & Schwarz Secures Critical Certification for Next-Gen eCall Compliance appeared first on ELE Times.
XpressConnect PCIe 6.0: Solving AI Data Center Latency
As AI workloads continue to scale, the data center architects show limitations by signal reach and rising latency, leaving valuable memory resources underutilized across large GPU clusters. These challenges boost as interconnect speeds increase. At 64 GT/s (giga transfers per second), signal integrity limitations can restrict system scale and burden server architectures. In response, Microchip Technology releases XpressConnect PCIe 6.0 and CXL 3.1 retimers to enable memory expansion and resource disaggregation in large-scale AI fabrics.
The retimers extend signal reach beyond conventional PCIe Gen 5 and Gen 6 electrical limits, enabling more flexible system designs across complex baseboards, riser cards, and cabled interconnects. The retimers are engineered to help address these challenges by enabling higher-bandwidth connectivity while supporting the stringent thermal requirements of modern AI fabrics that require power budgets. XpressConnect retimers achieve a pin-to-pin latency of less than 12 ns, approximately 80% lower than PCIe 6.0 specifications. This low-latency performance helps improve utilization of AI accelerators and GPUs by reducing data stalls in high-density AI clusters.
“AI data centers are increasingly constrained not by compute, but by the ability to move data efficiently across the system. As PCIe 6.0 pushes speeds to 64 GT/s, signal reach and latency become critical design challenges,” said Brian McCarson, corporate vice president and GM of Microchip’s data center solutions business unit.
Our XpressConnect retimers are designed to act as the high‑performance nerve center of the AI server, helping customers build more scalable, power‑efficient fabrics by reducing latency and improving connectivity across dense GPU clusters. This system‑level approach allows data center architects to reclaim underutilized resources and improve overall platform efficiency at scale.
The XpressConnect retimers round out Microchip’s data center portfolio and are engineered to work alongside the company’s 3-nm Switchtec PCIe Gen 6 switches, Adaptec SmartRAID controllers and Host Bus Adapters (HBAs), and Flashtec NVMe controllers, helping enable a pre-validated, interoperable fabric. Microchip’s XpressConnect PCIe Gen 6 and CXL 3.1 retimers can integrate with PCIe Gen 3, Gen 4, and Gen 5 platforms as required, helping reduce time to market. The retimers also connect into Microchip’s ChipLink diagnostic ecosystem, delivering a unified graphical user interface for real-time 2D eye capture and four-level pulse amplitude modulation (PAM4) telemetry. These capabilities help data center operators monitor link health more effectively and simplify troubleshooting, which can help reduce the total cost of ownership.
Engineered as an industry-standard, drop-in solution, XpressConnect retimers are designed to help reduce the risk of single-vendor dependency for hyperscalers. Additionally, the devices support flexible link bifurcation configurations (1×16, 2×8, and 4×4) and align with widely adopted retimer footprint guidelines, while providing enterprise-class features such as hot-plug support and end-to-end data integrity. Visit the website to learn more about Microchip Technology’s data center solutions for high-performance compute, storage, and connectivity.
Development Tools
Microchip’s ChipLink diagnostic tools offer comprehensive debug, diagnostics, configuration, and analysis through an intuitive graphical user interface (GUI). ChipLink connects via in-band PCIe or sideband signals such as UART, TWI, and EJTAG, enabling flexible, efficient monitoring and troubleshooting throughout design and deployment.
The post XpressConnect PCIe 6.0: Solving AI Data Center Latency appeared first on ELE Times.
University of Texas at Dallas and Attolight launch new demo lab for wide-bandgap R&D
BTL Deploys Taiwan’s First CTIA-Compliant OTA Test System with Rohde & Schwarz
Rohde & Schwarz supplies the independent test house BTL Laboratory in Taiwan with a full R&S TS8991 OTA test system that meets CTIA Certification standards. Plus, the company’s experts give hands‑on support throughout the necessary accreditation audits. This collaboration makes BTL the first test house in the region to provide its customers with comprehensive over-the-air testing services, including certification of wireless devices in line with CTIA Certification OTA requirements based on a Rohde & Schwarz test system.
BTL relies on Rohde & Schwarz to install a full CTIA Certification-compliant turnkey OTA test solution in one of its prominent testing and certification laboratories in Taiwan. The project covers the R&STS8991 over-the-air test system, related measurement software, a ready‑to‑use third-party test chamber, and a positioner from a single source. Furthermore, Rohde & Schwarz experts provide guidance and support on-site throughout the process of the two necessary accreditation audits performed by TAF (Taiwan Accreditation Foundation) and CTIA Certification, to guarantee measurement proficiency and accuracy.
Rohde & Schwarz and BTL collaborates closely to make sure the test chamber and its supporting infrastructure provide an interference-free test environment, a requirement for reliable measurements. The single‑source arrangement simplifies procurement for the test house in comparison with solutions that rely on several vendors.
As the first test lab in Taiwan using the R&S TS8991 with CTIA Certification. BTL now offers OTA measurements on wireless devices that use 2G, 3G, 4G, 5G, Wi‑Fi, and Bluetooth technology, especially notebooks and laptops. Furthermore, by keeping it compatible with new wireless standards, A‑GNSS, it upgrades the measurement software of the test system. By bringing in expertise in antenna measurement.
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