Microelectronics world news

• DIRK (German Investor Relations Association) awards Infineon first place for best Investor Relations among DAX 40 companies
• IR Impact has honored Infineon with first-place rankings at the European level in the categories “Best Overall Investor Relations (Large Cap)” and “Best Investor Relations Officer (Large Cap)”
• Awards confirm the quality and credibility of Infineon’s capital markets communication

Infineon Technologies AG receives several awards for its Investor Relations (IR) activities. At the German Investor Relations Award presented by DIRK, the German Investor Relations Association, the Infineon IR team achieve first place for best Investor Relations among all DAX 40 companies for the first time, jointly with Siemens Energy AG. Infineon also ranked third in the categories “Best ESG Communication by a Company” and “Best IR Communication by a Head of IR”. The latter award was presented to Alexander Foltin, Head of Finance, Treasury & Investor Relations, who accepted the prize together with Chief Financial Officer Dr. Sven Schneider at the ceremony in Frankfurt on 30 June.

Just two weeks earlier, the team had already been recognized at the 2026 IR Impact Awards – Europe. Infineon’s entire IR team ranked first in the category “Best Overall Investor Relations (Large Cap).” Alexander Foltin and Daniel Györy, Team Lead Investor Relations, also jointly secured the top position in the category “Best Investor Relations Officer (Large Cap).”

“The strong recognition of Infineon’s Investor Relations work at national and international level confirms the high quality and credibility of our capital markets communication,” said Dr. Sven Schneider. “My sincere thanks go to the colleagues who continuously foster an open and transparent dialogue with our investors and analysts, particularly at a time marked by unprecedented growth opportunities and geopolitical challenges. We remain committed to shaping Infineon’s equity story, meeting the expectations of analysts and investors, and to maintaining a close and constructive exchange with the capital markets.”

The German Investor Relations Award is presented annually by Extel, WirtschaftsWoche and DIRK. The winners are determined based on Extel’s Developed Europe Executive Team Survey, which gathers independent feedback each year from thousands of buy- and sell-side professionals worldwide on the IR activities of listed companies.

The IR Impact Awards – Europe are presented annually by IR Impact and are among the most prestigious distinctions in the Investor Relations field in Europe. They recognize excellence in financial communications as well as in the dialogue between listed companies and the capital markets. Winners of the respective categories are determined by an independent survey of analysts and investors.

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The enterprise AI platform turns millions of engineering artifacts that run a plant into accurate, decision-ready data, delivering up to 85% extraction accuracy and full, audit-ready traceability

L&T Technology Services announces the launch of Ainfonix 4.0, a next-generation Engineering Intelligence platform for process industries. Unveiled at EI Live, LTTS’ flagship event that brings together analysts, industry leaders and engineering experts, Ainfonix 4.0 marks an important step in the company’s Enterprise AI and Engineering Intelligence strategy.

As industrial enterprises accelerate AI adoption, decades of engineering knowledge remain trapped in fragmented drawings, specifications, and technical records across disparate systems. Without trusted and accessible engineering data, organizations struggle to realize the full value of AI, automation, and digital transformation initiatives.

Ainfonix 4.0, developed in LTTS’ Sustainability segment, addresses this challenge by transforming engineering artifacts and multi-modal data into structured, asset-linked information that can be governed, searched and reused across the enterprise for faster and better decision-making. Built on decades of process industry expertise, the platform combines AI-powered extraction, engineering intelligence and human-in-the-loop validation to improve data quality, strengthen traceability and create a trusted foundation for engineering execution, operational visibility, and lifecycle performance. In early deployments, Ainfonix 4.0 has delivered up to 85% accuracy in technical data extraction, 30-50% faster artifact retrieval and review, and 100% audit-ready traceability, helping enterprises operate with greater speed, reliability, and control. LTTS was recently rated as a Leader in the ISG Provider Lens 2025 study for Enterprise Asset Management in the Oil & Gas Industry Service & Solutions (Americas).

Amit Chadha, CEO & Managing Director, L&T Technology Services, said, “Engineering Intelligence begins with trusted engineering data. While enterprises invest heavily in digitization, much of the engineering knowledge remains locked within disconnected engineering systems. Ainfonix 4.0 helps bridge that gap by transforming engineering information into structured, asset-linked intelligence that can be used across the asset lifecycle, from engineering and project execution to operations and maintenance. As organizations look to scale AI adoption, we believe trusted engineering data will become a critical competitive advantage, and Ainfonix 4.0 is designed to help clients unlock that value.”

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• Advance single-die solution with PQC (post-quantum cryptography) hardware accelerator
• Helps mobile device makers prepare for future security requirements while enabling rich consumer and ecosystem use cases.

STMicroelectronics introduces the ST54M, a secure mobile chip designed to help smartphone and personal electronics manufacturers meet upcoming quantum-ready security requirements while supporting a seamless user experience across connected services.

ST54M brings to the market a single-die device featuring an innovative hardware accelerator for post-quantum cryptography (PQC) with NFC, secure element and eSIM functionality, delivering a powerful future-ready solution for secure mobile connectivity and services. The solution supports a wide range of use cases, including contactless payments, transit ticketing, access control, digital identity, driving licenses, connectivity services, and digital car keys.

Future-proof protection for expanding mobile use cases

As mobile devices increasingly serve as trusted platforms for financial transactions, identity credentials, operator services, and secure access, product developers need solutions that combine multiple functions without compromising security, performance, or convenience. ST54M addresses this need by enabling OEMs and ecosystem partners to support multiple applications on one platform while preparing for the transition toward PQC.

The device is designed for use across personal electronics ecosystems involving mobile network operators, banks, governments, transit operators, car manufacturers, digital-wallet and service providers. It helps manufacturers create devices that maintain a stable, familiar user experience while meeting stronger long-term security expectations.

Arriving now, ST54M enables customers and partners to deliver post-quantum-ready implementations with enough time to meet demanding industry-driven market deployment requirements, which are expected to be mandated around 2030.

“With ST54M, we are extending our mobile-convergence platform to help customers address evolving security challenges while supporting the rich set of services users now expect from their devices,” said David Richetto, Connected Security Group VP, Division General Manager, STMicroelectronics. “By combining a PQC hardware accelerator with NFC, embedded secure element, and embedded SIM capabilities, ST54M gives device makers a secure path to start preparing next-generation mobile experiences.”

Engineered for security, integration, and RF performance

ST54M is an advanced single-die solution that integrates an NFC controller with a secure element supporting secure applications, eSIM, and NFC-compliant products. A key feature is its hardware accelerator for post-quantum cryptography algorithms, including ML-KEM and ML-DSA, supporting the transition from hybrid cryptographic approaches toward full post-quantum deployment. The hardware engine is designed to address emerging PQC requirements while helping protect against side-channel and fault-injection attacks and is the latest result from ST’s long-term commitment that also includes certified software libraries NesLib-PQML and X-CUBE-PQC in STM32 microcontrollers.

In addition to its security architecture, the device integrates a large memory capacity to support multiple applications and includes an enhanced RF front end. These capabilities can help improve performance with smaller antennas and single-ended configurations, support more stable reader-writer operation, and enable demanding use cases such as mobile Point-of-Sale (mPOS) and wireless charging. The platform has completed certification testing under Common Criteria 2022 EUCC and EMVCo, underscoring its suitability for security-sensitive mobile applications.

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Featuring AI-powered noise reduction, real-time audio transmission, compact lightweight design, Type-C connectivity, and seamless audio-video synchronisation for content creators

Portronics launches the VlogMate Neo, an AI-powered Type-C wireless microphone designed to help creators capture crystal-clear audio with ease. Built for vloggers, influencers, podcasters, educators, and mobile content creators, the VlogMate Neo combines intelligent audio processing with a compact, lightweight design to deliver professional-grade sound on the go.

Built for modern content creation needs, the VlogMate Neo features a dual-microphone system with AI-powered noise reduction, enabling it to effectively isolate voices while minimising unwanted background noise for consistently clear and natural audio across diverse environments. It also offers seamless plug-and-play functionality with Type-C smartphones, eliminating the need for additional apps or complex pairing processes.

Its lightweight and discreet form factor ensures comfortable wear during extended recording sessions, making it ideal for on-the-go creators. With real-time wireless audio transmission, the device delivers stable, low-latency performance for smooth and uninterrupted recording.

The VlogMate Neo supports audio-video synchronisation, ensuring perfectly aligned output for polished, professional-quality content. With a wireless range of up to 30 meters, creators can move freely while filming travel vlogs, fitness tutorials, interviews, presentations, and outdoor shoots without compromising audio quality.

Adding to its versatility, the microphone comes with a removable magnetic clip for quick attachment and flexible positioning. The included charging case protects the device and extends battery life, making it suitable for long recording sessions across multiple locations. Compatible with Type-C smartphones and devices, the VlogMate Neo offers true plug-and-play functionality, allowing users to start recording instantly without additional apps or complex setup procedures.

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Part 1 of this mini-series on advanced packaging outlined the basic comparison between CoWoS, wafer-scale integration, and CoWoP. It established why the package substrate, silicon wafer, and platform PCB represent different settings for future AI system bottlenecks.

Part 2 continues with the advanced CoWoP concept: pitch translation, transition patches, VRM and memory placement, Universal Chiplet Interconnect Express (UCIe) routing, and trusted realization governance.

The most challenging CoWoP part is not only whether the package substrate can be reduced or removed. The harder question is whether the architecture can physically transition from silicon-interposer pitch to platform-PCB pitch.

A wafer-level interposer, silicon bridge, or advanced redistribution structure operates in a fine-pitch environment. Micro-bumps, hybrid bonding, and high-density redistribution can exist in the tens-of-microns range. A platform PCB, even an advanced HDI board, operates at a much larger manufacturing scale, closer to hundreds of microns for practical solderable attach and board-level assembly.

This creates a major geometric discontinuity:

• Interposer/wafer-level interface: roughly tens of microns
• Platform-PCB attach interface: roughly hundreds of microns

Trying to force the primary interposer to absorb this entire fan-out directly would consume expensive interposer area, increase routing complexity, reduce yield, and weaken the economic argument for CoWoP. Therefore, the more practical CoWoP architecture may require an intermediate transition structure.

• Die/HBM → wafer-level interposer → transition redistribution patch → platform PCB

This patch is not simply another conventional package substrate. It’s a localized pitch-translation and CTE-management layer. Its role is to convert the silicon/interposer interface into a PCB-compatible attach interface while preserving electrical, mechanical, and thermal continuity.

A useful name for this structure is interposer-to-PCB transition patch, or more specifically, pitch-transition redistribution patch. This transition patch becomes the governed bridge between wafer-level precision and platform-level manufacturability.

Glass as a local transition patch

One possible implementation is a thin glass-core transition patch. A 2-3-layer glass-based transition patch could provide dimensional stability, CTE compatibility with the silicon/interposer side, and a controlled vertical path through TGVs. In this use case, glass is not being treated as a full package substrate replacement; it’s being used as a local transition bridge between wafer-level precision and board-level attach.

The concept is similar in spirit to wafer-to-package redistribution: expand the pitch in controlled stages rather than forcing one layer to absorb the entire geometric transformation. The transition could look like this in silicon die/HBM:

• Micro-bumps or hybrid bonding at fine pitch
• Primary wafer-level interposer
• First-stage redistribution
• Glass-core transition patch with TGVs
• Second-stage fan-out toward PCB pitch
• Platform PCB

The value of the glass patch is that it may preserve the CTE and dimensional-stability advantages near the interposer while providing a more manufacturable path toward the PCB. This matters because the hardest interface may not be the PCB alone or the interposer alone. It may be the transition between the two.

A glass transition patch can potentially help with:

• Fine-pitch registration
• CTE continuity near the silicon/interposer side
• Controlled vertical fan-out through TGVs
• Reduced interposer area devoted only to fan-out
• More stable pad alignment across thermal cycling
• A shorter vertical PDN path toward the platform PCB

But the glass patch also introduces its own realization needs:

• TGV reliability
• Glass/copper stress
• Attach fatigue
• Inspection accuracy
• Edge cracking
• Lifecycle drift

In other words, glass can make the transition more governable.

Organic as a compliant transition patch

Another possible implementation is a high-density organic transition patch. An organic patch may not match the dimensional stability of glass, but it may provide mechanical compliance. That compliance could help absorb shear stress between a rigid silicon/interposer structure and a larger platform PCB that expands, warps, and bends differently under thermal and mechanical loading.

This creates an important trade-off. A glass transition patch may offer stronger dimensional stability, stronger CTE matching to silicon/interposer, better fine-pitch registration, and a stronger TGV-based vertical transition. An organic transition patch may offer better mechanical compliance, more familiar substrate processing, and potentially better stress absorption between rigid silicon and PCB.

This trade-off is exactly why CoWoP should be treated as a governed realization problem, not only a layout concept. The transition patch becomes a decision point. The best material may depend on system size, thermal cycling, pitch requirements, power density, board stiffness, rework needs, reliability targets, and cost.

CoWoP as an interposer-to-patch-to-PCB corridor

With the transition-patch concept included, CoWoP becomes technically more credible. The architecture is not simply interposer directly attached to PCB, as shown below.

Interposer → controlled transition patch → platform PCB

It means CoWoP is not only a substrate-removal concept. It’s a pitch-transition, CTE-governance, and system-integration concept. The package substrate may be reduced, localized, or re-architected, but the realization burden does not disappear. It moves into a new corridor where the interposer-to-transition patch-to-platform PCB corridor must govern:

• Pitch translation
• Pad registration
• TGV or via integrity
• CTE continuity
• Attach fatigue
• Return-path continuity
• PDN impedance
• Decoupling location
• Thermal spreading
• Inspection and test
• Lifecycle reliability

Why CoWoP may be attractive for VRM placement

One of the strongest opportunities is power delivery. In advanced AI packages, the VRM is often physically far from the die. The power-delivery path must travel through the PCB, package substrate, interposer, bumps, and on-die distribution. This creates loop inductance, PDN impedance challenges, transient-response limitations, dI/dt sensitivity, resonance concerns, and pressure to place decoupling capacitance closer to the load.

Moving active power components onto the interposer or package may reduce distance, but it introduces other risks:

• Thermal density
• Active-component integration complexity
• Manufacturing risks
• Repairability concerns
• Reliability uncertainty

CoWoP may offer a more practical middle path. The VRM can remain on the PCB, where active power components are more manufacturable, serviceable, thermally manageable, and familiar to the design ecosystem. At the same time, however, the vertical corridor from platform PCB to transition patch to interposer may become shorter and more direct than the conventional package-substrate path.

So, the value is not that the VRM is placed on interposer; the value is that the VRM can stay on the PCB while the power corridor to the interposer becomes shorter, more controlled, and potentially lower inductance. That may reduce part of the package-dominated loop inductance and improve the power-delivery architecture without forcing active VRM components into the interposer itself.

This creates a new chiplet power architecture opportunity: PCB-side VRM, transition-patch power delivery, lower package burden, and governed PDN evidence. But the power problem is not solved automatically. The transition patch must preserve current return paths, minimize spreading inductance, support decoupling strategy, avoid PDN anti-resonance, and remain reliable under thermal cycling.

In short, while the corridor is shorter, it still must be governed.

Why CoWoP may be attractive for DDR and LPDDR

Memory is another important area. HBM will remain critical for high-bandwidth AI accelerators, but not every memory requirement should necessarily move onto the package. DDR and LPDDR placed on package can create manufacturing, warpage, thermal, test, yield, and reliability concerns.

So, memory on the PCB remains attractive because it’s more familiar, more serviceable, and more compatible with established board-level manufacturing. The problem is distance and signal quality.

In a conventional architecture, the memory path may be:

Die → interposer → package substrate → PCB → DDR/LPDDR with CoWoP

The path may become closer to:

Die → interposer / wafer-level routing → transition patch → platform PCB → DDR/LPDDR

This does not make PCB memory identical to on-package memory. However, it may improve the compromise: memory can remain on the PCB while the routing path becomes shorter, more direct, and potentially more controllable than the conventional package-to-board path.

That is a meaningful system architecture advantage. It may also reduce pressure to place every useful memory element inside the package, which can help with manufacturability, reliability, thermal control, and module yield.

But DDR/LPDDR on the PCB still demands careful governance.

• Timing margin
• Impedance control
• Crosstalk
• Return path
• Via transitions
• Thermal drift
• Board manufacturing variation

CoWoP may improve the memory compromise, but it does not eliminate memory convergence risk.

Why CoWoP may help UCIe and chiplet routing

UCIe and other chiplet interconnect strategies need dense routing, controlled impedance, short paths, clean return current, low jitter, and manageable power/thermal interaction. However, in conventional 2.5D architectures, much of the high-density routing is constrained by interposer size, substrate escape, package boundary, and board transition.

CoWoP may create more flexibility by making the platform PCB part of the high-density system-integration fabric. This could support more flexible routing between chiplets, memory, power, and system I/O. It may also support larger integration footprints without relying on ever-larger package substrates.

But this is also where the challenge appears. The platform PCB can no longer be treated as an ordinary board. It becomes part of the advanced-package realization path. That means PCB materials, dimensional accuracy, layer stack-up, shielding, via structures, reference planes, surface finish, warpage, inspection, and assembly control all become part of the governed convergence problem.

The transition patch makes this more realistic, but it also introduces a new boundary that must be modeled, measured, inspected, and qualified.

The new CoWoP challenges

CoWoP may reduce several package-level burdens, but it does not eliminate complexity. It shifts complexity into a new interposer-to-transition patch-to-platform PCB corridor. The key challenges include:

• Low-loss platform PCB materials
• Interposer-to-transition patch attach reliability
• Transition-patch-to-PCB attach reliability
• Pitch translation from fine-pitch interposer scale to PCB attach scale
• TGV or via reliability inside the transition patch
• Warpage and CTE mismatch
• Board flatness and dimensional control
• High-density routing precision
• Shielding between dense high-speed traces
• Return-path continuity across multiple interfaces
• PDN impedance and resonance
• VRM placement and transient response
• Decoupling location and effectiveness
• DDR/LPDDR timing and signal integrity
• UCIe routing and crosstalk
• Thermal spreading from die and HBM into board-level structures
• Inspection accuracy
• Rework strategy
• Lifecycle reliability

These challenges are solvable, but they require a different mindset. CoWoP does not simply move packaging onto a PCB. It asks the PCB ecosystem to operate closer to semiconductor-grade precision, while also asking the package ecosystem to think beyond the traditional package substrate. This is why CoWoP is not only a packaging innovation. It is a governed realization challenge.

Three architectures, three bottleneck locations

The most useful way to compare these architectures is by asking where each one places the system bottleneck. CoWoS places the bottleneck in advanced package scaling: interposer size, package substrate capability, HBM integration, substrate supply, package warpage, thermal design, SI/PI, PDN, and board transition.

Wafer-scale integration places the bottleneck in system adaptation around a very large silicon object: power delivery, cooling, mechanical design, yield management, redundancy, system serviceability, and workload mapping.

CoWoP places the bottleneck in the interposer-to-transition patch-to-platform PCB realization corridor: pitch translation, CTE continuity, low-loss PCB materials, precision manufacturing, attach reliability, power delivery, memory routing, UCIe flexibility, shielding, return-path continuity, inspection, and lifecycle evidence.

None of these paths eliminates convergence complexity. Each path chooses where complexity will live.

Why CoWoP needs a trusted realization layer

CoWoS, wafer-scale integration, and CoWoP all create different evidence domains, but the same fundamental governance problem remains. Which evidence is mature enough to support a deterministic engineering decision?

For CoWoS, the evidence includes interposer routing, substrate PDN, HBM integration, warpage, thermals, package attach, SI/PI, EM/IR, and board transition. For wafer-scale integration, the evidence includes wafer yield, defect tolerance, power delivery, cooling uniformity, mechanical stability, redundancy, board interaction, and system operation.

For CoWoP, the evidence includes interposer-to-transition-patch attach, transition-patch-to-PCB attach, platform PCB materials, VRM proximity, loop inductance, decoupling strategy, LPDDR/DDR routing, UCIe flexibility, shielding, return-path continuity, warpage, inspection, and lifecycle reliability.

The common requirement is governed convergence. This is where a scalable trusted realization layer (STRL) becomes important. STRL does not need to decide that one packaging structure is always superior. Instead, it asks whether each corridor has enough normalized, admissible, causally grounded evidence to support closure.

In this sense, CoWoP is a powerful new vector for trusted realization because it converts the platform PCB from a passive board into an active realization corridor. With the transition-patch concept included, the sharper statement is: CoWoP converts the interposer-to-transition patch-to-platform PCB boundary into a governed realization corridor.

Platform PCB as an active realization corridor

The most important idea is this: CoWoP may turn the platform PCB into the next active control plane for AI system realization. This does not mean the board replaces the interposer. It means the board becomes more deeply integrated into the convergence path.

The platform PCB must support power delivery, memory routing, thermal interaction, high-speed signaling, mechanical stability, shielding, and manufacturing precision. The board is no longer downstream from the package. It becomes part of the package-system continuum.

That creates a new research and industry-development opportunity: Interposer + transition patch + platform PCB as a governed system EM corridor. This corridor can be evaluated across:

• Power delivery and transient response
• Loop inductance and dI/dt sensitivity
• Decoupling effectiveness
• UCIe/chiplet routing flexibility
• DDR/LPDDR signal integrity
• Shielding and crosstalk
• Thermal spreading
• Mechanical stability
• CTE and warpage
• Manufacturing yield
• Inspection and test
• Field reliability

This is not only convergence theory; it’s a practical architecture direction.

Evidence domains for a governed CoWoP corridor

For CoWoP to become a credible production architecture, the key evidence domains must be governed together, not separately.

A CoWoP realization corridor would need evidence from:

• Interposer layout and redistribution
• Micro-bump or hybrid-bonding interface quality
• Transition-patch material selection
• TGV/via resistance and reliability
• Pad registration and pitch expansion
• CTE transition and shear stress
• Patch-to-PCB attach integrity, platform PCB flatness, and dimensional stability
• VRM phase-current behavior
• PDN impedance and transient droop
• Decoupling effectiveness across frequency
• DDR/LPDDR timing margin
• UCIe crosstalk and return-path continuity
• Thermal gradients and cycling stress, inspection, rework, and lifecycle failure signatures

In conventional workflows, these may be treated as separate domains. In a governed realization architecture, they become one corridor. That is the role of STRL:

• Normalize evidence
• Preserve causality
• Qualify admissibility
• Support bounded engineering authority

Why this idea matters now

The current package stack is under pressure. AI packages are becoming larger, more complex, more thermally constrained, more power-hungry, and more challenging to manufacture. Moreover, package substrates face size, availability, yield, warpage, layer-count, PDN, and cost challenges.

At the same time, memory, UCIe, power delivery, thermal design, and system-level integration are becoming harder to close independently. CoWoP may not be mature enough today to replace CoWoS in mainstream high-volume AI accelerators. But the direction is important.

If low-loss PCB materials, precision board manufacturing, inspection capability, transition-patch technology, and interposer-to-board attach reliability continue to improve, CoWoP may become one of the important platform-level architectures for future AI systems. The reason is simple.

It reduces the number of realization layers between silicon and system, but only if the transition boundary is engineered correctly. Instead of managing interposer, package substrate, and PCB as three separate convergence domains, CoWoP points toward a tighter corridor: interposer → transition patch → platform PCB.

That can potentially improve power-delivery proximity, reduce package-dominated loop inductance, keep active VRM components on the board, preserve DDR/LPDDR manufacturability, support flexible UCIe routing, and reduce some package-size and substrate-related burdens. But it also demands stronger governance.

What makes CoWoP practical

CoWoS proved that advanced packaging is central to AI scaling. Wafer-scale integration proved that silicon-scale system integration can unlock a different class of compute architecture. CoWoP may become an important middle path: wafer-level density brought closer to the platform PCB, with power, memory, routing, and system realization governed through a shorter corridor.

However, the most important CoWoP challenge is not only substrate removal; it’s the transition from silicon/interposer scale to PCB scale. The opportunity is not that CoWoP solves every problem. The opportunity is that it relocates the problem to a corridor that may be more scalable, more board-integrated, and more compatible with practical power and memory placement.

The challenge is that this corridor must be governed. Low-loss materials, pitch translation, transition-patch reliability, VRM proximity, PDN impedance, loop inductance, decoupling, LPDDR routing, UCIe flexibility, shielding, thermal behavior, warpage, and lifecycle reliability must be treated as one convergence problem. This is where STRL becomes relevant.

The future question is not only whether CoWoP can be built. The future question is whether the interposer-to-transition patch-to-platform PCB corridor can remain electrically, thermally, mechanically, manufacturability, and operationally converged across lifecycle. That is trusted realization.

It’s also the next bottleneck. And it may also be the next opportunity.

Interoperability moves data. STRL qualifies evidence. Governed convergence closes decisions.

Dr. Moh Kolbehdari is senior director of IC/packaging at Socionext US.

Editor’s Note

This is Part 2 of the mini-series on advanced packaging. Part 1 highlighted the basic comparison between CoWoS, wafer-scale integration, and CoWoP technologies.

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• Intel flash move could put wafer-level packages on the map

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Built around the NXP RW612 wireless MCU, Quectel’s FCM365X module combines dual-band Wi-Fi 6, Bluetooth LE 5.4, Zigbee, and Thread connectivity in a single device. It integrates a 260-MHz Arm Cortex-M33 processor with TrustZone, 1.2 MB of SRAM, and 8 MB of flash, with optional PSRAM expansion.

The FCM365X gives developers the flexibility to support multiple wireless protocols while simplifying device design. Zigbee and Thread enable low-power, reliable mesh networking across smart home and industrial IoT ecosystems, with Thread emerging as a key technology for Matter-enabled devices.

Suited for power-constrained applications, the FCM365X offers multiple low-power modes and keep-alive mechanisms. Standard interfaces include GPIO, SDIO, UART, USB, SPI, and JTAG, while the QuecOpen SDK enables access to I²C, I²S, ADC, LCD, and PWM. The module also complies with WPA-PSK, WPA2-PSK, and WPA3-SAE security standards and uses AES-128 encryption.

The FCM365X is housed in an LCC+LGA surface-mount package with a compact footprint of 25.5×18.0×3.16 mm. A timeline for availability was not provided at the time of this announcement.

FCM365X product page 

Quectel Wireless Solutions

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The TPM1R408RH 80-V N-channel MOSFET is built on Toshiba’s latest-generation low-voltage U-MOS11-H process. It features an optimized device structure with an RDS(on) of 1.4 mΩ—about 26% lower than the 80-V TPM1R908QM based on the previous-generation U-MOS X-H process. It also improves the RDS(on)-Qg tradeoff, reducing figure of merit by ~45% versus the TPM1R908QM.

These reductions lower power loss in switch-mode power supplies for industrial equipment such as AI data centers and communication base stations. The TPM1R408RH also suppresses drain-source voltage spikes during switching, reducing EMI. This helps minimize late-stage design rework and simplifies filter and snubber circuits.

The MOSFET is supplied in the SOP Advance(E) package, which delivers approximately 65% lower package resistance and approximately 15% lower thermal resistance than Toshiba’s current SOP Advance(N) package. This reduces conduction losses and improves thermal performance, enabling higher power density in compact power supply designs.

The TPM1R408RH is available through Toshiba’s authorized on-line distributors.

TPM1R408RH product page 

Toshiba Electronic Devices & Storage 

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Infineon’s AIROC UWB TSL100 SoC enables centimeter-level distance measurement and localization using ultra-wideband (UWB) time-of-flight (ToF) technology. Designed for low-power, secure operation, the device targets automotive, consumer, and industrial applications such as secured vehicle access, in-cabin presence detection, contactless payment and ticketing, and industrial asset tracking and collision avoidance.

The TSL100 is the first member of a scalable UWB product family intended to align with upcoming standards such as IEEE 802.15.4ab. It includes a CCC-, FiRa-, and Aliro-compliant MAC. The PHY delivers 48-bit FiRa and CCC security in challenging non-line-of-sight conditions, detecting and verifying direct paths up to 100,000 times weaker than reflected paths.

The SoC enables more than two years of coin-cell battery life in CCC ranging schemes for key fobs, achieved through a dedicated low-power mode that reduces current consumption by more than 50%. Its RF architecture extends sensing functions to presence detection, kick sensing, intrusion detection, and NCAP scenarios. Additionally, AIROC zoning technology enables configurable unlock zones and inside/outside detection for Aliro-enabled smart locks.

Engineering sample kits for the AIROC UWB TSL100 are available upon request.

AIROC USB TSL100 product page 

Infineon Technologies 

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ST’s ST54M integrates a post-quantum cryptography (PQC) hardware accelerator, NFC controller, secure element, and eSIM on a single die. The chip helps smartphone and personal electronics manufacturers prepare for future post-quantum security requirements while enabling secure mobile connectivity. Applications include contactless payment, transit ticketing, access control, digital identity, and mobile driver’s licenses.

The ST54M’s hardware accelerator supports PQC algorithms such as ML-KEM and ML-DSA, aiding the transition from hybrid cryptographic approaches to full post-quantum deployment. It also helps protect against side-channel and fault-injection attacks and addresses emerging PQC requirements.

Based on an Arm Cortex-M3 32-bit MCU, the contactless front-end provides NFC card emulation, reader/writer, and peer-to-peer communication modes. It increases RF communication distance, simplifies NFC integration, and supports efficient low-power operation. An integrated step-up DC/DC converter enables transmit drive up to 3 W.

Samples are available now. Production and Common Criteria 2022 EUCC and EMVCo certifications are targeted for July 2026.

ST54M product page 

STMicroelectronics

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The Melexis MLX91229 Hall current sensor provides a second-order sigma-delta digital output that improves signal integrity in EV traction inverter applications. Optimized for automotive systems, this output tolerates heavy EMI, helping maintain signal integrity over longer PCB traces or wiring where electrical noise can introduce disturbances between the sensor and MCU.

Unlike analog sensors, the MLX91229 encodes measured current into a sigma-delta bitstream, with information represented by the density of digital pulses rather than absolute voltage levels. This encoding makes the signal inherently more resistant to electrical noise during transmission to the MCU. Because demodulation is performed in the host MCU, designers can optimize the tradeoff between fast overcurrent detection and high-accuracy current measurement.

Supporting current sensing from 200 A to 2000 A, the MLX91229 measures peak magnetic fields from 11 mT to 400 mT. It uses Manchester-encoded data transmission over differential RS-422 or LVDS interfaces. The AEC-Q100-qualified sensor operates over an ambient temperature range of –40°C to +125°C and is powered from a selectable 3.3-V or 5-V supply.

The MLX91229 is available in a 4-pin SIP through authorized distributors and is designed as a drop-in replacement for conventional analog sensors.

MLX91229 product page 

Melexis

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submitted by /u/jones_supa
[link] [comments]

Dynex Semiconductor Ltd of Lincoln, UK has developed a 450A, 650V gallium nitride (GaN) half-bridge power module, designed to deliver ultra-fast switching performance, high efficiency, and enhanced thermal management for demanding power conversion applications...

A linearized output is a useful elaboration of a capacitive sensor design. But what if the circuit is located a significant distance from the control electronics?

Recently, Design Ideas included a circuit that comprised a simple analog interface to basic capacitive position sensors. Figure 1 shows its minimal six parts topology with complementary outputs: Out and –Out.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Figure 1 U1a and U1b cross-coupled Schmidt trigger timers form a ~1MHz RC multivibrator. The Tsense pulse width is inversely proportional to sensor displacement Tref/Tsen = Cref/Csen = d.

Doubling the parts count to 12 transmogrifies Figure 1 into Figure 2 and provides a linear voltage mode output,  Then, with the exemplar 38mm-diameter sensor plate capacitor connected, separation d between plates reads out as d = (Vout – 1) = 0 to 4 millimeters as Vout goes from 1 to 5v.  Vout ripple is just half a millivolt pk-pk. The linear voltage output modification is described in this Design Idea.

Figure 2 Averaging integrator A1 implicitly computes the output voltage needed to linearly balance the charge transferred onto C1 during Tref through discharge during Tsense. Vout = Tref / Tsense  + 1 = Cref / Csense + 1 = d + 1.

So, let’s take it as granted that providing a linearized output was a useful elaboration of the original design.  But suppose the capacitive sensor is located a significant distance from the control electronics.  Voltage mode analog outputs are notoriously vulnerable to noise pickup and disturbances like ground loop voltage differentials.  What to do then?  Figure 3 shows a simple and plausible remedy.  It’s a classic, if I do say so myself.  A noise- and cable length- tolerant, linear 4 to 20mA, current mode output.

Figure 3 Dangling the TLV431 shunt voltage reference Z1 from the 15 volt supply is a shortcut toward implementing a noise- and cable length- tolerant current mode output.

Here’s how it works. Figure 3’s A1 integrator generates a 1 to 5 volt linear output, much like Figure 2’s A1 does.  The difference is this 1 to 5v is inverted, referenced to +15v, and developed across 249ohm current sense resistor R5.  It’s therefore an accurate readout of Pfet Q1’s 4 to 20mA source current.  Shunt reference Z1 provides both the 1.00v integrator reference and a 5v step-down supply for U1 and U2.  DC blocking C4 and R9 trickle protect the chips from being instantly fried in case the sensor capacitor plate shorts to ground.

Some random remarks: U1’s unused inputs should be tied to +15v.  C1, 2, 3, and 4 should be rated for the full supply voltage, which itself isn’t critical but shouldn’t exceed 20v.  Otherwise Q1’s gate will be at risk for over-voltage if the load becomes disconnected.  If  the supply equals 15v as shown, voltage compliance and consequent ground noise resistance is >9v. Iout ripple is ~0.01% pk-pk.  Figure 4 shows the net nicely linear response.

Figure 4 In this graph, black = sensor readout d in mm, and red = the nicely constant 4 microamps per micrometer resolution.

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

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I recently purchased a new Rohde&Shwarz RTB2 scope. 300MHz and 10bit ADC with a lot of extra software options :). almost 50% off At the same time i purchased 2 new soldering stations from JBC to power a T245 and T210 soldering irons. Also i got the idea to put a small 7" screen close to my microscope to make work easier under the micropscope. As example i have designed a USB output adapter for bench power supplies, USBpwrME which can be found on DIY different sites when googled. I wanted to measure a specific pin on a IC. I magnified this IC on the 7" screen and then it was really easy to follow the pins and pcb traces on the screen while measuring :) Love my lab setup 😂 submitted by /u/KS-Elektronikdesign [link] [comments]

Private rare-earths exploration and process development company US Critical Materials Corp (USCM) of Salt Lake City, Utah, USA (which is dedicated to advancing high-grade domestic sources of rare-earth elements and critical minerals essential to US national security, supply chain independence, and advanced manufacturing) has announced several major milestones: the relocation of its corporate headquarters to Darby, Montana; key leadership appointments; and the launch of a new public information website for the Sheep Creek Project in Montana...

Keysight Technologies Inc of Santa Rosa, CA, USA and WIN Semiconductors Corp of Taoyuan City, Taiwan — which provides pure-play gallium arsenide (GaAs) and gallium nitride (GaN) wafer foundry services for the wireless, infrastructure and networking markets — have announced a joint monolithic microwave integrated circuit (MMIC) design workflow that enables GaN MMIC design houses to achieve first-pass tapeout success. The workflow connects on-chip multi-domain simulation, 3D layout with verifications, and off-chip MMIC evaluation board design into a single environment. It supports the growing number of companies developing GaN MMICs for 5G base stations, Wi-Fi access points, satellite payloads, and defense radar systems...

In first-quarter 2026, patent activity in silicon carbide (SiC) technology remained particularly dynamic, both upstream in substrates and epitaxial wafers and downstream in power devices and modules, according to technology intelligence and IP strategy consulting company KnowMade in two new patent monitoring services dedicated to SiC technology:...

Hello everyone! I have made myself a simple function generator controlled by a raspberry pi Pico w. It's my first proper PCB work, as I have done one in the past but it was my first and had alot of mistakes. This one looks proper aswell, made it in altium and just wanted to share. If you're interested you can see Schematics / PCB and Github. Just finished second year of ECE. submitted by /u/S4vDs [link] [comments]

Advanced AI systems are forcing the semiconductor industry to rethink the boundary between silicon, package, board, power delivery, memory, cooling, and manufacturing. For several years, the dominant discussion has centered on advanced packaging capacity, high-bandwidth memory (HBM) integration, large interposers, organic substrate constraints, glass-core substrates, and scaling limits of 2.5D and 3D integration.

That discussion remains valid. But a deeper system question is emerging. What happens if the package substrate is no longer the center of the system-integration hierarchy? This question becomes especially important when comparing three architectural directions:

• CoWoS-style 2.5D integration
• Wafer-scale integration
• CoWoP/chip-on-wafer-on-platform-PCB concepts

Each approach is trying to solve the same industry problem: how to scale AI compute density, memory bandwidth, transient power delivery, thermal control, and multi-die integration beyond the physical limits of conventional packaging stacks. However, each architecture moves the bottleneck to a different place.

Chip-on-Wafer-on-Substrate (CoWoS) makes advanced packaging central to AI and high-performance compute (HPC) scaling. Next, wafer-scale integration pushes silicon integration to the extreme. Finally, Chip-on-Wafer-on-PCB (CoWoP) may create a new middle architecture where the platform PCB becomes part of the governed realization corridor.

Therefore, it’s not only a packaging phenomenon; it’s also about system realization.

CoWoS: The proven advanced packaging path

CoWoS has become one of the most important advanced-packaging architectures for AI accelerators and HPC silicon. It enables logic die, HBM stacks, and high-density interconnect to be integrated through an interposer and then connected to a package substrate and board.

The strength of CoWoS is apparent. It provides high-density die-to-die and die-to-HBM connectivity, supports large AI/HPC modules, and has become a production-proven integration path for high-bandwidth systems. However, CoWoS also exposes the limits of the modern package stack. See the complex corridor below:

Die/HBM → interposer → package substrate → PCB → voltage regulator module (VRM)/system

The package substrate must support escape routing, power delivery network (PDN) distribution, coefficient of thermal expansion (CTE) transition, mechanical stability, manufacturing yield, decoupling strategy, signal integrity (SI)/power integrity (PI) control, warpage management, and board attach reliability. And as package size increases, these challenges become more critical.

Many of the hardest problems in advanced AI packaging aren’t located in silicon; they occur in the package and package-to-board realization path.

• Warpage
• Substrate availability
• Package size
• Thermal gradients
• PDN impedance
• Loop inductance
• dI/dt response
• Decoupling placement
• SI/PI discontinuities
• Manufacturing complexity

In other words, CoWoS is powerful, but the package substrate becomes a major convergence burden. This is why glass-core substrates are receiving so much attention.

Glass substrates help, but they don’t remove corridor

Glass can improve dimensional stability, reduce warpage, provide better CTE control, support finer routing environments, and improve vertical power-delivery paths with through-glass vias (TGVs). For large AI/HPC packages and future electro-optical integration, these advantages are meaningful.

But glass should not be treated as a complete escape from package realization complexity. In most practical glass-core substrate architectures, the glass is primarily the core and the build-up layers still there. That means many high-speed routing-density challenges remain concentrated in the top build-up structure.

Moreover, bottom-side routing through the core is still not equivalent to short top-side interconnect. Signals passing through TGVs and returning through lower layers still face discontinuities, parasitics, reference-plane challenges, and SI/PI governance requirements.

So, glass changes the package problem, but it does not eliminate it. This distinction matters because CoWoP is not simply about replacing one substrate material with another. It’s about asking whether the realization hierarchy itself can change.

Wafer-scale integration: The extreme silicon path

Wafer-scale integration takes a different route. Instead of assembling many dies through a package-level integration strategy, it expands the silicon system itself. The result is an extremely large compute fabric with direct wafer-level integration, specialized power delivery, cooling, redundancy, and system infrastructure.

This can be technically powerful because it removes many conventional package boundaries and creates a very large on-wafer compute fabric. At the same time, however, wafer-scale integration does not eliminate realization complexity. It relocates it.

The board, power architecture, cooling system, mechanical structure, redundancy strategy, yield-management approach, and system-level service model must all adapt around a very large silicon platform. A useful way to summarize the difference is that wafer-scale integration expands silicon until the system must adapt around it. That can be attractive for certain AI workloads and specialized systems, but it’s not necessarily the most flexible path for every AI accelerator, custom ASIC, chiplet platform, or memory-rich architecture.

CoWoP: A possible middle architecture

CoWoP is interesting because it may offer a third path. Instead of the traditional path comprising die/HBM, interposer, package substrate and PCB, CoWoP points toward a shorter realization path.

Die/HBM → interposer/wafer-level structure → platform PCB

The deeper architectural value is not simply cost reduction. The deeper value is that CoWoP may change the power, memory, mechanical, and system-realization architecture. If the package substrate is reduced or removed, the system no longer needs to carry as much of the convergence burden through three separate layers: interposer, package substrate, and PCB.

Instead, the corridor becomes more direct. However, this directness should not be oversimplified. A realistic CoWoP architecture cannot simply assume that a fine-pitch silicon interposer can land directly onto a platform or PCB without a transition strategy.

The most important challenge may be the transition between wafer/interposer precision and PCB manufacturability. That transition may define whether CoWoP becomes a practical system architecture or remains only an attractive concept.

Dr. Moh Kolbehdari is senior director of IC/packaging at Socionext US.

Editor’s Note

This is Part 1 of the mini-series on advanced packaging. Part 2 continues with the advanced CoWoP concept: pitch translation, transition patches, VRM and memory placement, UCIe routing, and trusted realization governance.

Related Content

• True Wafer-Level Packaging
• Wafer Level Chip Size Package (WLCSP) Guidelines
• Intel’s Embarrassment of Riches: Advanced Packaging
• Nvidia, TSMC, and advanced packaging realignment in 2025
• Intel flash move could put wafer-level packages on the map

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Ones and zeroes: are clustered or spread out bits better? “It depends,” is the answer. Well, at least sorta.

In the Comments section of a recent Design Idea for a DAC (Reference 1), one reader expressed a full-throated preference for an alternative to the common type of PWM used therein. For this “common” PWM, the ones in a repetitive cycle are “clustered” together, as are the zeroes. The reader’s preferred alternative is a “spread” type, in which the ones and zeroes are evenly disbursed within each cycle.

The clustered PWM tends to concentrate energy toward the lower frequencies, versus toward the higher with the spread PWM. Noting the relative ease of filtering out the higher frequencies, the reader argued that a microcontroller implementing the spread PWM filtered by a first order low pass (single resistor, single capacitor) filter was superior to the clustered version followed by a more complex third order filter (three pairs of these components.) So, which is the better choice? Let’s take a look.

The job of a PWM filter

PWMs generally produce repetitive sequences of NO ones and NZ zeroes of length N = NO + NZ. A sequence’s filtered resolution is 1/N. Its duty cycle (DC) is its average value, NO / N. The filter will take some settling time TS to get to within some value VST of a new DC. And as long as DC is neither zero nor one, there will be an AC “ripple” signal of some level at the filter output.

Not only must the ripple signal’s contribution to TS be considered, but its post-setting time peaks and valleys must be closer than some error value VRip to DC. Typically, VRip is set to .5/N. The ideal filter meets this requirement while minimizing TS for a VST of 1/N. These requirements must hold for all DCs and transitions between them.

Verdict first, then the trial

With apologies for my paraphrase of a famous quote from Lewis Carroll’s Queen of Hearts, there’s enough math and batch file simulations required to adjudicate this PWM shoot-out that I thought it best to present the somewhat surprising (to me at least) conclusions without forcing you to first endure the derivations (perhaps this reported result will spur an interest in that math). Figure 1 provides the summary:

Figure 1 This graph shows the settling time TS for clustered and spread PWMs at various clock speeds. The spread filter employs a single resistor and capacitor; the clustered, 3 pairs of the same (see Table 1 for filter details.) Dividing the clock frequency by a factor multiplies the settling time by that same factor. The error VST at the settling time is 1/N. The post-settling time absolute maximum ripple error VRip is .5/N.

If implemented fully in hardware, such as with an FPGA, it would be possible to clock both PWM types at the same rate and compare their performances. For PWMs of more than 8 bits, the spread PWM (purple trace) with a first order analog filter does indeed settle faster than its clustered competitor (red trace) with a third order filter. The situation is reversed for PWMs of less than 8 bits. A simple explanation for this behavior is that below 8 bits, the clustered filter’s time constants turn out to be less than those of the spread, and the situation reverses above 8 bits. However, it’s worth noting that matched clocking is not possible in a microcontroller.

In a microcontroller, until a change in duty cycle is required, an initialized, clustered PWM can run indefinitely without further processor intervention. It can also benefit from the fastest clock available to the controller. Not so with the spread PWM; it requires code to be executed every PWM clock cycle period. I have assumed 6 machine cycles to execute this spread code within an infinite loop (blue trace). As such, only 16 bit and lengthier PWMs will favor the spread option.

Of course, if you need the processor to do more than just run a spread PWM, these additional functions will increase the effective spread clock period well beyond a mere 6 machine cycles. Obviously, this increases the settling time of the associated filter. And by the way, any non-PWM code had better take a constant number of clock cycles to execute, or the spread PWM output will jitter and its accuracy suffer. The less-than-pristine “cherry on top” is that processor interrupts while supporting a spread PWM are problematic.

PWM bits	Sequence length	Spread R·C/T: filter time constant / clock period	Spread settling time TS (ms), 1/6 MHz clock	Spread settling time TS (ms), 1 MHz clock	Clustered filter	Clustered settling time TS (ms), 1 MHz  clock
1	2	9.102E-01	6.00E-03	1.00E-03	See Reference 2 which points to a spreadsheet for filter design	7.92E-04
2	4	3.228E+00	3.00E-02	5.00E-03		3.32E-03
3	8	7.810E+00	1.08E-01	1.80E-02		1.01E-02
4	16	1.696E+01	3.12E-01	5.20E-02		2.93E-02
5	32	3.527E+01	8.04E-01	1.34E-01		8.32E-02
6	64	7.187E+01	1.97E+00	3.29E-01		2.34E-01
7	128	1.451E+02	4.67E+00	7.78E-01		6.53E-01
8	256	2.915E+02	1.08E+01	1.80E+00		1.81E+00
9	512	5.843E+02	2.24E+01	3.74E+00		4.98E+00
10	1024	1.170E+03	5.05E+01	8.42E+00		1.36E+01
11	2048	2.341E+03	1.12E+02	1.87E+01		3.71E+01
12	4096	4.684E+03	2.48E+02	4.13E+01		1.00E+02
13	8192	9.369E+03	5.42E+02	9.03E+01		2.71E+02
14	16384	1.874E+04	1.11E+03	1.85E+02		7.28E+02
15	32768	3.748E+04	2.40E+03	4.00E+02		1.95E+03
16	65536	7.496E+04	5.17E+03	8.61E+02		5.21E+03
17	131072	1.499E+05	1.11E+04	1.84E+03		1.39E+04
18	262144	2.999E+05	2.36E+04	3.94E+03		3.68E+04
19	524288	5.997E+05	4.81E+04	8.01E+03		9.75E+04
20	1048576	1.199E+06	1.02E+05	1.70E+04		2.58E+05
21	2097152	2.399E+06	2.16E+05	3.59E+04		6.80E+05
22	4194304	4.798E+06	4.55E+05	7.58E+04		1.79E+06
23	8388608	9.596E+06	9.57E+05	1.59E+05		4.71E+06
24	16777216	1.919E+07	1.94E+06	3.23E+05		1.24E+07

Table 1 This table details spread and clustered settling times and filter characteristics. Multiply the R·C / T term by the desired spread PWM clock period T to obtain the product of the resistance and capacitance of the first order analog filter (see Figure 4).

To avoid large settling times, recall the option of operating a most significant and a least significant 8-bit PWM simultaneously and adding their outputs as seen in Reference 2. A filter with a 16-bit settling time can be swapped for one with a much shorter 8-bit settling time. Should you want even more resolution, use this concept to add a third PWM.

All this being said, read on for some important sequence characteristics and how best to implement k-bit spread PWMs where k = 1, 2, 3… 24.

Clustered-bit PWM sequences

Clustered-bit PWMs’ NO ones and NZ zeroes each appear in contiguous streams. An example of a waveform for such can be seen in Figure 2. Most microcontrollers can implement these with no software overhead. Just “set ‘em and forget ‘em”: specifically, program the count (NO – 1) after which a one-to-zero output transition is to be produced, and the count (N – 1) after which the counter returns to 0 and the output to a one. The PWM goes on its merry way with no further intervention necessary from executable code unless a change in the value of the duty cycle DC is required.

8 and 16-bit counters are typically available, and so DC values of A / B can be had for any integers such that 0 ≤ A ≤ B ≤ either 28 or 216, respectively. Typically, these counters can be clocked from the same high frequency clock source used to execute the microprocessor instruction set. This is useful because in general, the higher the frequency, the shorter the settling time of the filter needed to suppress the ripple.

Figure 2 This plot is of a clustered-bit PWM where NO = 16, N = 256, and T = 1uS.

Spread-bit PWM sequences

Another type of PWM produces the same number of ones and zeroes in a cycle, but spreads these binary values as evenly as possible. An example can be seen in Figure 3.

Figure 3 With this spread-bit PWM, NO = 16, N = 256, and T = 1uS.

Notice that lowest frequency of the spread PWM is far higher (16 times) than that of the clustered one. Accordingly, a faster-settling filter can be used to suppress the ripple. So what rule governs the positions of the ones and zeroes in the spread sequence? A very simple one.

Consider a parameter X which can take on the values 0, 1, 2… or N – 1. Y is periodically updated to the value of (Y + X) modulo N. If an update reduces Y, the PWM output is one; otherwise, it’s zero. The DC is X / N. This process has at least two important properties:

1. The period of the PWM sequence is N. This can be shown by considering a parameter W upon which the process W = W + X is repeatedly performed (no modulus is involved in the W update.) If the initial values of Y and W were both C, then Y = (Y + X) modulo N and (W + X) modulo N would be equal after each process step. N steps later, W would be C + N X. For any X, (C + N · X) modulo N is C. Since the moduli of W and Y are always equal, C is also the value of Y after N process steps. And so for any X, the PWM sequence is periodic in N.
2. To gain insight as to how spreading works, consider when X is 0. Y would never be reduced, and so there would never be a PWM output of one. If X were 1, the PWM would produce a one only once every N steps. If X were increased, there would be ones approximately (if not exactly) every N/X steps. As X approached N/2, the proportion of ones in the output would increase, but as long as X ≤ N/2, ones would never appear in succession. For X ≥ N/2, there would never be any zeroes in succession. And as X approached N, a reversed version of the aforementioned progression of ones would apply to the zeroes.

How might this process be executed on a basic 8-bit microcontroller? The simplest implementation would be to set N to 28 and periodically hijack a portion of the processor’s executable bandwidth to run the process. The following code implements a spread 8-bit PWM of duty cycle X / 28, where the value of X is in register r17 and that of Y is in register r16:

ADD r16, r17 ; r17 holds the value of NO which can be anywhere from 0 to 28-1. ; r16 is a simple accumulator which overflows periodically. ROL r20 ; The carry bit ( 0 or 1) from the prior addition goes to bit 0 of r20. OUT PORTB, r20 ; Bit 0 of the PORTB GPIO register takes on the carry bit value.

Of course, you can include a few more instructions so that the other PORTB bits are unaffected. It’s important to note that this code must be executed regularly. Aperiodic, “jittery” execution will impact the accuracy of the filtered value of the output stream. This means that all non-PWM code must always take the same amount of time to execute, making interrupts on the processor problematic.

Want a PWM with more resolution? Place the following instruction after the existing ADD:

ADC r18, r19 ; r19 is the MSbyte of the input X and r17, the LSbyte.

This additional instruction enables a 16-bit duty cycle of X / 216. It’s obvious how to further increase resolution by additional factors of 28 to obtain 224, etc.

The inputs of spread PWMs can range from X = 0, 1, 2… to N-1. But if N is limited to integral powers of 28, there’s a very big jump (a factor of 28) of sequence lengths between these options. That means a proportional jump in filter cutoff frequencies and, more importantly, in settling times. Fortunately, a finer range of selections is readily available. Simply limit the allowable values of X to those for which X / 2k is an integer, where k = 1, 2… log2(N)-1. The result is a (log2(N) – k) bit DAC.

The settling times of filters meeting the ripple suppression requirement are now available in increments of a factor of 2. Of course, a spread-bit DAC can have any integer value for N. But values other than 2k require additional code which must explicitly compare Y to N to generate a carry, and then conditionally update Y by subtracting N from it. Also, the spacing between successive values of X could vary unless all N possible input values were used. Perhaps a better approach would be to operate multiple PWMs simultaneously, whose outputs are weighted differently by a factor of 28. The relatively quick settling time of an 8-bit filter would be a benefit.

Analog filters

For PWM filter designs, it’s necessary to determine the input-dependent output sequence whose ripple which is the most challenging for a filter to adequately suppress. As discussed in Reference 3, the worst case for a clustered PWM is a 50% DC. To achieve reasonable settling times (TS) to within an error VTS of 1/N while meeting the Vrip requirements of .5/N, a third order lowpass filter is employed. The structure of such a filter is seen in Figure 4. The referenced Design Idea offers a downloadable spreadsheet which designs filters to users’ specifications of PWM cycle frequency and of peak-peak ripple as a fraction of full-scale output.  It was used to populate the settling time entries in Table 1 for the clustered PWM.

For the spread PWM, the worst case was determined by running simulations of all 256 output sequences of an 8-bit spread PWM applied to a first order filter (see Figure 4 again.) But what first order filter? To answer this question, I started by assuming (perhaps counterintuitively) that the worst case for ripple suppression occurs for 1 one, that is, when PWM input X = 1. (Since zeroes and ones are fully symmetric, this is equivalent to the case of 1 zero, or X = 255.) What will the ripple troughs and peaks look like for each input value at the output of a filter with a time constant selected to provide the necessary ripple suppression for X =1 only?

Figure 4 With these first and third order low-pass analog filter structures, the filters are buffered with op amps because their inputs employ resistors of high values. This is done to limit the errors imposed by the unequal resistances of the logic high and low outputs of ICs such as the 74AC04 which drive the filter inputs (Reference 4).

First we have to find that time constant. We start by writing equations for ripple starting at time t = 0. Here, R and C are the first-order filter components, and NO + NZ = N as before. The filter output is:

1. V0 (immediately before a zero-to-one transition)
2. V1 = V0·e-NO·T/(R·C) + (1 – e-NO·T/(R·C)) (immediately before the next one-to-zero transition)
3. V2 = V1·e-NZ·T/(R·C) (immediately before the next zero-to-one transition)

in the steady state, after the filter settles from a change in duty cycle, V2 = V0. Solving:

4. V₁ss = (1 − e-NO·T/(R·C)) / (1 − e-N·T/(R·C)) + 1/N (ripple peak)
5. V₀ss = 1/N – (e-NZ·T/(R·C) − e-N·T/(R·C)) / (1 − e-N·T/(R·C)) (ripple trough)
6. Vrip = V1ss – V0ss = (1 – e-NO·T/(R·C)) · (1 – e-NZ·T/(R·C) ) / (1 – e-N·T/(R·C) ) (peak – trough)

Setting V₁ss in #4 above to .5/N for N = 28 and solving numerically, a value of 291.5 is obtained for the unit-less term R·C / T. Setting V0SS in #5 to .5/N with R·C / T = 291.5 yields a smaller error than .5/N for the trough; the peak error is the larger of the two (tabulations of this term for a range of N values were calculated from #4 and appear in Table 1). In a simulation, T was set to 1uS, R to 1MegΩ and C to 291.5pF. Output sequences resulting from inputs from 1, 2… 255 were applied to an 8-bit spread PWM.

Figure 5 shows a graph verses the input X values of the maximum ripple deviations from DC and of half the peak-to-trough differences. It’s clear that the biggest error is associated with inputs both of 1 one and of 255 ones (1 zero). This filter time constant 291.5uS does indeed limit the deviation from the duty cycle of 1/N (1/256) to .5/N times the PWM’s full-scale output, one half of the PWM resolution, and an input of X = 1 does yield the worst-case ripple. For any clock period T, simply multiply the Table 1 unit-less parameter R·C / T by T to obtain the filter’s R-C time constant.

Figure 5 This graph shows the filter output deviations from DC in the steady state vs. input values of 1, 2… 255 for an 8-bit spread PWM. A 100mS wait was employed before measurements to ensure settling, more than 300 times the 291.5uS filter time constant.

It might be surprising that the worst ripple peaks are associated with a single one or zero in the output sequence. But a little thought reveals that a single pulse is the case where the lowest frequency f1 = 1/(N·T) Hz that the PWM can produce has the largest amplitude. Note that input values which are powers of 2 have the lowest maximum errors. This is in part because they have no energy at f1 Hz. I have spot-checked sequences of N-4096 and those for N < 256 and found an input of X = 1 to consistently produce the maximally deviant ripple.

Settling times of the spread PWM filter

Tired of the math by now? You ain’t seen nothin’ yet!

Because an analog filter is being driven by a digital sequence, difference equations can be used to calculate the filter output. The worst case for setting time is when the filter output at time t = 0 is DC = 1 (NO = 256) and the input transitions to NO = 1. Then:

7. y[k]      =          a*y[k-1] + (1-a)*x[k],              y[0] = 1,           a = e-T/(R·C),       k = 0, 1, 2…

where x[k] = 1 when k modulo N = 0, and 0 otherwise.

Ripple peaks occur when x[k] = 1 and troughs when k modulo N = N – 1 =255 (immediately before a peak.) We have:

8. Yp[k·N]             =          ak·N + (1 – a)*(1 – a(k+1)·N) / (1 – aN),                   ripple peaks
9. Yt[k·N – 1]        =          ak·N -1 + (1 – a)*(aN-1 – a(k+1)·N-1) / (1 – aN),          ripple troughs
10. yp_SS                 =          (1 – a) / (1 – aN)                                                steady state ripple peak
11. ypp                             =          (1 − a)(1 − aN−1) / (1 − aN)                                steady state p-p ripple
12. k1st_peak = N * Ceiling [ Log { ( (2/N) · (1 – b) + a – 1) / (1 + (a – 2)·b) } / Log(b) ],       b = aN

where k1st_peak is the smallest value of k for which all ripple peaks are less than 2/N.

It’s worth taking a look at what is going on for the worst-case ripple when N = 256. See Figure 6.

Figure 6 This graph represents data for a spread PWM with N = 256 and filter outputs starting at one (1 volt.) At time t = 0, the red trace reflects a change of input to X = 1 and the blue, an input change to X = 0. X = 1 takes longer to settle because it spends 1/N of its time with an input of one, whereas X = 0 spends all of its time with an input of zero.

From #12, k1st_peak is the smallest value of k for which ripple peaks y[k·N] are less than or equal to 2/N. In this case, that corresponds to k = 8·N at 2.048mS ( y[7·N] is slightly larger than 2/N.) Finally, #7 is used to iterate all integer values of k from 7·N to 8·N find the smallest value of k = kS (that is, the first time) for which y[k] and all subsequent values of y[k] are less than 2/N. The settling time is then T·kS. This procedure is used to populate in Table 1 the spread PWM settling times at various cycle lengths N for a 1MHz clock.

In conclusion…

PWMs can be implemented by microcontrollers. For a clustered-bit PWM, no further intervention is required by the controller beyond the cycle length of a programmable counter and the latest value of DC. Typically, the counter can be advanced by the highest speed clock available to the controller. But for a spread-bit PWM, a supportive block of code consisting of multiple instructions must be executed periodically This must be done at consistently timed intervals if accuracy is to be maintained.

To allow the processor to perform other functions, these intervals, the effective period of the spread clock, can be quite long in comparison to those of the clustered-bit PWM. Longer clock periods lengthen the settling time of the filter needed to suppress a PWM’s ripple. Granted, the spread sequence has generally much less lower frequency energy than a comparably clocked clustered sequence and therefore can employ a faster settling time filter for ripple suppression. But in practice, microcontrollers cannot clock code-driven spread PWMs at the rates of clustered ones, which have inherent hardware support. Comparable resolution spread PWM filters generally take longer to settle than those of their clustered cousins when microcontrollers implement these PWMs.

It’s intriguing to consider that the spread PWM discussed herein can be considered to be a first order delta-sigma modulator (Reference 5). The overflow of the registers can be thought of as an accumulator which, when instead of overflowing, adds a value of -N to its input X. Modulators of order higher than the first can shift even more low frequency energy to higher frequencies, relaxing ripple-suppression requirements even more and reducing settling time. Most commercial implementations of such techniques replace analog filters with digital versions thereof which then drive conventional multi-bit DACs, all implemented on a single IC.

If our PWM types were to be implemented in hardware such as an FPGA, their clock rates could be identical. As per Table 1, at identical clock rates, some sequence lengths N would favor the spread PWM with a simple single R-C pair (first order) filter, and others which would favor the clustered PWM with its three-pair (third order) R-C filter. However, the spread PWM would also benefit by replacing its first order filter with a third order one, something I plan to discuss in a forthcoming Design Idea.

PWMs: the gift that keeps on giving!

References:

1. Custom design PWM filters easily
2. Ibid, Figure 3.
3. Ibid
4. Ibid, see the SN74AC04-induced errors section.
5. https://www.ti.com/lit/an/slyt423a/slyt423a.pdf

Christopher Paul has worked in various engineering positions in the communications industry for over 40 years.

Related Content

• A nice, simple, and reasonably accurate PWM-driven 16-bit DAC
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• Parsing PWM (DAC) performance: Part 2—Rail-to-rail outputs
• Parsing PWM (DAC) performance: Part 3—PWM analog filters
• Parsing PWM (DAC) performance: Part 4 – Groups of inhomogeneous duty cycles

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