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Infineon Technologies AG of Munich, Germany says that its CoolGaN Transistor 100V devices have been selected by BRC Solar GmbH of Ettlingen, Germany (which provides module-level power electronics for photovoltaic systems) as the core switching technology for its Power Optimizer...

ClassOne Technology of Kalispell, MT, USA (which manufactures electroplating and wet-chemical process systems for ≤200mm wafers) has announced record follow-on orders from Applied Optoelectronics Inc (AOI) of Sugar Land, TX, USA (a designer and manufacturer of optical and hybrid fibre-coaxial networking products for AI data centers, cable TV and broadband fiber access networks) for multiple Solstice S8 single-wafer wet processing systems to support AOI’s expanding production of optical devices in Houston...

SmartController from GÖPEL electronic offers a framework and versatile interfaces for controlling demanding tests, demonstrations, and laboratory applications

In the automotive sector, individual components such as vehicle seats often need to be tested or demonstrated independently of the overall configuration to ensure functions such as adjustment ranges, massage, heating, and ventilation. However, the control elements and power supply configured for the final vehicle are not available for this purpose. GÖPEL electronic has developed the SmartController for this application. This universal control solution is designed for demanding individual or endurance tests, presentations, and functional demonstrations, as well as laboratory applications. The powerful platform combines modern hardware, flexible software architecture, and intuitive operating concepts in a compact system.

The SmartController is based on the proven Serie62 G CAR 6281 hardware platform and offers a modular architecture with versatile interfaces. With this, GÖPEL electronic has created a universal hardware foundation that can be used across projects and customized as needs a clear advantage for test environments with changing requirements. Thanks to its high scalability, the SmartController supports up to eight bus interfaces, providing comprehensive support for automotive communication standards such as CAN, CAN-FD, LIN, and Automotive Ethernet, including residual bus simulation, diagnostics, and monitoring. The integrated Ethernet and Wi-Fi connectivity enables seamless networking and easy integration. This makes the SmartController suitable for both long-term endurance tests and dynamic development and presentation environments.

A key feature is the tablet control framework, which enables modern and convenient operation. Its uniform structure allows for use in various projects while maintaining a consistent user experience. Features such as the “Sticky Keys” input assistance (“Touch ’n’ Click / Make ’n’ Break”) support ergonomic and safe operation regardless of the hardware used. With the SmartController, GOEPEL electronic underscores its commitment to providing future-proof, modular, and practical solutions for vehicle development and industrial test applications.

The post Universal Control Solution for Endurance Tests of Vehicle Components appeared first on ELE Times.

AEC-Q102 Qualifies Devices Feature Spectral Sensitivity Matches to Human Eye and Improves Spectral Angular Performance in Compact 0805 and Top-View QFN Packages

Vishay Intertechnology, Inc. expands its optoelectronics portfolio with the introduction of two Automotive Grade PIN photodiode ambient light sensors that deliver enhanced optical accuracy and long-term reliability in harsh environments. AEC-Q102 qualifies; the Vishay Semiconductors VEMD4210FX02 and VEMD5525FX02 feature spectral sensitivity closely matched to the human eye response with a peak wavelength of 530 nm and no infrared (IR) bump.

The devices are designed for automotive applications, including automatic light control in Center Information Displays (CID), Head-Up Displays (HUD), and Rain Light Tunnel (RLT) systems, as well as backlight dimming in industrial equipment. By eliminating the IR bump in the spectral sensitivity curve, the devices ensure precise visible light measurement without unwanted IR influence in these applications. In addition, the devices’ superior angular characteristics ensure stable spectral accuracy regardless of the angle of incoming lighting for consistent and reliable light measurement performance.

For space-constrained applications, the VEMD4210FX02 offers a typical reverse-light current of 0.014 μA and a sensitivity range from 470 nm to 610 nm in a compact 0805 package with a radiant-sensitive area of just 0.42 mm². For applications requiring enhanced sensitivity, particularly in low-light conditions, the VEMD5525FX02 offers a reverse-light current of 0.11 μA and a sensitivity range from 480 nm to 590 nm in a top-view QFN package with a large 7.5 mm² radiant-sensitive area. Both parts also feature wettable flanks for optical solder joint inspection.

RoHS-compliant, halogen-free, and Vishay Green, the sensors feature a moisture sensitivity level (MSL) of 4 in accordance with J-STD-020 for a floor life of 72 hours. The devices support lead (Pb)-free reflow soldering and operate over an ambient temperature range of -40 °C to +110 °C.

 

Device Specification Table:

Part number	VEMD4210FX02	VEMD5525FX02
Typical reverse light current at EV = 100 lx (µA)	0.014	0.11
Angle of half sensitivity (°)	± 52	± 58
Range of spectral bandwidth (nm)	470 to 610	480 to 590
Wavelength of peak sensitivity (nm)	530	530
Package	0805	Top-view QFN
Dimensions (mm)	2.0 x 1.25 x 0.7	5.0 x 4.0 x 0.9
Radiant sensitive area (mm²)	0.42	7.5

 

The post Vishay Launches High-Accuracy Automotive Light Sensors appeared first on ELE Times.

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Deposition equipment maker Aixtron SE of Herzogenrath, near Aachen, Germany says that the Massachusetts Institute of Technology (MIT) Lincoln Laboratory has purchased two Hyperion 300mm metal-organic chemical vapor deposition (MOCVD) systems as part of a partnership made possible by the Massachusetts Governor’s Office and the Northeast Microelectronics Coalition (NEMC). The systems will support research on gallium nitride (GaN) power electronics, radio-frequency applications, and next-generation two-dimensional materials, and will be available to users across the NEMC ecosystem and beyond...

In high-volume consumer electronics, the margin between a feature and a failure mode is increasingly narrow.

As the architecture of form-factor constrained devices becomes more tightly integrated, the traditional modularity of hardware systems breaks down. Thermal behavior, RF performance, mechanical tolerances, and power delivery are no longer independent domains because small sub-system shifts cascade across the entire system.

When the thermal envelope of a system-on-chip (SoC) directly impacts the signal integrity of a nearby 5G antenna, or when a mechanical tolerance stack-up in a camera module creates parasitic capacitance on a display flex, validation can no longer be a post-design activity.

Today, the complexity of modern hardware validation is a direct consequence of early architectural decisions. As highlighted in McKinsey’s analysis on handling technical complexity, upfront product architecture misjudgements inevitably compound into severe downstream bottlenecks during the integration phase.

Cost of coupling: Architectural debt

In loosely coupled systems, validation scales linearly. Components can be tested independently, and integration risk is bounded. However, in tightly coupled systems, validation scales exponentially. For instance, in a loosely coupled architecture where the display, power management IC (PMIC), and RF modem operate within encapsulated boundary interfaces, validating state transitions across 4 operating modes requires an additive test matrix, totaling 12 unique test permutations.

However, when these 3 subsystems are tightly coupled, where transient voltage drops from a 5G RF burst could force dynamic updates to the display’s refresh logic and PMIC power rails, the test matrix explodes up to 48 unique test permutations for the same feature set, a 4x increase in test overhead.

Decisions to integrate a new module, compress an existing subsystem, or optimize the overall system introduce a new set of interdependencies to be de-risked. For example, a custom-design ASIC may require entirely new silicon-level validation infrastructure in collaboration with the chip manufacturer before meaningful system integration can begin.

In parallel, a complex PCB stack-up can increase the risk of parasitic coupling and desense, requiring exhaustive EMI testing. Furthermore, high-density packaging may compress thermal margins, necessitating sophisticated workload throttling to maintain performance metrics.

When architecture teams prioritize power, performance, and area (PPA) without explicitly accounting for validation and verification, they incur architectural debt. This simply refers to an acceptance of long-term trade-offs (the debt) in exchange for immediate product architecture wins.

This debt is often paid off during engineering validation builds and volume ramp. Gamliel and Barron (2026) empirically analyzed high-complexity new product introduction (NPI) environments and found that early organizational and architectural blind spots are the primary upstream drivers that later materialize as volatile downstream ‘non-quality costs,’ directly yielding schedule deviations, material waste, and collapsed margins during volume manufacturing transitions.

Figure 1 In loosely coupled systems, validation effort grows linearly with added complexity. In tightly coupled systems, interdependencies cause exponential growth. The gap is architectural debt. Source: Author

Supplier co-development: Moving handshake upstream

At flagship scale, global supply chain provides co-engineering support in addition to its legacy logistics execution function. Supply chain is tightly integrated with system architecture. Here, a common failure mode in NPI treats suppliers strictly as a black box expected to deliver components to fixed specifications.

Meanwhile, in tightly coupled systems, critical risks are bound to emerge from sub-components within the system. Mitigating these risks require moving validation alignment upstream and creating an earlier validation handshake during system architecture. This includes:

• Joint validation planning between system teams and suppliers to align on defining success at component and system levels.
• Infrastructure sharing where suppliers are provided with realistic system conditions, enabling them to test and de-risk components in system-level simulation models.
• Transparent yield modeling between system teams and suppliers to accommodate the supplier’s manufacturing variance in system design.

If this handshake happens later, validation becomes reactive. If earlier, architecture becomes more robust and more tolerant to real-world variations.

Validation infrastructure as a design tool

In leading programs, the minimum viable product (MVP) for validation comes much earlier than the first system hardware. Validation infrastructure is set up to serve as a de-risking tool prior to the first prototype build. This infrastructure includes the employment of virtual systems that enable high-fidelity simulations for validating system behavior in digital twin environments.

Digital models can uncover thermal coupling, signal integrity issues, and power interactions early in the design cycle. Modular breadboards and development platforms also enable early development of firmware, software, and tests while final mechanical enclosures are still being designed.

Additionally, pre-silicon emulation allows teams to explore system behavior early in the loop with accelerated simulation layers, even before physical prototypes exist. Pre-silicon environments allow software and power-state validation before tape-out. This is particularly essential because silicon tape-out schedules often come in advance of overall system readiness.

By the time the first “steel-tooled” builds are available, most integration risks should already be understood, bounded, or mitigated. Programs that rely on physical builds to discover system behavior are effectively deferring architectural decisions into the most expensive phase of development.

However, even with the right infrastructure, organizations still need a decision framework to ensure validation is treated as a first-class architectural constraint. That’s where governance comes in.

Governance: Where architecture and validation converge

Enforcing validation as a first-class architectural priority is more of a leadership mandate than a technical hurdle. System engineering program managers and technical leaders must establish the structural authority to elevate validation readiness to a non-negotiable, first priority directive within early architectural decision-making.

When new features are proposed, the validation path required to support them must also be considered. If a design introduces dependency on new validation infrastructure that cannot be developed within the program timeline, an architectural risk and debt has just been introduced.

Validation should be shifted from a milestone to a gating function. Architectural reviews should explicitly evaluate validation complexity, infrastructure readiness, and integration risk alongside performance and cost. Below is a simple governance checklist:

• Is the validation path defined before architecture sign-off?
• Are suppliers’ validation plans aligned with system-level requirements?
• Is there a rollback option if validation reveals unmanageable complexity?

Without this shift, teams unintentionally accept risk that will surface later as schedule slips, yield instability, or late-stage redesign.

Figure 2 With making validation a gating function, every architectural decision must include a credible validation plan before approval. Source: Author

From validation to architecture

As systems become more integrated, the relationship between architecture and validation becomes inseparable. Validation is no longer the mechanism that ensures a design works. It’s the lens through which architectural risk is exposed.

Organizations that recognize this shift can realize design systems that are inherently more testable, more manufacturable, and more predictable at scale. And those that don’t, continue to discover risk at the point where it’s most expensive to resolve.

When you sit in an architecture review next time, ask one question before approving any new feature: ‘What is the validation path, and is it ready today?’ If the answer is anything but ‘yes,’ you are already in debt.

Ayokunle Oni is a system engineering program manager at Apple, where he helps coordinate the iPhone hardware design and engineering process across cross-functional teams. He specializes in system integration and validation and has led complex engineering programs from concept through production, working closely with global manufacturing and vendor partners.

Related Content

• Basics of Bench Silicon Validation – PCB Passives
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• Design Constraint Verification and Validation: A New Paradigm
• How system-level validation compresses schedule risk in device design
• Design-Stage Analysis, Verification, and Optimization for Every Designer

The post Relationship between architecture and validation in system design appeared first on EDN.

Here’s a neat and novel way of using a long-tailed pair to drive not just two but three LEDs.

As everyone knows, rainbows always have pots of gold at their ends. This Design Idea reverses that, starting with a pot (no gold, alas) and ending with a rainbow.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Bi-color LEDs can be useful animals for indicating circuit balance or battery condition, and the common-cathode types are easily driven with a long-tailed pair, with various proportions of red and green giving oranges and yellows. Tri-color (RGB) types, capable of producing a much wider spectrum, usually need three separate drive sources.

So what happens if we drive drive the red and blue LEDs with a modified long-tailed pair, adding in the green as some function of the other two? Read on to find out.

Figure 1 shows the first attempt.

Figure 1 The red and blue LEDs are driven by a long-tailed pair and controlled by pot (potentiometer) R4, whose wiper voltage varies according to its position and is used to control the green LED’s drive, producing a decently wide spectrum.

Figure 2 gives plots of the three LED currents as calculated by LTspice, which did most of this Design Idea’s heavy lifting. When pot R4’s wiper is at either end of its travel, Q1 or Q2 will be fully on and the voltage across R5 will be high (~3 V). When it’s centered, Q1 and Q2 and thus the red and blue LEDs will be largely off, but the top of R5 will fall to ~1.7 V. That 3 V is enough to hold the Darlington-pair current source Q3/4 off, while reducing it towards 1.7 V gently turns it on, proportionately driving the green LED.

Figure 2 This graph plots the LED currents against pot rotation.

This result is optimized, meaning it’s the best that Figure 1 can do, but is still rather unsatisfactory because the drives for intermediate colors—oranges, lemons, and the interesting cyans and turquoises—are badly matched, giving rather sludgy shades compared with the pure ones. Breadboarding confirmed the problem.

Take two

Some thought and a rearrangement of the circuit gave Figure 3.

Figure 3 Rearranging the circuit and adding an op-amp to drive the green LED gives better, more linear control of the LED currents.

The pot now gives a lower, more linear, drive to Q1/Q2, the green-controlling voltage being picked off from the tail resistor R1. Obviously, the voltage across R1 is at a maximum with the pot at either extreme and falls to near zero with the pot centered, when red and blue LEDs are off. A1 amplifies that voltage and drives the green LED through R7.

Figure 4 shows the sim plot, which implies that it should work much better when built…

Figure 4 The response of the revised design has more linear curves, giving a smoother spectrum.

…as indeed it does! Owing to brightness mismatches in my 10 mm diffused LEDs (common to most tri-color types) I had to drop the green drive by increasing R7 to 1k2. That drive is also affected by LED1_G’s forward voltage; turning A1 into a proper current source worked well but added more components and didn’t look any better. After fixing R7, the brightness was fairly constant over the whole available spectrum.

A rainbow, or only a portion thereof?

Ah, that weasel word “available”! This can never quite match a real rainbow or other white-light spectrum because the deepest reds and the furthest indigos and violets are outside its range—even rainbows have rather a limited palette compared with a full RGB mix. Swapping the LEDs around gives some interesting spectra (to use the word loosely) in other parts of the chromaticity diagram.

A digital departure

While the basic analog circuit may find applications where three interdependent values need to be controlled by a single pot, there is a better way to drive LEDs like this: use a micro that can read the voltage tapped from a pot and generate appropriate PWM signals to drive the LEDs, perhaps indirectly should you need kilo-lumen rainbows. This approach would also allow direct voltage control of the effects.

I have some solar-powered garden lights that use this principle to span the whole (again, “available”) RGB gamut, using what looks like my my favorite PIC 12F1501 nanocontroller containing a mere 64 bytes of RAM, but more peripherals than pins. Internal demons crank three virtual pots up and down, although low-powered operation means a low and flickery PWM rate. Time to put on the coding hat—waterproof, because rainbows imply rain—and have some digital fun doing it properly.

—Nick Cornford built his first crystal set at 10, and since then has designed professional audio equipment, many datacomm products, and technical security kit. He has at last retired. Mostly. Sort of.

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The post A pot of many colors appeared first on EDN.

Helen Duncan’s father took her to a trade show in London when she was 10 years old. She was fascinated by watching CNC machines make large mechanical parts without human involvement. Her father worked in mechanical engineering as a skilled toolmaker and later as an estimator, and he encouraged Helen to help him with car maintenance.

Helen Duncan is CEO of Blueshift Memory, a Cambridge, England-based design outfit that optimizes memory architecture to more efficiently handle large datasets and time-critical data. Its Cambridge Architecture for stored-program machines is designed to replace the current modified Harvard architecture and to overcome the traditional constraints of the von Neumann bottleneck.

Helen was talking to EDN on the eve of “International Women in Engineering Day,” which is celebrated on 23 June this year. When asked what motivated her to enter the engineering world, she pointed to physics being one of her favorite subjects in high school. “When we had to make an electric motor from scratch in a practical lesson, mine was the only one in the class that worked,” she recalled. “I was thrilled by this.”

At 13, Helen decided that electrical and electronic engineering was what she wanted to study. The more some of her teachers tried to discourage her, the more determined she became to pursue that course. “My wonderful physics teacher, Mr. Wood, a Star Trek fan, was unfailingly supportive though,” Helen acknowledged.

In the field

Helen joined the workforce in the late 1970s when only 1-2% of electronics engineers were women. “With a good degree, I had a choice of several jobs, and I accepted a position as an R&D engineer with Plessey, working on RF and microwave projects for both defense and commercial applications,” she told EDN.

Over there, direction-sensing Doppler radar modules for automatic door openers were an early design project. Later, she became a product engineering manager and hence the design authority for all the company’s microwave source products, including two mmWave subsystems for airborne radar. During those days, there was only one other female engineer working alongside Helen: a Turkish lady a few years older than her, who had a PhD from Oxford University.

Figure 1 Helen Duncan began her design work on RF and microwave projects for defense and commercial applications.

By the mid-1980s, Plessey had recruited several new graduate engineers, and surprisingly, women then made up around 25% of the engineering department, much more than the national average, which was still less than 10% at that time. “I like to think that, as I was a member of the interview panel, they were encouraged to see me as a role model who was already in a management position,” Helen recounted.

Mistaken as a caterer

When asked about the challenges of being a minority in those early days and the advantages as well, Helen said she was incredibly lucky to have some very supportive managers. “Within the company, I was unfailingly treated with respect.”

However, sometimes it was more of a problem with outsiders meeting her for the first time. Helen recalled a senior Royal Air Force officer visiting with a defense procurement team; he mistook her for a member of the catering staff, but then instantly recognized his mistake when she stood up to give a presentation.

When asked for a piece of advice she could give to young female engineers entering the electronics industry, Helen said: Believe in yourself and your abilities, and don’t allow others to undermine you or try to mansplain. “Always remain open to any opportunities that may come along, as your career may not always take the course you would expect,” she added.

Figure 2 EDN spoke with Helen Duncan, CEO of Blueshift Memory, on the eve of the “International Women in Engineering Day,” observed on June 23, 2026.

Career advice for female engineers

EDN concluded the talk with Helen by asking her which areas and disciplines female engineers should consider for long-term career prospects. “In general, I would say that no disciplines are off limits for female engineers,” she said. “However, it can be easier to progress in some of the areas that require better communication skills or a more consultative management style.”

She recalled her career trajectory over the years: she has worked in marketing at both Plessey and Rohm, and then in journalism as editor-in-chief of Microwave Engineering. “I have also been a semiconductor market analyst, a technical conference organizer, and a marketing consultant,” she said. “And I managed some of these roles concurrently.”

Most recently, Helen was headhunted for a marketing role at Blueshift Memory and later became CEO. Blueshift targets its smart memory architecture at CPU vendors, AI chip companies, and memory manufacturers; it can be used in combination with GPUs or AI accelerators, or anywhere the von Neumann bottleneck is a problem.

Figure 3 Blueshift Memory appointed Helen Duncan as its CEO in October 2024.

My career has been full of surprise opportunities and unexpected role changes, but it’s been an exciting journey,” she concluded. “And if I were starting today, I wouldn’t change anything.” That’s quite a career statement.

Related Content

• Pioneering female engineers
• Women in Tech: Profiles in Persistence
• Memory Startup Targets High-Performance Computing
• A Female Analog Designer Shares Traits for Career Success
• Blueshift Breaks Memory Wall in Data-Intensive Applications

The post Women in engineering: Helen Duncan’s journey from design engineer to CEO appeared first on EDN.

🎥 Випускний вечір Політехнічного ліцею НТУУ «КПІ» 2026 kpi вт, 06/23/2026 - 13:12

AXT Inc of Fremont, CA, USA — which makes gallium arsenide (GaAs), indium phosphide (InP) and germanium (Ge) substrates and raw materials at plants in China — says that Tracy Liu has been appointed to its board of directors, which has hence expanded from four to five directors...

DigiKey, the global distribution leader of electronic components and automation products, showcases its commitment to innovation and customer engagement at electronica Shanghai 2026.

DigiKey features an “in the wild” brand experience with in-booth and online giveaways, live demonstrations, hands-on workshops, and a live DigiKey Moment interview series featuring leading suppliers such as Analog Devices, Molex, Omron, NXP, TE Connectivity, YAGEO, and STMicroelectronics. These dynamic interviews are accessible to online audiences via DigiKey’s Bilibili channel and focus on trending topics in robotics and AI that are shaping the industry’s future.

“DigiKey is excited to participate in electronica Shanghai 2026 and meet face-to-face with our customers while offering insights and support to engineers, builders, and designers in China and beyond,” said Dave Doherty, DigiKey CEO. “In particular, our DigiKey team is thrilled to present an immersive ‘in the wild’ booth experience that celebrates the people and technology shaping our industry.”

Attendees get the opportunity to engage directly with DigiKey’s customer and application experts on-site. The DigiKey fulfillment zone also offers attendees the opportunity to sign up for a chance to win a box featuring one of five component-shaped pouch designs, with winners selected at random during the show.

DigiKey hosts The Powerhouse Panel, featuring an exclusive discussion with technology experts and industry leaders from Microchip, Molex, and NXP. Additionally, a central product showcase wall highlights a curated gallery of current electronics trends, including AI, robotics, sensing, connectivity, and power solutions from DigiKey’s supplier partners.

The post DigiKey to Stream Live Robotics and AI Supplier Interviews with Analog Devices, NXP, and STMicroelectronics appeared first on ELE Times.

In partnership with equipment provider Advanced Semiconductor Materials Lithography (ASML) of Veldhoven, The Netherlands and foundry Taiwan Semiconductor Manufacturing Corp (TSMC), nanoelectronics research center imec of Leuven, Belgium has presented a novel, robust and scalable 300mm integration route for 2D-material-based nFETs and pFETs at the 2026 IEEE/JSAP Symposium on VLSI Technology & Circuits in Honolulu, Hawaii, USA (14–18 June)...

КПІ ім. Ігоря Сікорського став лауреатом Organizational Supporting Friend of IEEE Member and Geographic Activities Award 2026 kpi пн, 06/22/2026 - 17:59

I've been building an open-source embedded systems simulator called Velxio. It supports: Arduino, ESP32, Raspberry Pi Pico and Raspberry Pi emulation Multi-board systems communicating over UART, I2C and SPI SPICE-based analog circuit simulation with ngspice Retro CPUs including Z80, Intel 8080, 4004 and 8086 MicroSD and ePaper emulation An AI agent that can generate circuits and firmware from natural language Everything runs directly in the browser. No installation, no account required. You can try it at http://velxio.dev submitted by /u/LeadingFun1849 [link] [comments]

High power density power-supply modules based on gallium nitride (GaN) devices are core components in the automotive, industrial and data-center sectors. As their integration level and power density continue to rise, the issue of dissipation of concentrated internal heat becomes increasingly prominent. Device overheating leads to thermal failure and degrades system reliability; therefore, sound thermal design is of paramount importance.

Thermal resistance analysis and power-loss calculations form the theoretical foundation of thermal design. The thermal resistance (RQJA) of a complex power system represents a coupling of the thermal resistances of numerous components, however, making it difficult to calculate precisely using theoretical formulas alone. Thermal simulation software can directly yield the coupled RQJA of the system and rapidly identify a significant operating condition – the maximum power dissipation sustainable at a given ambient temperature – thereby providing precise data guidance for thermal designs. Figure 1 shows the simulation of temperature distribution of a GaN-based power-supply system using Ansys Electronics Desktop (AEDT) Icepak software. By referring to the temperature color scale on the left, we can intuitively observe the temperature distribution and heat dissipation status of different areas based on their colors.

Figure 1 This simulation of the temperature distribution of a GaN-based power-supply system uses Ansys’ Electronics Desktop Icepak software. Source: Texas Instruments

Understanding conduction, convection and radiation RQJA

Heat transfer in a power supply occurs in three forms: conduction, convection and radiation. Thermal resistance is the core parameter for characterizing the ease or difficulty of heat transfer. Within a power supply, heat generated by semiconductor chips is transferred layer by layer through the package, solder joints, printed circuit board (PCB) copper traces, thermal interface materials and heat sinks – a process that constitutes classic thermal conduction but requires direct physical contact between materials. Equation 1 gives the thermal conduction resistance as:

where L is the length of the conduction path, k is the thermal conductivity, and A is the cross-sectional area of heat transfer.

Once heat reaches a material surface, it is transferred to the surrounding air. Taking a heat sink as an example, its fins transfer heat to the adjacent air, which rises upon heating to form natural convection, or is driven by a fan for forced convection cooling. Convective thermal resistance represents the resistance to heat exchange between a solid surface and a cooling medium, expressed in Equation 2 as:

where h is the convective heat-transfer coefficient and A is the convective heat-transfer surface area.

In addition, heat radiating from the enclosure and heat sink rises toward cooler surrounding walls or the ambient environment. Particularly under natural cooling conditions with a high temperature rise, radiated heat can account for 20% to 30% or even more of the total heat dissipation and therefore requires attention. Equation 3 gives the radiative heat flux as:

where ε is the surface emissivity, σ is the Stefan-Boltzmann constant, A is the radiating surface area, Ts is the absolute temperature of the solid surface, and Tsurf is the absolute temperature of the surrounding ambient walls.

In a practical power-supply thermal design, the three conduction, convection and radiation modes of heat transfer occur simultaneously and are mutually coupled: heat from the chip first reaches the heat sink by conduction and then flows into the environment from the heat sink’s surface by convection and radiation. Thoroughly understanding their physical meanings and governing equations is the foundation for performing thermal design and estimating RQJA.

Calculating MOSFET and magnetic component power losses as heat sources

The heat sources in a power supply originate from the power losses of its core devices, which constitute the fundamental input to thermal design.

The losses of a GaN metal-oxide semiconductor field-effect transistor (MOSFET) consist primarily of conduction losses and switching losses. Conduction loss (Pcond) is the loss produced by the root-mean-square (RMS) drain current flowing through the on-state resistance during conduction, calculated using Equation 4:

Equation 5 and Equation 6 calculate the turnon (Pon) and turnoff (Poff) losses of the MOSFET, respectively:

where VDS is the drain-to-source voltage before turnon or after turnoff; tfv and tri are the drain-to-source voltage fall time and current rise time during turnon; fsw is the switching frequency; and trv and tfi are the drain-to-source voltage rise time and current fall time during turnoff. Equation 7 expresses the total losses of each MOSFET as:

The losses of magnetic components such as transformers and inductors are the sum of core losses and winding losses. Core losses (Pcore) comprise hysteresis losses and eddy current losses, while winding losses (Pcoil) comprise DC losses and AC losses, making it one of the primary heat sources in high-frequency power supplies. Equation 8 and Equation 9 are the relevant expressions:

where PCV is the volumetric core loss, Ve is the effective core volume, RDC is the DC winding resistance, Icoil(RMS) is the RMS winding current, and RAC is the AC winding resistance.

Using Icepak simulation to extract RΘJA and determine the maximum current and temperature limits

The RΘJA of a complex power system is difficult to solve precisely through analytical methods. Icepak, a thermal simulation software package for electronic equipment from Ansys, enables system-level modeling and thermal field solving, allowing you to directly obtain the total RΘJA from simulation results, thereby compensating for the limitations of theoretical calculations.

The Icepak thermal simulation workflow comprises three broad steps:

• Model construction, which retains the heat-generating components and thermal-management structures (including chips, PCBs, magnetic components, heat sinks and enclosures); assigns the corresponding material thermal parameters; and generates the mesh.
• A boundary condition setup that applies theoretically calculated device losses as heat sources and specifies the ambient temperature, air-domain boundaries and convection mode.

Solution and output: after iterative solving, the Icepak tool obtains the temperature field distribution and junction temperatures of important devices, which it then uses to compute the total RΘJA along with the heat dissipation path from chip to ambient. Equation 10 is the formula for RΘJA:

where Tj is the chip’s junction temperature, Ta is the ambient temperature, and Ploss is the chip’s power dissipation.

After obtaining RΘJA through simulation, Equation 11 is the fundamental heat-transfer equation:

Applying this formula determines the most significant operating conditions of the power supply, yielding both the maximum permissible power dissipation at different ambient temperatures and the maximum safe ambient temperature at the rated power dissipation.

Here is an example. As shown in Figure 2, under a certain working condition, the GaN device’s power consumption is 1.16W, the ambient temperature is 70°C, and the simulation results show that the chip’s temperature is about 95°C. According to the thermal resistance formula, RΘJA is 21.55°C/W.

Figure 2 The temperature distribution of chips and the PCB they’re mounted on commonly varies. Source: Texas Instruments

After obtaining the RΘJA parameter, it is possible to calculate the chip’s power dissipation based on the specified junction temperature and ambient temperature. The chip’s power dissipation formula then determines the maximum current that can pass under different operating conditions (for calculation convenience, assume that the chip’s power dissipation equals the conduction losses, although in reality they are different). Table 1 shows the maximum allowable load current under various ambient and junction temperatures.

Tj (°C)	Ambient temperature (°C)	Power losses per GaN (W)	RDS(on) (Ω)	Imax (A)
150	25	5.80	0.00210	74.33
110	70	1.86	0.00188	44.4
125	25	4.64	0.00196	68.8

Table 1 This table documents the maximum allowable load current under various ambient and junction temperatures.

Conclusion

Thermal design is one of the most important steps to help ensure the reliability of high-power-density power supplies. Theoretical calculations of power losses and thermal resistance can clarify the heat generation and heat-transfer behavior of individual components, but cannot accurately characterize the coupled thermal resistance of complex systems.

Thermal simulation software enables efficient extraction of the total system RQJA, rapidly determining operating boundaries under varying power dissipation and ambient temperature conditions, and achieving quantitative analysis and precise optimization of thermal design.

The combination of theoretical calculation and simulation represents an efficient methodology for modern power-supply thermal design and can significantly enhance heat dissipation capability and system reliability, particularly for high-power-density GaN-based designs.

Bert Zhang (Haobo Zhang) currently works as a systems engineer in Texas Instruments’ Power Design Services team to develop power solutions using thermal simulation, magnetic simulation, and power design techniques. He earned a Master’s degree from Nankai University.

 

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Infineon Technologies AG and Amazon Web Services (AWS) to accelerate microcontroller (MCU) evaluation to shorten development cycles for automotive systems. As part of this collaboration, Infineon is launching a cloud-based platform for virtual evaluation of Infineon automotive MCUs, powered by AWS. The new platform removes dependency on physical hardware, helps to reduce evaluation cycles from multiple weeks to minutes, and significantly lowers evaluation cost per user, while supporting hundreds of concurrent users globally. The platform already includes Infineon’s next-generation RISC-V architecture.

“Development speed is a decisive competitive factor for the automotive industry and has become even more important with software-defined vehicles,” said Thomas Schneid, Vice President Software, Partner & Ecosystem Management at Infineon Technologies. “While hardware-dependent MCU evaluation has been a bottleneck for many engineering teams, our cloud-based platform is making it significantly easier for customers to get hands-on with our microcontrollers early in their development cycle. This is particularly helpful when evaluating entirely new MCUs such as our future RISC-V-based family.”

The new platform is based on the Virtual Engineering Workbench, an AWS open-source offering for automotive and manufacturing customers for digital toolchains, hardware virtualization, and infrastructure management. Infineon’s semiconductor expertise delivers a comprehensive, cloud-native virtual MCU evaluation experience. A browser-based interface eliminates local tool installation and provides a consistent workflow across operating systems, while isolated cloud environments help ensure users can experiment without impacting others. Users receive immediate feedback throughout their MCU evaluation journey.

The platform supports two primary workflows. Quick Mode enables rapid testing using pre-configured reference applications for immediate validation of MCU capabilities. Expert Mode provides a full in-browser virtual machine development environment, including compilation, flashing, debugging, and performance analysis, enabling experienced embedded developers to move from evaluation to deeper prototyping without locally installed tool chains.

The platform also introduces automation for Infineon product teams to package and release new MCU variants with minimal effort, making them available for customer evaluation instantly. Usage tracking provides insights into which MCUs and applications are evaluated most frequently, helping to optimize future product planning.

The post Infineon and AWS Launch Cloud Platform to Speed Up Automotive MCU Evaluation appeared first on ELE Times.

India’s electronics manufacturing ecosystem reaches a critical inflection point, formalizing its position as the world’s sixth-largest electronics exporter, Union Minister Ashwini Vaishnaw highlights this milestone.

The scaling of India’s domestic manufacturing capacity is part of a broader macroeconomic strategy aim at capturing secondary placement in the global electronics export hierarchy. Expanding the Semiconductor and Components Value Chain to mitigate supply chain vulnerabilities and increase Domestic Value Addition (DVA), the government is pivoting from simple assembly to deep-tech infrastructure. A core pillar of this transition is the acceleration of the domestic semiconductor Fab and ATMP (Assembly, Testing, Marking, and Packaging) ecosystem. Two semiconductor fabrication plants are currently under active construction, with structural frameworks for two additional facilities slated to break ground by the end of the standard fourth quarter. Integration verticality is being expanded in the Pune cluster with upcoming facilities dedicated to the fabrication of high-tolerance mechanical precision parts, a critical move to localize the component supply chain for semiconductor and aerospace hardware.

To further strengthen the electronics ecosystem, the government is accelerating semiconductor development, with two semiconductor plants currently under construction and two more expected to be added by the end of the year. Moreover, the statement outlined that plans are underway to begin manufacturing mechanical precision parts in Pune, enhancing domestic capabilities across the electronics and semiconductor value chain. Maharashtra is emerging as a key beneficiary of this growth, aided by investor-friendly reforms and robust infrastructure, nearly 60% of India’s data centre capacity is located in Maharashtra, reinforcing its status as a leading technology investment destination. The statement also underscores that the Mumbai-Ahmedabad Bullet Train and the upcoming Wadhvan Port project are set to boost logistics efficiency, trade, exports, and industrial development while creating one of India’s most significant economic corridors.

The post India’s Tech Manufacturing Surge Propels it to 6th Largest Electronics Exporter appeared first on ELE Times.

A gallium nitride (GaN) high-electron-mobility transistor (HEMT) incorporating the proprietary reGaN selective regrowth technology of IVWorks Co Ltd of Daejeon, South Korea has become the world’s first GaN transistor to achieve a maximum oscillation frequency (fmax) exceeding 700GHz. This was demonstrated through a 45nm GaN HEMT device developed by professor Dae-hyun Kim’s research team in the School of Electronics Engineering at Kyungpook National University and was unveiled on 18 June at the 2026 IEEE/JSAP Symposium on VLSI Technology & Circuits in Honolulu, Hawaii, USA...