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Dreading placing those SMDs… I need a PnP 😭 submitted by /u/aq1018 [link] [comments]

КПІ ім. Ігоря Сікорського та Науковий парк адитивних технологій провели воркшоп для українського бізнесу KPI4U-2 пт, 08/14/2026 - 19:16

As AI infrastructure, industrial robotics, battery management systems (BMS) and advanced power electronics drive increasing power density and efficiency requirements, accurate current sensing is becoming increasingly critical. According to market analyses, the global current-sense resistor market is projected to expand at a CAGR of approximately 6% through the coming years, reflecting growing demand across battery management, motor control and power conversion applications.

At the same time, engineers are under increasing pressure to improve energy efficiency and reduce system costs while maintaining measurement accuracy in higher power designs. To address these challenges, Panasonic Industry offers its Thick Film Current Sensing Resistors as a cost-effective alternative to conventional metal shunt resistors for selected low- and medium-current sensing applications.

Current sense resistors play a vital role in measuring electrical current and enabling its monitoring and control in applications ranging from AI server power systems and industrial robotics to battery management systems, DC/DC converters, motor drives and advanced power supplies. Accurate current detection and control support improved system performance, system protection and higher energy efficiency.

Traditionally, metal shunt resistors have been widely used for current sensing, particularly in applications requiring very low resistance values and high power-handling capabilities. However, not all current-sensing applications require ultra-low resistance values or the highest power ratings. In low- and medium-current designs with suitable electrical and thermal requirements, thick film current sense resistors can provide the required sensing performance while helping to reduce component cost.

Panasonic’s Thick Film Current Sense Resistors support efficient and accurate current measurement in low- and medium current applications where low resistance, thermal stability and cost efficiency are key design considerations. By combining advanced resistor materials, optimized trimming technology and different structural designs, including double-sided resistor structures and wide-terminal designs, Panasonic offers resistance values down to 10 mΩ, with stable resistance performance over temperature and TCR values as low as ±75ppm/°C in selected series.

A key challenge in current sensing is balancing low resistance with a low temperature coefficient of resistance (TCR), as these requirements typically involve a trade-off. Panasonic addresses this challenge through optimized resistor materials and component structures that support accurate current measurement, low power loss through low resistance values, improved heat dissipation and reduced temperature-induced drift.

For engineers working within the operating range in which thick-film and metal-shunt technologies overlap, Panasonic’s Thick Film Current Sensing Resistors offer several important advantages:

• Potential component cost savings of up to 50% compared with selected comparable metal shunt solutions in suitable applications*
• Improved heat dissipation through optimized component design, such as wide-terminal structures and double-sided resistive element structures, helping to lower operating temperatures and enhance thermal performance.
• Enhanced reliability under thermal cycling, supported by soft termination technology that helps reduce solder-joint stress.
• Supports accurate current sensing with resistance values down to 10mΩ, stable resistance performance over temperature and TCR values as low as ±75ppm/°C in selected series.
• Simplified migration through footprint-compatible designs available in selected case sizes, supporting the replacement of metal shunt resistors within the overlapping operating range.

Panasonic’s Thick Film Current Sense Resistors are already proven in customer applications and are particularly suited to AI infrastructure, robotics, battery management systems, motor control, power supplies and industrial automation systems, where designers seek to optimize both cost and performance.

As designers look for ways to improve efficiency, reduce thermal stress and manage bill-of-materials costs, Panasonic’s Thick Film Current Sensing Resistors offer a practical, cost-effective option for low- and medium-current sensing applications that require accurate measurement, thermal stability and reliable performance.

The post Panasonic Thick Film Current Sense Resistors Enable Potential Cost Savings Up to 50% as an Alternative to Metal Shunts appeared first on ELE Times.

Oscilloscopes utilize both hardware and software tools to enhance the resolution of time measurements. Happily, most of the processing is transparent.

The primary display from an oscilloscope is amplitude versus time. Most of the focus when using oscilloscopes is on the vertical axis, including amplitude resolution, analog bandwidth, and vertical accuracy. The time axis does not seem to get equal billing. That’s because oscilloscope time bases are very good.

Timebase accuracy

The oscilloscope’s timebase generates the sampling clock, which samples the input signal at uniform time intervals at the sampling rate. The sampling rate and the length of the acquisition memory determine the horizontal scale factor. The timebase clock of an oscilloscope has a frequency accuracy generally specified in parts per million (ppm) or parts per billion (ppb).

For example, an instrument with a timebase specified as accurate to within ± 0.1 ppm (100 ppb). This means that any time interval, T, being measured is accurate to within ± 0.1/106 of the value of T. If the measured interval is one second, the uncertainty of the measurement is ±1×10-7 seconds or ±0.1 microseconds (ms).

Clock oscillators are subject to frequency drift over time. This timing uncertainty is cumulative and increases as the oscillator operates over longer periods. That drift, called aging, is usually specified as an additive uncertainty in frequency, expressed in parts per million per year (ppm/yr). A typical clock timebase accuracy specification might be ±0.1 ppm + 0.05 ppm/year. The time is measured from the instrument’s last calibration.

If the oscilloscope’s internal timebase is not as accurate as desired or if the oscilloscope’s operation must be synchronized with other instruments, many oscilloscopes include an external clock reference input. The external reference is usually generated from a very stable signal source at either 10 or 100 Megahertz (MHz), which is used to synchronize the internal timebase to the reference input to improve its accuracy.

Improving time resolution

The time resolution of a digitizing instrument, based only on the sampling clock frequency, would be the reciprocal of the sampling rate. An oscilloscope that samples at 40 gigasamples per second (GS/s) would have a time resolution of 25 picoseconds.

Oscilloscopes enhance hardware time resolution by using a specialized frequency counter called a time-to-digital converter (TDC). In real-time acquisition mode, the time-to-digital converter measures the time between the trigger event and the next sample.

In general, the trigger event and the sample clock are not synchronous. The time delay between these two events is uniformly distributed over the sampling period. The uniform distribution means that any time delay between zero and the sampling period is equally possible. The time delay for each acquisition is called the horizontal offset and is a characteristic of the acquired waveform. Figure 1 shows a horizontal offset measurement.

Figure 1 A typical measurement of the horizontal offset of an acquisition measuring time between the trigger point and the next sample point.

The figure shows an acquired waveform. The bright dots on the waveform indicate the real samples.

Horizontal relative cursors provide a visual measurement of the time between the trigger point and the next following sample and display the Δx value of 12.5 ps in the cursor readout field in the lower right corner. The TDC output provides an exact digital readout internally.

The time resolution of the TDC is much finer than the sample rate. In this specific example, it is five ps. The horizontal offset is used to align waveform samples for display and measurements. It is also used to combine multiple acquisitions of a periodic waveform into a random interleaved sampling acquisition.

Random interleaved sampling

Random interleaved sampling (RIS) is an acquisition mode that enhances the instrument’s time resolution when measuring multiple periodic waveforms with a stable trigger point. The oscilloscope acquires multiple waveforms, each with the same shape (Figure 2).

Figure 2 The horizontal offset, time delay between the trigger and the next sample, is uniformly distributed over the sampling period; multiple acquisitions show this variation.

Each acquired waveform has a horizontal offset uniformly distributed over the sampling period. Multiple acquired waveforms will each have a different horizontal offset. Examining the time difference between the trigger point and the first sample that follows in the figure illustrates this variation. Overlaying the twelve waveforms shows how they synthesize a waveform with an effectively higher sample rate (Figure 3).

Figure 3 Creating a composite waveform from multiple acquisition results in a higher effective sample rate.

The oscilloscope measures the horizontal offset of each waveform and categorizes them to select those whose values are multiples of the desired effective sampling rate. These selected waveforms are combined to form the RIS waveform (Figure 4).

Figure 4 This graph compares a real-time and RIS waveform.

The lower waveform in the figure is the real-time acquisition. Cursors mark a 25 ps sampling period of the real-time waveform.  The upper trace is the RIS acquisition. Note that there are five effective sample periods between the cursors; the effective sample rate is five times the 40 GS/s sample rate, or 200 GS/s. Remember that the RIS acquisition mode requires multiple repetitive acquisitions with the identical waveform using a stable trigger point.

Sequence mode

Sequence mode is another acquisition mode that uses the TDC. This mode is used to minimize the dead time between adjacent acquisitions. It is also applied to reduce the time between acquisitions. Sequence mode breaks the acquisition memory into a user-defined number of segments. Each segment holds a single acquisition. Since the oscilloscope does not need to display the trace between segments, the dead time between acquisitions is minimized.

The downside of this mode is that the time between segments is indeterminate as the instrument waits for the next acquisition trigger. To counter this, the oscilloscope marks the location, in time, of each segment in two ways.

First, it labels the start of each segment using the oscilloscope’s real-time clock to label each trigger time. The real-time clock has a resolution of one second, which is not practical for fast acquisitions. It also uses the TDC to measure the time delay of each trigger from the first trigger in the acquisition (Figure 5).

Figure 5 A sequence mode acquisition of five ultrasound pulsed bursts showing the sequence mode time stamps.

The figure shows a sequence-mode acquisition of five ultrasonic pulse bursts, each in its own segment. The sequence mode time stamps appear under the graphic display, including the absolute time from the oscilloscope’s real-time clock in the column labeled time. Additionally, it lists the time from the start of the first segment and the time between segments. These TDC-measured times are displayed with a resolution of one nanosecond.

The time stamps indicate the timing of the trigger events. It basically places each segment at a specific time. If each trigger event is an anomaly, then the time stamps provide the frequency of the anomalies, a bit of diagnostic information that often proves useful.

Interpolation

If the TDC is the hardware tool for precise time measurements, then interpolation is the software tool. Interpolation is a mathematical technique for increasing the effective sample rate of an acquired signal. Interpolation calculates intermediate sample values between the real-time samples. Interpolation is usually applied to the displayed data, but in many cases, it is incorporated into application-specific measurements.

Interpolation is also available as a math function and can be used to increase the time resolution of acquired waveforms. The oscilloscope used in this article offers sin x/x, linear, or cubic interpolation with sampling rate improvement from two to fifty calculated points per real-time sample.  Interpolation increases instrument processing time proportional to the number of interpolated samples.

On the positive side, interpolation can be applied to single-shot acquisitions. On the downside, interpolation requires that the data meet the Nyquist criteria and have a sample rate greater than twice the signal’s bandwidth. Failure to satisfy Nyquist can result in significant errors. From a data integrity perspective, it is essential to note that RIS data comprises all real samples, whereas interpolated data is a combination of real and calculated sample values.

Jitter measurements

Jitter is a short-term variation in the timing of a digital signal from its nominal value. Any timing parameter can be the subject of jitter analysis, and the main timing parameters considered are variations in width, period, and time-interval error (Figure 6).

Figure 6 This graphic gives examples of timing uncertainty in width, period, and time interval error jitter, including jitter measurements along with the histogram of time interval error.

Width or period jitter can be measured using the width and period measurement parameters, respectively. The jitter is evident in the statistical readouts for minimum (min), maximum (max), and standard deviation (sdev). The difference between the maximum and minimum is the range or peak-to-peak jitter. The standard deviation is the root-mean-square (RMS) jitter.

Time interval error (TIE) measures the difference between each actual waveform edge and the ideal location of that edge. The ideal edge locations are computed from the waveform’s mean frequency.  TIE can be thought of as the instantaneous phase of the signal.

 The time parameters period, width, and TIE are measured by determining the time between edges. For a period, it is the time between adjacent edges with the same slope. For the width measurement, it is the time between adjacent edges with different slopes. TIE measures the time between an acquired edge and an ideal edge. The measurement uses interpolation to achieve the highest possible time resolution (Figure 7).

Figure 7 A dual interpolator finds use in obtaining a more precise measurement time resolution.

The figure shows an edge defined by three real-time samples taken with a 10 GS/s sampling rate. The interpolator uses a cubic interpolation to fit several interpolated samples between each real-time sample. Then, the two samples that bracket the measurement threshold are used to perform linear interpolation to determine the time at which the measurement threshold is crossed. The resulting measurements in this example have a resolution better than 1 picosecond.

Jitter has both random and deterministic components.  Random jitter is associated with stochastic processes, such as noise, and is unbounded, meaning it increases with increasing observation time. Deterministic jitter is bounded, and its amplitude is limited with increasing observation time. The random components of jitter are studied using statistical tools, such as histograms.

Figure 6 shows the histogram of the TIE parameter. There are parameters intended to interpret histograms themselves. The histogram mean (hmean), mode (hmode), standard deviation (hsdev), and range (hrange) are examples of histogram-specific parameters.

Conclusion

Oscilloscopes utilize both hardware and software tools to enhance the resolution of time measurements. Improved time resolution is used both in displaying the data and in measurements. Happily, most of the processing is transparent and requires little user interaction to achieve good results.

Arthur Pini is a technical support specialist and electrical engineer with over 50 years of experience in electronics test and measurement.

Related Content

• Using an oscilloscope’s time, frequency, and statistical measurement domains
• Basic oscilloscope operation
• Analyze noise with time, frequency, and statistics
• Oscilloscope special acquisition modes
• How to perform histogram analysis on your oscilloscope
• Basic jitter measurements using an oscilloscope
• Closing the gaps in your digital oscilloscope waveforms

The post Secrets of oscilloscope time measurements appeared first on EDN.

MongoDB, Inc. today announced at MongoDB .local Build Fest that MongoDB’s intelligent data platform is now available natively inside the AI tools developers use to build applications. Available today, MongoDB Atlas Managed MCP Server is a fully hosted way to connect agents to Atlas without running additional infrastructure. Builders can now easily add MongoDB Atlas to Claude Code, Codex, Grok Build and Devin. Everything announced today is available now, and teams can get started with Atlas for free at mongodb.com/atlas.

“The AI tools teams reach for keep changing, so our approach is to make sure MongoDB is present in all of them, whether a team is working in Claude or Codex, or running an agent in production. More of that building is now done by agents, and neither the agent nor the developer has to stop and set up a connection, so applications come together faster,” said Pablo Stern-Plaza, Chief Product Officer, AI and Emerging Products, MongoDB.

With the new connectors, MongoDB is available natively across the tools where software is built. Ask questions of data in plain language in ChatGPT, Claude, and Grok. Query, inspect, and update data in MongoDB as work happens, with coding agents like Claude Code, Codex, Grok Build and Devin. And builders can also see live MongoDB data while generating an app in an IDE like Cursor.

Getting connected with these tools takes only a few clicks. Find the MongoDB connector in the tool’s marketplace and authorize it, with no connection string to paste and no infrastructure to configure. Once connected, the tool can list collections and indexes, query and aggregate data, and inspect schemas—and with the right permissions—can also create collections or manage indexes.

Introducing the MongoDB Atlas Managed MCP Server

Running an agent in production means connecting it to real operational data and agent memory, and until now, teams had to build and maintain that connection themselves. MongoDB’s MCP server already sees more than 30,000 installs a week. Starting today, the MongoDB Atlas Managed MCP Server is remote and fully hosted, running as a service inside Atlas, so there is nothing for a team to install, operate, or upgrade. Teams connect using the same credentials and access controls they already use with Atlas, so administrators can govern how agents access operational data from one place.

“Developers want their AI tools to connect with the context and systems they already rely on,” said Vibhor Chhabra, Product Lead for ChatGPT Ecosystem at OpenAI. “MongoDB’s plugin in ChatGPT makes it easier to access and work with live application data, helping developers move faster while staying grounded in the context of their applications.”

“We’re in the golden age of software engineering. The scope of what one engineer can build has exploded, and the unlock is agents working with real context,” said Russell Kaplan, President at Cognition, the company behind Devin. “By connecting Devin to MongoDB Atlas, engineers can hand off well-scoped tasks knowing Devin is working from live application data, not stale assumptions, and spend their own time on the harder problems.”

MongoDB also announced at Build Fest new capabilities that bring its benchmark-leading Voyage AI retrieval models into the operational database, including Automated Embeddings in MongoDB Atlas powered by Voyage AI, the Atlas Embedding and Reranking API, and voyage-code-4: https://www.mongodb.com/company/newsroom/press-releases/mongodb-atlas-now- delivers-industry-leading-context-retrieval-with-precision-accuracy

The post MongoDB Brings Live Operational Data to the Agentic Coding Stack appeared first on ELE Times.

The growing New Space market is fueling demand for smaller, less expensive space hardware to support short-duration missions for applications such as satellite-to-cellular communications, alternative navigation and Earth imaging. Microchip Technology today announces it expanded its atomic clock portfolio with the radiation-tolerant Space CSAC-SA65, a Chip Scale Atomic Clock designed to deliver precise timing for space systems. The device provides a compact, low-power alternative to traditional radiation-hardened timing solutions, helping developers reduce size, weight, power and cost while maintaining accuracy.

Building on the heritage of Microchip’s Space CSAC-SA45, the Space CSAC-SA65 extends radiation tolerance to at least 30 kRad and operates in extended temperature ranges from –40°C to +80°C. Consuming less than 120 mW and occupying less than 17 cc of volume, the device is optimized for size-, weight- and power-constrained satellite designs. Its built-in 1 PPS input and output capabilities support synchronization for satellite systems, while its atomic stability enables extended operation without continuous reliance on external timing references such as Global Navigation Satellite System (GNSS) signals.

“By enabling one of the lowest power atomic clocks to thrive in extreme conditions, even the smallest CubeSat can now fly with atomic accuracy,” said Randy Brudzinski, corporate vice president of Microchip’s frequency and time systems business unit. “The Space CSAC-SA65 brings atomic-clock performance to applications where size, weight, power and cost are tightly constrained, helping developers maintain synchronization and timing accuracy even when external timing references are unavailable.”

Manufactured as a Commercial Off-The-Shelf (COTS) product using radiation-tolerant commercial electronic components, the device can offer shorter lead times and lower overall costs compared to traditional space-grade oscillators. Designed for Low Earth Orbit (LEO) missions, the CSAC-SA65 is well suited for applications including satellite timing and frequency control, satellite clock reference, assured positioning, navigation and timing (PNT), and satellite cross-linking.

Microchip offers an extensive portfolio of clock and timing systems, ranging from miniature component oscillators, to small plug-in timing server cards, to multi-rack time scale systems. As a primary contributor to the world’s time, Microchip’s timing solutions are trusted, reliable and resilient. For more information, visit Microchip’s Clock and Timing Systems web page.

The post Microchip Advances Space-Grade Timing with Enhanced Radiation Tolerance and Extended Temperature Performance appeared first on ELE Times.

STMicroelectronics has extended the STGAP3S family of gate drivers that feature enhanced galvanic isolation for greater reliability, introducing an efficient and economical 3A series for circuits that need lower drive current. The new STGAP3S3S is optimized for silicon carbide (SiC) MOSFETs, while the STGAP3S3IF is suited to IGBTs.

All STGAP3S drivers work with high-voltage rails up to 1200V in circuits such as power-factor correction (PFC), power supply units, DC/DC converters, and inverters. International safety and insulation certifications, including UL 1577 and IEC 60747-17, independently confirm robust isolation, safe operation, and reliable long-term performance at high voltage.  Typical applications include charging stations, energy-storage systems (ESS), solar inverters, industrial electric vehicles like forklifts, induction heating equipment, and general drives, pumps and fans.

ST’s state-of-the-art reinforced galvanic isolation protects the power-stage circuitry against transients up to 9.6kV and ensures Common Mode Transient Immunity (CMTI) up to 200V/ns. The family contains three series capable of sinking/sourcing up to 10A, 6A, and now 3A, each containing variants optimized for driving IGBTs and silicon-carbide MOSFETs.

The new STGAP3S3 series, with 3A drive strength, integrates the complete active Miller clamp, including clamping MOSFET, to prevent unwanted induced turn-on of the power switch thereby avoiding shoot-through currents. Integrating the MOSFET saves PCB space, simplifies the circuit design, and reduces the bill of materials, while providing suitable clamping performance with gate drive up to 3A. The 6A STGAP3S6 and 10A STGAP3SX series contain a pre-driver for an external MOSFET, giving extra flexibility to optimize the clamping speed in systems with high gate-drive current.

All STGAP3S drivers have desaturation detection with soft turn-off to ensure controlled voltage and current transitions, which protects the power switch during dangerous overload or short-circuit conditions. The 6A and 10A drivers, and the new 3A drivers for SiC MOSFETs, let designers connect an external resistor to optimize the soft turn-off speed.

All devices have diagnostic pins that indicate when desaturation protection, undervoltage-lockout UVLO, and thermal shutdown are active. The drivers allow negative gate voltage that strengthens unwanted turn-on prevention, protects the device during fault turn-off, and ensures robust switching without ringing during normal turn-off transitions.

An evaluation board is available for each STGAP3S driver, including the latest 3A models. These two boards, the EVLSTGAP3S3S and EVLSTGAP3S3IF, are half-bridge boards that come with protection already configured and provide test points and diagnostic LEDs to assist development.

The complete STGAP3S family for driving IGBTs and SiC MOSFETs, including STGAP3S3, STGAP3S6, and STGAP3SX series, is in production now. The drivers are offered in the SO16W wide-body package, from $1.93 for orders of 1000 pieces.

The post STMicroelectronics’ New Galvanically Isolated Gate Drivers Simplify Power Design with Advanced Isolation appeared first on ELE Times.

submitted by /u/1Davide [link] [comments]

Гордість КПІ: студентів та випускників відзначено до Дня молоді 2026 kpi чт, 08/13/2026 - 22:31

Odorless. Colorless. Tasteless. But certainly not harmless. Radon, in both air and ground water, is a health risk whose prevalence should be regularly assessed and, if necessary, dealt with.

Beginning last fall and continuing through early summer, my community built an emergency access road that links up with a state highway below us and provides an alternate escape path in case of fire or other calamity, a particularly appealing option for those (like me) whose homes are at the far end of the community.

Road construction involved, among other things, the use of dynamite to blast pathways through rocky hillsides. And shortly after road completion, I learned that a residence a few minutes’ walk away from us had tested positive for high radon levels and was in the process of installing a mitigation setup.

Were the two events—earth disturbance due to road construction and radon release—related? I don’t know, and I’m not forward enough to ask the neighbors, but it’s possible. Regardless, even though our home had successfully passed a radon test done as part of the pre-purchase inspection more than a decade ago, I was motivated to learn more about radon and then re-test the premises for myself to see if the situation had subsequently evolved in an adverse direction.

Uranium and radium decay

As usual, I began my education with a visit to Wikipedi’s radon entry.

Radon is a chemical element; it has symbol Rn and atomic number 86. It is a radioactive noble gas and is colorless and odorless. Of the three naturally occurring radon isotopes, only 222Rn has a sufficiently long half-life (3.825 days) for it to be released from the soil and rock where it is generated. Radon isotopes are the immediate decay products of radium isotopes.

Here’s more.

A common source of environmental radon is uranium-containing minerals in the ground. Radon can also occur in ground water, such as spring waters and hot springs. Radon trapped in permafrost may be released by climate-change-induced thawing of permafrosts, and radon may also be released into groundwater and the atmosphere following seismic events leading to earthquakes, which has led to its investigation in the field of earthquake prediction.

Seismic events leading to earthquakes…and possibly also dynamite blasts? Here’s where the prose turned worrisome.

Epidemiological studies have shown a clear association between breathing high concentrations of radon and incidence of lung cancer. Radon is a contaminant that affects indoor air quality worldwide. Because radon is denser than air it accumulates in basements and crawlspaces under dwellings. According to the United States Environmental Protection Agency (EPA), radon is the second most frequent cause of lung cancer, after cigarette smoking, causing 21,000 lung cancer deaths per year in the United States. About 2,900 of these deaths occur among people who have never smoked. While radon is the second most frequent cause of lung cancer, it is the number one cause among non-smokers, according to EPA policy-oriented estimates.

And finally, there’s this from the related Wikipedia entry for radon mitigation.

There is no proven link between radon in water and gastrointestinal cancers; however, extremely high radon concentrations in water can be aerosolized by faucets and shower heads and contribute to high indoor radon levels in the air.

Yikes!

Radeon prevalence varies across the United States and, more broadly, the world at large. It turns out that Denver, Colorado and surrounding regions have among the highest U.S. concentrations, as the following two related graphics show. The first documents the predicted fraction of U.S. homes having concentrations of radon exceeding the EPA’s recommended action level of 4 pCi/L. Note the orange region smack dab in the middle of Colorado, right where my residence is located.

And then there’s this one, which formats the data slightly differently, but ends up with the same essential outcome.

The most concise and clarifying data I came across related to my specific situation comes from an informative page (and a highly recommended read, even if you’re not a neighbor of mine) on the Jefferson County website.

Approximately 50% of homes in Jefferson County test above the EPA action level for radon every year.

It’s followed by this.

Radon is found throughout the U.S. and is particularly prevalent in Colorado. The U.S. Environmental Protection Agency (EPA) has ranked Colorado as a Zone 1 area, meaning the average house will exceed the EPA’s action level for indoor radon.

Once again: yikes! I guess that’s why I see mitigation setups (more on them later) like this one all over the community.

Testing scenarios and equipment options

The Jefferson County webpage on radon also includes these non-scientist explanation statements that I thought were enlightening.

Radon is an invisible, odorless, tasteless, cancer-causing gas that comes from the natural radioactive breakdown of uranium and radium in soil, rock and water. Radon enters buildings through cracks, holes and pipes in the foundation. All buildings contain some radon, but homes are the most concerning since that is where families spend most of their time.

There’s also this.

Radon is produced as a decay product from uranium and radium. This naturally occurring radioactive gas is found in most soil, rock, and groundwater. Since radon is a gas, the inert element can easily travel through cracks and pores without being chemically bound or attached to other elements. Voids and porous materials are found under every building, allowing radon easy entry.

Perhaps obviously, once again quoting from the Jefferson County website, “the test kit should be placed in the lowest occupied level (typically a basement) and in the normal breathing zone (about 2-6 ft. from the floor) and 3 ft. from windows, doors, vents, or anything that allows airflow.”

Preferably, in fact, windows, doors (especially screened) and other outside-air ventilation sources should be shut as much as possible through the entire multi-day testing cycle to minimize gas dilution and maximize negative pressure (aka, “stack effect”) flow into the home, thereby simulating the worst-case radon accumulation that would normally occur in winter and other closed-off times (that said, air conditioning systems are another common catalyst for high radon gas leakage into buildings).

Free radon test kits are available to me from both Jefferson County and the Colorado Department of Public Health and Environment and can also be bought from local hardware and home improvement stores and online retailers. Keep in mind, however, that the kit still needs to be sent in for post-test analysis, with results subsequently sent back to the submitter, all steps incurring delays.

Yet another gizmo-acquisition opportunity

Instead, especially since I’m a techie who can’t resist new toys, I decided to buy my own radon detector hardware. The Airthings Corentium Home 2 (stock photos and promo video follow) normally costs around $180, but I found one promotion-priced on the Resale (formerly Warehouse) area of Amazon’s website for $121.46.

Versus its first-generation predecessor, it supplements the integrated display with Bluetooth LE and SmartLink (Airthings’ proprietary wireless protocol) connectivity to a separate device.

And battery life extends from 1.5-2 years (3 AAA alkaline batteries) with the original Correntium to 2-3 years (two AA alkaline batteries).

Here’s my own unit, starting with outer packaging shots.

Now open, with the contents accompanied by a 0.75′′ (19.1 mm) diameter U.S. penny for size comparison purposes.

Inside, of course, is the Corentium Home 2, along with some literature (also found online here) and a silica gel packet.

Here’s the open backside; batteries are included, with only a thin slip of plastic needing to be removed to complete the connection. Activate them as the power source and start testing.

Mating and initial setup of the device with my smartphone—which subsequently receives periodic notifications from it—was uneventful.

And, after a preparatory 24-hour delay over which the device collected and averaged (but did not yet share with me) its initial data set, preliminary results were encouraging.

I kept the measurements going for nearly three weeks before capturing another screenshot set, and the good news thankfully kept coming.

The application (Android in my case, but iOS also available) displays trend graphs, too, useful to see how radon levels, along with also-measured humidity and temperature, varied over time.

Mitigation methodology

All well and good, though I plan to continue conducting going-forward measurements, since radon gas levels vary over time due to a variety of factors. But what if my results had been more concerning? Step one is to seal off as much as possible any soil-sourced radon gas leakage coming into the house through slab and foundation cracks; more substantial slab voids resulting from floor drains and sump pumps are also potential culprits, albeit harder-to-eliminate ones.

Next, strive to minimize negative pressure (stack effect) situations, where the inside-house air pressure is lower than that of the outside, generating a partial vacuum condition that pulls air in from below the residence in attempting to equalize the differential. Frequent, vigorous use of HVAC systems is a potential root cause of pressure imbalances, along with attic fans, bathroom and kitchen-cooking-appliance exhausts, and the like. Keeping windows and screen doors open whenever weather and broader seasonal temperatures afford this option, as earlier mentioned, is helpful albeit only as temporary workarounds.

The most significant mitigation measure, and one that per my earlier shared photo I see frequently around my community, involves the installation of an active soil depressurization system. A PVC pipe originating below the home’s foundation, commonly in combination with a continuously running inline fan, draws radon gas out and up to the roof where it’s safely exhausted, completely bypassing the residence interior (and its inhabitants) in the process.

A tutorial video I found online showcases an in-home mitigation system installation.

I found it interesting for two main reasons, among others:

• The system’s location: I’d previously only been familiar with exterior-visible setups such as the one in the earlier-shown photo. I now wonder how many more homes in my community have implemented radon mitigation, internally (and therefore invisible to me from the outside) in these latter cases.
• And the initial, albeit unsuccessful, attempt to rely solely on a passive system, later supplemented by an active fan to create sufficient incremental suction.

I’ll wrap up here and turn it over to you for narration of your radon-related experiences and broader thoughts in the comments. Thanks as always in advance for them!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

• Improve HVAC efficiency with accurate sensors
• My Geiger counter doesn’t count (sob sob)
• Design femtoampere circuits with low leakage, part 1 and part 2

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Sivers Semiconductors AB of Kista, Sweden (which supplies RF beam-former ICs and lasers for AI data-center, SATCOM, defense and telecom applications) and SemiNex Corp of Danvers, MA, USA – which designs and makes indium phosphide (InP) lasers diodes, DFB lasers, semiconductor optical amplifiers (SOAs) and external-cavity lasers – have announced a program for next-generation InP light sources for AI data-center interconnects...

The Controller Area Network (CAN) extended data-field length (XL) specification—which has been standardized for years—now has the first commercially available CAN XL transceiver. Texas Instruments has unveiled the TCAN6062 CAN XL transceiver, which supports payloads of up to 2,048 bytes per frame and data rates up to 20 Mbps.

The CAN XL transceiver ensures that priority messages are delivered first and on time, facilitating performance critical to humanoid robots, industrial robots, and human-machine interface (HMI) systems. This allows system designers to leverage CAN XL to exchange data rapidly and reliably in applications ranging from industrial robotics to automotive safety.

Figure 1 The CAN XL technology is promising to open the door to a new era of applications. Source: Texas Instruments

The new CAN XL transceiver is also backward compatible with CAN flexible data rate (FD) and CAN signal improvement capability (SIC) operations. This ensures a seamless migration and enables design teams to evolve existing designs incrementally without requiring a full redesign.

Next, while CAN XL is better and cheaper than CAN FD, it can also tunnel Ethernet. So, the CAN XL transceiver allows engineers to consolidate communication layers and use Ethernet in mixed-network architectures with Transmission Control Protocol/Internet Protocol (TCP/IP) tunneling. That facilitates efficient transfers of diagnostics, sensor data, control traffic, and over-the-air (OTA) updates on a single network.

Figure 2 The TCAN6062 CAN XL transceiver helps reduce ringing by up to 80% in complex networks, simplifying validation in high-node architectures. Source: Texas Instruments

CAN has been the backbone of industrial communications for decades. However, industrial systems are now generating and demanding more data than ever before. That’s because applications require fast, deterministic communication to synchronize motion control, sensor feedback, and diagnostic data. That, in turn, leads to new networking requirements, and as a result, engineers often accept system-level trade-offs to compensate for bandwidth constraints.

Dwight Byrd, GM of Interface Products at TI, claims that the TCAN6062 CAN XL transceiver bridges that gap. “It offers engineers a path to higher-bandwidth networks while maintaining the proven reliability CAN is known for.”

“As industrial systems become more intelligent and interconnected, what we ask of our networks continues to evolve,” Byrd added. “Engineers need more data, higher speeds, and greater flexibility, all without compromising performance or reliability.

TI’s networking technology managers are confident that CAN XL will open the door to a new era of applications, enabling systems to deliver higher performance at a reasonable cost. And here, TI has the first-mover advantage.

Related Content

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• CAN: Network for Thousands of Applications Outside Automotive
• Signal Chain Basics: Industrial Market Transitions to 3.3V CAN Transceivers

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New TCAN6062 CAN XL transceiver delivers the highest bandwidth and largest payload of any CAN-based network while preserving the advantages of proven CAN protocols.

What’s new?

Texas Instruments (TI) today introduced the industry’s first commercially available CAN XL transceiver, designed to help industrial engineers keep pace with the growing data demands of modern networks. TI’s TCAN6062 Controller Area Network (CAN) extended data-field length (XL) transceiver supports payloads up to 2,048 bytes per frame and data rates as high as 20Mbps, while ensuring that priority messages are delivered first and on time with the performance on which humanoid robots, industrial robots and human-machine interface (HMI) systems depend.

The TCAN6062’s backward compatibility with CAN flexible data rate (FD) and CAN signal improvement capability (SIC) operations enables seamless migration to CAN XL, allowing teams to evolve existing designs incrementally without requiring a full redesign. Additionally, the transceiver allows engineers to consolidate communication layers and use Ethernet in mixed network architectures with Transmission Control Protocol/Internet Protocol (TCP/IP) tunneling, enabling efficient transfers of diagnostics, sensor data, control traffic and over-the-air updates on a single network.

Why does it matter?

Industrial systems are generating and demanding more data than ever before, with applications requiring fast, deterministic communication to synchronize motion control, sensor feedback and diagnostic data. These applications have introduced new networking requirements, often leading engineers to accept system-level trade-offs to compensate for bandwidth constraints. TI’s TCAN6062 CAN XL transceiver bridges that gap, offering engineers a path to higher-bandwidth networks while maintaining the proven reliability CAN is known for.

The specification for CAN XL has been standardized for years, but TI is the first to deliver and bring the hardware that makes it possible to the mass market. By introducing the TCAN6062, TI is transforming the innovative protocol into a broadly available, ready-to-use solution that engineers can implement in their next-generation designs.

“As industrial systems become more intelligent and interconnected, what we ask of our networks continues to evolve,” said Dwight Byrd, general manager, Interface Products at TI. “Engineers need more data, higher speeds and greater flexibility, all without compromising performance or reliability. TI’s TCAN6062 CAN XL transceiver puts that capability in their hands today, helping them build faster, more capable industrial systems.”

The TCAN6062 CAN XL transceiver’s SIC helps reduce ringing by as much as 80% in complex networks, simplifying validation in high-node architectures. Combined with wide input/output voltage compatibility and protection up to ±58V, the transceiver offers broad design flexibility across a range of industrial applications.

More details

As members of the CAN in Automation (CiA) technical group that developed International Organization for Standardization (ISO) 11898-2:2024, TI’s engineers helped shape the physical layer specification for CAN XL, ensuring the protocol was built to support the real-world demands of industrial applications.

“CAN has been the backbone of industrial communications for decades,” said Holger Zeltwanger, managing director at CiA. “Texas Instruments’ long-time membership and collaboration with CiA builds on that legacy, helping shape CAN XL by contributing to a standard that will guide the entire industry. Now with the introduction of the first commercially available CAN SIC XL transceiver, CAN XL is accessible to engineers worldwide, reflecting our shared commitment to solving the engineering challenges of today and tomorrow.”

“CAN XL opens the door to a new era of applications, enabling systems to deliver higher performance at a reasonable cost. CAN XL is the better and cheaper CAN FD, but can also tunnel Ethernet,” said Arthur Mutter, Ph.D., chairman of the CAN XL Special Interest Group at CiA and senior executive, Networking Technologies at Bosch. “With TI now offering a CAN SIC XL transceiver, system designers can leverage CAN XL to exchange data rapidly (up to 20 Mbit/s) and reliably in all applications, from industrial and robotics to automotive safety.”

The TCAN6062 represents the next generation of TI’s industry-leading CAN transceiver portfolio. Spanning CAN FD, CAN SIC and now CAN XL, TI offers a comprehensive range of solutions, giving engineers the flexibility to deliver more data faster, farther and more reliably.

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Applied Materials, Inc. today announced that the University of California, Berkeley will join the company’s EPIC Center in Silicon Valley as a research collaborator. Working side by side with Applied’s scientists and engineers, UC Berkeley faculty and students will pursue high-impact research programs to accelerate the material and process innovations that are foundational to AI computing.

“The EPIC Center is designed to bring together the best minds from industry and academia in a high-velocity, manufacturing relevant environment to dramatically accelerate the development and commercialization of next-generation semiconductor technologies,” said Dr. Prabu Raja, President of the Semiconductor Products Group at Applied Materials. “Few institutions have shaped modern chipmaking as profoundly as UC Berkeley. Expanding our research collaboration at the EPIC Center strengthens the lab-to-fab innovation pipeline and gives us a powerful platform for developing the semiconductor talent the industry will depend on for decades to come.”

Research universities generate many of the ideas that become tomorrow’s semiconductor materials and process technologies, yet those ideas advance fastest when researchers can test them on the same equipment used by global manufacturers. Applied’s EPIC Center gives university researchers access to industry-scale tools, enabling rapid iteration, earlier validation and a smoother handoff from discovery to deployment.

UC Berkeley brings a history of translating foundational research into commercial semiconductor technology. UC Berkeley engineers built the first research laboratory at a university dedicated to prototyping integrated circuits in 1962. In the decades that followed, the institution produced breakthroughs the entire industry now runs on – among them the SPICE circuit simulator and the FinFET, the three-dimensional transistor that is now the basis of leading-edge logic manufacturing worldwide. That heritage of moving inventions out of the lab and into high-volume production is precisely what the EPIC Center is built to accelerate.

“Pioneering innovations by UC Berkeley researchers have enabled advancements in semiconductor chip technology, resulting in the exponential growth of computing that has ushered in the AI era,” said Mark Asta, dean of UC Berkeley’s College of Engineering. “Applied Materials’ new EPIC Center in the heart of Silicon Valley aims to speed the translation of university inventions into commercial products by providing early access to cutting-edge, industrial-scale semiconductor process equipment and technologies. I look forward to advancing research and supporting new engineering talent through this R&D collaboration with Applied Materials.”

Applied and UC Berkeley already share strong ties through semiconductor research collaborations and shared laboratory space, including work connected to the Berkeley Emerging Technologies Research (BETR) Center and the Center for Information Technology Research in the Interest of Society (CITRIS). A large network of UC Berkeley alumni works at Applied as engineers, scientists and managers, and Applied recruits from the campus each year. Both organizations are rooted in the same Silicon Valley ecosystem, allowing ideas, people and equipment to move easily between campus and industry.

Applied’s new EPIC (Equipment and Process Innovation and Commercialization) Center in Silicon Valley represents the largest ever U.S. investment in advanced semiconductor equipment R&D. The center is designed from the ground up to dramatically reduce the time it takes to commercialize breakthrough technologies from early-stage research to full-scale manufacturing. The facility is on track to become operational in 2026.

 

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BAE Systems Inc says that its FAST Labs research, development and production organization of Nashua, NH, USA has completed Phase 1 of the US Defense Advanced Research Projects Agency’s (DARPA) program Technologies for Heat Removal in Electronics at the Device Scale (THREADS) and has been awarded continued support to move into Phase 2...

PayU, India’s leading diversified fintech platform, today announced the launch of Accessible Payments Checkout, India’s first RBI-compliant payment checkout designed for people who are blind or visually impaired. The launch marks a significant step towards making digital payments more accessible and inclusive. As the country celebrates Independence Day, the launch reinforces the importance of ensuring that everyone can participate in the digital economy with greater independence.

With this launch, PayU becomes the first payment gateway in India to comply with the Reserve Bank of India’s October 2024 accessibility mandate (BIS IS 17802). The enhanced checkout introduces a range of features designed to improve discoverability, navigation, and interaction for users with visual and cognitive accessibility needs, making the online payment journey more seamless and intuitive.

The solution reflects PayU’s continued commitment to building inclusive financial technology and enabling every user to access digital payments with confidence and ease.

The new PayU Accessibility Checkout includes four key features:

• Full-Screen-Reader Optimisation: PayU’s Accessibility Checkout is engineered to work seamlessly with screen readers, ensuring easy navigation of the entire payment journey for the visually impaired and blind without any sighted assistance. From choosing the payment method like Net banking, UPI, QR, NEFT, etc. to payment amount confirmation and transaction completion, every element on the checkout page is clearly and transparently announced via voice commands to the user, ensuring they know where exactly they are in their payment journey.
• Adaptive User Profiles: This feature allows users to customize their checkout environments–adjusting cursor size, button dimensions, and navigation aids to fit their requirements. Their preferences can be saved, switched between or reset at any point. The checkout adapts as the user wants, delivering complete control in the hands of the user.
• Visual Inclusivity Modes: To aid users with conditions such as low vision, colour blindness, or light sensitivity, a wide variety of visual modes are offered by PayU’s Accessibility Checkout. From high contrast to greyscale mode to colour inversion to saturation adjustment options, the checkout offers support to the visually impaired users who rely on colour and contrast adaptations to use digital platforms.
• Text Resizing: The Accessibility Checkout supports text scaling of up to 200% of the standard size, without overlapping or hiding any content. This feature ensures all elements on the checkout is transparently seen and read by the users with visual impairments.

“True financial inclusion is only possible when every individual can access and use digital payments independently. At PayU, accessibility is not an afterthought – it’s a core design principle. With the launch of our Accessibility Checkout, we’re helping merchants deliver payment experiences that are inclusive by design while enabling millions of users with diverse accessibility needs to participate more confidently in India’s digital economy. This is an important step towards supporting the RBI’s accessibility vision and building digital infrastructure that works for everyone,” said Manas Mishra, Chief Product Officer, PayU and Wibmo.

Prashant Ranjan Verma, General Secretary, National Association for the Blind, Delhi, said, “I appreciate PayU’s efforts to make digital payments more accessible for everyone, including people who are blind or have low vision. I was able to complete a UPI payment independently using PayU’s accessibility-first checkout with VoiceOver. I hope PayU continues to strengthen accessibility so that more people with visual impairments can transact confidently and independently.”

PayU’s Accessibility Checkout does not require merchants to change their existing integrations. Accessibility is embedded as a design feature allowing merchants using PayU to automatically offer a compliant and accessibility-first payments checkout experience to their customers with disabilities.

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AI-driven demand underpins logic foundry and memory fab capacity constraints, leading to cost increases. Add tariffs to the mix, and Google and its competitors (not to mention end users) pay the price.

Last year’s Made By Google fall product launch event happened midday on August 20, moderated by Jimmy Fallon. Although I found value in the devices, software and services Google unveiled there, the un-traditional Tonight Show-styled format wasn’t particularly to my liking, a negative opinion shared by a notable number of others whose coverage I subsequently perused.

This year’s event, earlier today (August 12) as I write this, was once again celebrity-moderated, this time by Trevor Noah. But this time it took place in the evening, with the announcements notably preceding it; a flurry of blog posts had already hit Google’s website at 8 am MT, where I am. Feel free to draw your own conclusions as to the judged effectiveness (or, perhaps more accurate, lack thereof) of last year’s event And begging the question of why Google bothered doing this year’s event at all, save I suppose for the chance to see “live” demos, “softball” interviews and other such questionable-value content.

That said, the products themselves once again were notable, both in an absolute sense and relative to their prior-generation predecessors.

Befitting my engineering-dominated readership, I’ll as usual start out my coverage with the application processor, the Tensor G6, the intelligence nexus of the Pixel 11 smartphone series.

Power/performance balance (and profit) optimization

When I published last year’s event coverage, little was known at the time about the latest-generation Tensor G5 SoC save for its 3 nm TSMC fabrication source (a notable departure from Google’s longstanding foundry partnership with Samsung) and its eight-core CPU cluster mix: “one “prime” core, five mid-level ones, and two efficiency ones.” Beyond that, all Google was saying at the time was that, versus its Tensor G4 predecessor, it delivered the following updates.

• An up to 60% more powerful TPU
• A 34% faster on average CPU, and
• New security hardware

One year later, thanks to intensive developer engagement with the platform, we know much more about the Tensor G5 than we did before.

• CPU (8 total cores): 1x Arm Cortex-X4 at 3.78 GHz, 5x Arm Cortex-A725 at 3.05 GHz, 2x Arm Cortex-A520 at 2.25 GHz
• GPU: Imagination Technologies PowerVR (DXT-48-1536)

And now on “Day Zero” of the Tensor G6 era, what’s Google saying about it? Predictably, not much beyond another year’s worth of nebulous hand waving in comparison to the Tensor G5:

Tensor G6 features an upgraded CPU for 25% faster web browsing and 15% quicker app launches. Packing 50% more TPU compute and paired with the latest Gemini Nano model, Google Tensor G6 processes on-device AI tasks up to 3.5 times faster while using up to 3.5 times less energy.

But thanks to a leak sourced from embargoed media hands-on time with the Pixel 11 family, the following additional (and more specific) Tensor G6 specs, referencing Arm’s C-series cores, are also presumably accurate.

The Tensor G6 sports a seven-core configuration, with one prime “C1 Ultra” core clocked at 4.1GHz, four performance “C1 Pro” cores clocked at 3.4GHz, and two efficiency “C1 Pro” cores clocked at 2.65GHz. The GPU appears to be a PowerVR C-series variant with six compute units clocked at 1.3GHz.

One other silicon-related nuance also bears mention. Although, as previously mentioned, Google switched from Samsung to TSMC as its foundry source for the Tensor G5 last year, it stuck with Samsung’s Exynos cellular subsystem. This year, reportedly (although I haven’t yet seen definitive confirmation), this too has changed; Google’s supposedly now leveraging MediaTek M90 5G cellular IP.

Smartphone evolutionary modesty

Aside from the new colorways, you’d understandably likely be hard-pressed to discern a visual difference between Google’s latest handsets—the baseline Pixel 11, high-end Pixel 11 Pro and Pro XL, and book-style Pixel 11 Fold—and their 10th generation predecessors. Backs are once again all-glass. Displays are a bit brighter, and more scratch-resistant in the “Pro” variants. Camera bars are a bit more svelte (along with overall Fold thinness), and for “Pro” versions, embed a multicolor notification LED assembly surrounding the flash and branded “HiLight”. Particularly clever readers may have already noted the enhanced scratch-resistance association, since the notifications can only be seen when the phone is screen-down on a flat surface.

That all said, to the overall “supply constraints” theme of this writeup, I’ll point out that the Pixel 11 storage options now start at 256 GBytes; the entry-level 128 GByte variant of the Pixel 10 that I recently acquired isn’t offered this time around. In Google’s defense, Apple did the same thing a year ago with the iPhone 17 versus its iPhone 16 precursor, although in that earlier case the 2x capacity multiplier came for the same intro price as the 128 GByte prior-gen device.

This time the 256 GByte Pixel 11 price thankfully at least matches that of the year-ago 256 GByte Pixel 10, versus with an accompanying price increase as other smartphone suppliers are doing nowadays. Further to Google’s defense, note that a year ago any bill-of-materials cost increases were predominantly due to tariff impacts. Now, in contrast, supply constraints are additionally being felt to fuller effect. It’ll be curious to see how Apple handles both memory and TSMC foundry cost increases at its likely next-month announcement event; for one thing, the company will reportedly delay the launch of its baseline iPhone 18 until sometime next year.

In closing, at least for this section, one more memory-related twist bears mention. A year ago, I wrote, “Google also didn’t “hide” tariff costs by cutting RAM capacities (which would counterbalance its burgeoning AI ambitions, anyway)”. Well, this year they did. The lowest (256 GByte) storage capacity variants of the Pixel 11 Pro and Pro XL also have less RAM—12 GBytes vs 16 GBytes—than both their higher-capacity this-year siblings and same-capacity Pixel 10 predecessors, in the latter case with no accompanying generational price break. Admittedly, Google’s working hard on optimizing memory requirements for its on-device models, but still…

Watches and trackers

Last year’s Pixel Watch 4 was a notable update to its predecessor(s), as I wrote about at the time (although I’m still fiscally quite content with a recent update from my long-in-the-tooth first-generation wearable to “only” the Pixel Watch 3, more discussion of which I’ll save for another post another day). This year’s Pixel Watch 5 advancements are also more modest, notably including slight (~12%) CPU performance and battery capacity upticks along with an on-device AI-intended RAM upgrade from 2 GBytes to 3 GBytes, the latter leading to—you guessed it—an associated $50 price tag increment.

I’m not entirely sure why Google included a set of earbuds in its launch suite promo photo shown earlier this piece, as aside from a new Pixel Buds 2 (two years old) colorway option and pending firmware-delivered feature updates to both them and the Pixel Buds 2a (introduced a year ago), nothing’s new. Conversely, the most brand-new device released this week was the Pixel Tag, unsurprisingly supportive of Google’s Find My Device network and conceptually similar to (and a competitor of) Apple’s also-UWB-enhanced second-generation AirTag.

Hopefully, this wireless-connectivity enhancement suggests that we’ll be seeing broader support for UWB in both Google’s and other Android licensees’ handsets in the future. My biggest surprise here is that, unlike Motorola and other tracker manufacturers, Google didn’t also adopt an AirTag-clone form factor that would enable it to slot into the already sizeable and still steadily expanding AirTag ecosystem of luggage tags, stealth security setups and the like.

That’s what I’ve got for you today, folks. As always, please sound off with your thoughts in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

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• Google I/O 2026: Agentic AI gets serious
• Google’s Pixel 10: Upgrading smartphones again

The post Made by Google 2026: This limited silicon-supply situation really sucks appeared first on EDN.

NoMIS Power has developed a 6.5-kV large-die SiC MOSFET that has demonstrated over 8 kV of blocking voltage, 90-mΩ on-resistance, and 55-A drain current. Based on the planar SiC technology used in its 3.3-kV devices, the 6.5-kV MOSFET extends the technology into the high-voltage class and provides a foundation for the company’s planned 10-kV MOSFETs and 20-kV SiC IGBTs.

NoMIS is sampling the 6.5-kV SiC MOSFET to U.S.-based customers, with standard-production devices scheduled for Q4 2026. The company plans to expand the 6.5-kV portfolio with additional on-resistance variants, small-die MOSFETs, hybrid junction-barrier Schottky FETs (JBSFETs), and standalone diodes for applications including HVDC power transmission, solid-state transformers, pulsed-power systems, rail traction, and megawatt-scale EV charging

The 6.5-kV devices build on the company’s 3.3-kV SiC MOSFET family, which is already in production, while 10-kV and higher-voltage MOSFETs, diodes, JBSFETs, and SiC IGBTs are in development.

For more information, visit the NoMIS Power Semiconductors and Modules webpage.

NoMIS Power

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NEO.AI is a memory platform from NEO Semiconductor that overcomes SRAM and DRAM scaling limitations in AI memory systems. As part of the platform launch, NEO Semiconductor is introducing its X-SRAM technology for on-chip memory in GPUs and AI processors and reporting its latest progress on 3D X-DRAM, a high-capacity memory technology for HBM.

By replacing conventional six-transistor SRAM with a two-transistor architecture, X-SRAM enables up to 5 times higher memory density to support 1–2 GB of on-chip memory, according to NEO. The technology maintains SRAM-class performance and is compatible with advanced nanosheet CMOS processes. It also provides a path toward future monolithic 3D X-SRAM implementations.

Built on 3D NAND manufacturing processes, 3D X-DRAM delivers up to 10 times higher memory capacity than conventional DRAM, according to NEO. Successful proof-of-concept validation demonstrates its potential as a scalable and manufacturable solution for next-generation HBM.

For more information, visit the NEO X-SRAM webpage.

NEO Semiconductor 

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