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Breakthrough BMC Innovation Powers Secure, Scalable, and Open Compute Platforms

Nuvoton Technology Corporation announced the launch of the Arbel NPCM8mnx System-in-Package (SiP) — a compact, fully integrated BMC subsystem designed to accelerate deployment and simplify system management in next-generation AI servers and datacenter platforms.

As artificial intelligence reshapes the datacenter landscape, the demand for security, high-density, and easily deployable infrastructure is surging. Nuvoton ‘s new SiP solution addresses this need head-on, offering a plug-and-play BMC platform that dramatically reduces design complexity and time-to-market.

Compact Powerhouse for AI and Cloud Infrastructure

The NPCM8mnx-SiP integrates all essential BMC components into a single 23x23mm² BGA package, reducing the subsystem footprint by approximately 70%. This miniaturized form factor is ideal for:

• AI accelerator cards
• Multi-node compute systems
• Remote access modules
• Edge and hyperscale datacenters

Key integrated components include:

• Full-featured Arbel NPCM8mnx BMC
• Embedded DDR4 memory (1 GB to 4 GB)
• eMMC storage (8 GB to 64 GB)
• NOR Flash (16 MB to 128 MB)
• Reference clock oscillator
• Voltage regulators
• Over 120 passive components

This level of integration eliminates the need for high-speed signal simulations, power sequencing, and complex PCB layouts — enabling faster, more reliable product development.

Built for Security and Open Standards

Security is at the heart of the NPCM8mnx-SiP. Built on the latest Arbel A3 architecture, it supports:

• Post-Quantum Cryptography (PQC) LMS algorithms for secure boot
• DICE Unique Secrets generation and customer-specific key provisioning
• Compliance with OCP S.A.F.E. and FIPS 140-3 standards

The SiP is fully compatible with existing Arbel software stacks, including:

• OpenBMC
• OP-TEE / U-Boot / Linux
• pRoT secure firmware stack

This ensures seamless integration into open compute environments and supports industry-wide efforts toward secure and transparent infrastructure.

The post Nuvoton Launches Arbel NPCM8mnx System-in-Package (SiP) for AI Servers and Datacenter Infrastructure appeared first on ELE Times.

Silicon photonics-based chip-to-chip optical connectivity firm Ayar Labs of San Jose, CA, USA — which is pioneering co-packaged optics (CPO) for large-scale AI workloads — says that Vivek Gupta has joined as its first chief strategy officer (CSO). This comes as the industry transitions to next-generation AI architectures that demand the bandwidth, latency and efficiency benefits enabled by CPO...

STMicroelectronics has announced that Rias Al-Kadi, General Manager of the Company’s Range and Connectivity Division, has joined the board of directors of the FiRa Consortium, the industry body dedicated to advancing secured fine ranging and positioning ultra-wideband (UWB) technology.

ST is actively driving the development the IEEE 802.15.4ab amendment, building upon previous UWB enhancements to further improve system performance and expand UWB’s application scope. The ongoing evolution of UWB standards promises significant improvements, including centimeter-level accuracy, enhanced security, and reduced power consumption. These improvements are critical for enabling a wide range of applications, from automotive access and digital keys to smart home automation and IoT innovations. Integrating IEEE 802.15.4ab into the CCC Digital Key ecosystem would represent a major step forward in addressing implementation challenges and accelerate broader adoption of UWB technology in both consumer and automotive markets.

“STMicroelectronics has long been a valued member of the FiRa Consortium, and we are thrilled to welcome them at the Sponsor level. This upgrade is a reflection of ST’s deepening commitment to the future of Ultra-Wideband technology and to FiRa’s mission. We are especially pleased to have Rias Al-Kadi, General Manager of ST’s Ranging and Connectivity Division, join our Board of Directors. His experience and leadership will be instrumental as we continue to expand UWB’s global impact and shape the future of secure, interoperable solutions,” states SK Yong, FiRa Consortium Board Chairman.

“Joining the FiRa board underlines our commitment to advancing the CCC Digital Key and other UWB-based applications,” said Rias Al-Kadi, General Manager, Ranging and Connectivity Division, STMicroelectronics. “By deeply engaging in standardization and certification across all major UWB groups, we are helping to shape the future of UWB technology to deliver maximum value for consumers and industries alike.”

Rias Al-Kadi’s appointment further strengthens ST’s active participation in key UWB standards bodies and consortia, including the IEEE, Connected Car Consortium (CCC), Connectivity Standards Alliance (CSA), and UWB Alliance. Through strategic participation in these groups, ST supports the continuous evolution of UWB technology aimed at enhancing user experiences and lowering system costs, particularly in consumer and automotive access applications. This aligns with ST’s vision to foster a robust UWB ecosystem that enables seamless, secure, and cost-effective solutions for the growing UWB market.

The post STMicroelectronics joins FiRa board, strengthening commitment to UWB ecosystem and automotive Digital Key adoption appeared first on ELE Times.

NEPCON ASIA 2025, taking place from October 28 to 30 at the Shenzhen World Exhibition & Convention Center, is set to deliver an unparalleled platform for the global electronics manufacturing community. With over 3500 participating companies across more than 140,000 square meters and 80 high-level forums, the show will highlight the latest advancements in smart manufacturing, AI-driven automation, robotics, and semiconductor technologies.

According to Fortune Business Insights, the global Electronics Manufacturing Services (EMS) market reached USD 609.79 billion in 2024 and is projected to grow to USD 648.1 billion in 2025, eventually surpassing USD 1 trillion by 2032, underscoring the tremendous growth potential of the electronics manufacturing industry.

Connecting Global Manufacturers with Cutting-Edge Innovation

NEPCON ASIA 2025 will host over 600 leading suppliers from sectors including PCB assembly, smart factories, semiconductor packaging and testing, automotive electronics, and touch display solutions. The exhibition provides an immersive opportunity for international visitors to explore innovative products, witness advanced electronic manufacturing processes, and identify emerging technology trends. Through hands-on demonstrations, component dissections, and real-world production line showcases, visitors will gain insight into the industry’s next-generation solutions.

Driving Industry Transformation with AI and Smart Manufacturing

The concurrent S-Factory Expo will feature AI-driven smart factory and automation forums, showcasing how integration of AI, robotics, and digitalized production systems dramatically enhancing operational efficiency, product quality, and flexibility. Leading robotics companies such as FANUC, Elite Robot, Flexiv, and Fudan University will provide in-depth analyses of AI applications, offering actionable insights for businesses seeking to accelerate production line upgrades and embrace intelligent manufacturing transformation.

Vision + AI: Empowering Intelligent Manufacturing

The Vision China Shenzhen exhibition will highlight the convergence of machine vision and AI with a dedicated “Showcase for Machine Vision Innovative Products” Area and the Vision + AI High-Quality Development Innovation Conference. This platform will unveil global product launches and present full-industry-chain intelligent vision solutions for electronics, new energy, industrial automation, life sciences, and packaging industries. Attendees will gain critical insights into quality inspection, smart production, and process optimization, saving time while unlocking new business opportunities.

Innovative Technology Areas

Specialized Areas at NEPCON ASIA 2025 include:

• Embodied Intelligence Robot & Core Component Dissection Area – Featuring robot controllers, sensors, actuators, and power modules from leading brands such as Qiongche Intelligent, RobStride Dynamics, AISpeech and more, providing a window into the next frontier of robotics.
• AI Smart Glasses Disassembly Area – Showcasing 25 new AI smart glasses launched in 2025 by Huawei, Xiaomi, Meta, Lenovo, and others, integrating advanced optics, chips, sensors, and interactive technologies.
• IGBT & SiC Packaging and Testing Demo Line – Demonstrating over 50 semiconductor packaging and testing processes, supporting industry R&D and process optimization.
• Finished Electronic Product Automated Packaging Demonstration Area – Highlighting flexible manufacturing, automated packaging, and intelligent conveyance solutions from leading suppliers such as Fanuc, Elite, Feixi, and Yongchuang, enabling higher efficiency and quality control for electronic production lines.
• Engaging Global Audiences through Conferences and Forums – NEPCON ASIA 2025 will host 40 high-level forums across automotive electronics, semiconductors, AI, embodied intelligence, and smart glasses, bringing together industry experts, scholars, and practitioners to explore current challenges, future trends, and cross-industry collaboration opportunities. The SMTA International Forum will feature global technical leaders, including Charles E. Bauer Ph.D from SMTA, delivering international perspectives on the evolution of electronics manufacturing technology.

• Unlocking Global Business Opportunities – With a focus on international collaboration, NEPCON ASIA will invite buyers from Thailand, Vietnam, Malaysia, and Indonesia for factory tours, country-specific networking events, and business matchmaking. This ensures meaningful engagement between Chinese manufacturers and global electronics stakeholders, fostering partnerships and uncovering new market opportunities.

The post NEPCON ASIA 2025: Showcasing the Future of Smart Electronics Manufacturing appeared first on ELE Times.

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12 студентів КПІ ім. Ігоря Сікорського відвідають CES 2026 kpi нд, 10/12/2025 - 22:34

In this article, we'll analyze the single-tuned discriminator for FM-to-AM conversion. We'll then discuss the balanced discriminator and how it provides improved linearity across a wider bandwidth.

I just parts-salvaged a Metz camera flash with a burnt-out charging transformer, and found this vintage beauty on the inside. Tell me what you think! submitted by /u/A55H0L3_WindowsXP [link] [comments]

This bloody LM2576-33 (new) gave out 10V instead of 3,3V. Killed two STM32 before I figured out WTH was going on. I am, of course, going to widlarize it, as it it written in the ancient scrolls. submitted by /u/Defiant-Appeal4340 [link] [comments]

After addressing the issue with the shorted Kelvin Leads this instrument a FNIRSI LC2010E, it has so far proven to be a handy tool to have going above and beyond my Fluke DMM. Symptoms were erroneous readings and it would fail the lead calibration check on the short setting. FNIRSI support has also has responded well sending a replacement. submitted by /u/NoAnything604 [link] [comments]

Today I milled another working pcb (for practice) and its turned out great! In the basic TP4056 chip, only replaced the leds with bigger ones. submitted by /u/Big_Lack_ [link] [comments]

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Qualcomm acquired Arduino. This is a result of that acquisition. That was quick! Link to official page - Qualcomm QRB2210 (- 0.4mm pitch BGA package) - STMicroelectronics STM32U585 - 8 layer board submitted by /u/SkunkaMunka [link] [comments]

Born from a minimalist design brief in 1971, the NE555 delivered edge-triggered timing, pulse generation, and oscillation in one compact package, earning a place in everything from washing machines to rocket launchers.

Intel Corp. unveils new details about its next-generation client processor for AI PCs, the Core Ultra series 3, code-named Panther Lake, which is expected to begin shipping later this year. The company also gave a peek into its Xeon6+ server processor, code-named Clearwater Forest, expected to launch in the first half of 2026.

Core Ultra series 3 client processor (Source: Intel Corp.)

Panther Lake is the company’s first product built on the advanced Intel 18A semiconductor process, the first 2-nanometer class node manufactured in the United States. It delivers up to 15% better performance per watt and 30% improved chip density compared to Intel 35 thanks to two key advances—RibbonFET and PowerVia.

The RibbonFET transistor architecture, Intel’s first in over a decade, delivers greater scaling and more efficient switching for better performance and energy efficiency. The PowerVia backside power delivery system improves power flow and signal delivery.

Also contributing to its greater flexibility and scalability is Foveros, Intel’s advanced packaging and 3D chip stacking technology for integrating multiple chiplets into advanced SoCs.

Panther Lake

The Core Ultra series 3 processors offer scalable AI PC performance, targeting a range of consumer and commercial AI PCs, gaming devices, and edge solutions. Intel said the multi-chiplet architecture offers flexibility across form factors, segments, and price points.

The Panther lake processors offer Lunar Lake-level power efficiency and Arrow Lake-class performance, according to Intel. They offer up to 16 CPU cores, up to 96-GB LPDDR5, and up to 180 TOPS across the platform. They also feature new P- and E-cores, along with a new GPU and next-generation IPU 7.5 and NPU 5, delivering higher-performance and greater efficiency over previous generations.

Key features include up to 16 new performance-cores (P-cores) and efficient-cores (E-cores) delivering more than 50% faster CPU performance versus the previous generation; 30% lower power consumption versus Lunar Lake; and a new Intel Xe3 Arc GPU with up to 12 Xe cores delivering more than 50% faster graphics performance versus the previous generation, along with up to 12 ray tracking units and up to 16-MB L2 cache.

Panther Lake also features the next-gen NPU 5 with up to 50 trillion of operations per second (TOPS), offering >40% TOPS/area versus Lunar Lake and 3.8× TOPS versus Arrow Lake-H.

The IPU 7.5 offers AI-based noise reduction and local tone mapping. It delivers 16-MP stills and 120 frames per second slow motion and supports up to three concurrent cameras. It also offers a 1.5-W reduction in power with hardware staggered HDR compared to Lunar Lake.

Other features include enhanced power management, up to 12 lanes PCIe 5, integrated Thunderbolt 4, integrated Intel Wi-Fi 7 (R2) and dual Intel Bluetooth Core 6, and LPCAMM support.

Panther Lake will also extend to edge applications including robotics, Intel said. A new Intel Robotics AI software suite and reference board is available with AI capabilities to develop robots using Panther Lake for both controls and AI/perception. The suite includes vision libraries, real-time control frameworks, AI inference engines, orchestration-ready modules, and hardware-aware tuning

Panther Lake will begin ramping high-volume production this year, with the first SKU scheduled to ship before the end of the year. General market availability will start in January 2026.

Recommended Intel’s confidence shows as it readies new processors on 18A

Clearwater Forest

Intel also provided a sneak peek into the Xeon 6+, its first 18A-based server processor. It is also touted as the company’s most efficient server processor. Both Panther Lake and Clearwater Forest, built on Intel 18A, are being manufactured at Intel’s new Fab 52, which is Intel’s fifth high-volume fab at its Ocotillo campus in Chandler, Arizona.

Xeon 6+ server processor (Source: Intel Corp.)

Clearwater Forest is Intel’s next-generation E-core processor, featuring up to 288 E-cores, and a 17% increase in instructions per cycle (IPC) over the previous generation. Expected to offer significant improvements in density, throughput, and power efficiency, Intel plans to launch Xeon 6+ in the first half of 2026. This server processor series targets hyperscale data centers, cloud providers, and telcos.

The post Intel releases more details about Panther Lake AI processor appeared first on EDN.

Broadcom Inc. launches the Tomahawk 6 – Davisson (TH6-Davisson), the company’s third-generation co-packaged optics (CPO) Ethernet switch, delivering the bandwidth, efficiency, and reliability for next-generation AI networks. The TH6-Davisson provides advances in power efficiency and traffic stability for higher optical interconnect performance required to scale-up and scale-out AI clusters.          

The trend toward CPOs in data centers is to increase bandwidth and lower energy consumption. With the TH6-Davisson, Broadcom claims the industry’s first 102.4 Tbits/s of optically enabled switching capacity, doubling the bandwidth of any CPO switch available today. This sets a new benchmark for data-center performance, Broadcom said.

(Source: Broadcom)

Designed for power efficiency, the TH6-Davisson heterogeneously integrates TSMC Compact Universal Photonic Engine (TSMC COUPE) technology-based optical engines with advanced substrate-level multi-chip packaging. This is reported to dramatically reduce the need for signal conditioning and minimize trace loss and reflections, resulting in a 70% reduction in optical interconnect power consumption. This is more than 3.5× lower than traditional pluggable optics, delivering a significant improvement in energy efficiency for hyperscale and AI data centers, Broadcom said.

In addition to power efficiency, the TH6-Davisson Ethernet switch addresses link stability, which has become a critical bottleneck as AI training jobs scale, the company added, with even minor interruptions causing losses in XPU and GPU utilization.

The TH6-Davisson solves this challenge by directly integrating optical engines onto a common package with the Ethernet switch. The integration eliminates many of the sources of manufacturing and test variability inherent in pluggable transceivers, resulting in significantly improved link flap performance and higher cluster reliability, according to Broadcom.

In addition, operating at 200 Gbits/s per channel, TH6-Davisson doubles the line rate and overall bandwidth of Broadcom’s second-generation TH5-Bailly CPO solution. It seamlessly interconnects with DR-based transceivers as well as NPO and CPO optical interconnects running at 200 Gbits/s per channel, enabling connectivity with advanced NICs, XPUs, and fabric switches.

The TH6-Davisson BCM78919 supports a scale-up cluster size of 512 XPUs and up to 100,000+ XPUs in two-tier networks at 200 Gbits/s per link. Other features include 16 × 6.4 Tbits/s Davisson DR optical engines and field-replaceable ELSFP laser modules.

Broadcom is now developing its fourth-generation CPO solution. The new platform will double per-channel bandwidth to 400 Gbits/s and deliver higher levels of energy efficiency.

The TH6-Davisson BCM78919 is IEEE 802.3 compliant and interoperable with existing 400G and 800G standards. Broadcom is currently sampling the Ethernet switch to its early access customers and partners.

The post Broadcom debuts 102.4-Tbits/s CPO Ethernet switch appeared first on EDN.

Omnivision says its new image sensor captures sharp HDR video in any light, combining speed, clarity, and efficiency for premium phones and action cameras.

POET Technologies Inc of Toronto, Ontario, Canada — designer and developer of the POET Optical Interposer, photonic integrated circuits (PICs) and light sources for the hyperscale data-center, telecom and artificial intelligence (AI) markets — has closed a non-brokered financing with a single institutional investor. In a private placement, the firm issued and sold 13,636,364 common shares and one common share purchase warrant (at a combined price of US$5.50 each) for gross proceeds of US$75m, before deducting related expenses...

Черговий етап у розвитку. Центру декарбонізації енергетики – Енерго-Інноваційного Хабу КПІ Інформація КП пт, 10/10/2025 - 16:32

High school trigonometry combined with four-quadrant multipliers can be exploited to yield sinusoidal frequency doublers. Nothing non-linear is involved, which means no possibly strident filtering requirements.  

Starting with some sinusoidal signal and needing to derive new sinusoidal signals at multiples of the original sinusoidal frequency, a little trigonometry and four-quadrant multipliers can be useful. Consider the following SPICE simulation in Figure 1.

Figure 1 Two analog frequency doublers, A1 + U1 and A2 + U2, in cascade to form a frequency quadruple.

The above sketch shows the pair A1 and U1 configured as a frequency doubler from V1 to V2, and the pair A2 and U2 configured as another frequency doubler from V2 to V3. Together, the two of them form a frequency quadrupler from V1 to V3. With more circuits, you can make an octupler and so on within the bandwidth limits of the active semiconductors, of course.

Frequency doubler operation is based on these trigonometric identities:

sin² (x) = 0.5 * ( 1 – cos (2x) )  and  cos² (x) = 0.5 * ( 1 + cos (2x) )

sin² (x) = 0.5 – 0.5 * cos (2x)   and  cos² (x) = 0.5 + 0.5* cos (2x)

Take your pick, both equations yield a DC offset plus a sinusoid at twice the frequency you started with. Do a DC block as with C1 and R1 above, and you are left with a doubled-frequency sinusoid at half the original amplitude. Follow that up with a times two gain stage, and you have made a sinusoid at twice the original frequency and at the same amplitude with which you started.

This way of doing things takes less stuff than having to do some non-linear process on the input sinusoid to generate a harmonic comb and then having to filter out everything except the one frequency you want.

Although there might actually be some other harmonics at each op-amp output, depending on how non-ideal the multiplier and op-amp might be, this process does not nominally generate other unwanted harmonics. Such harmonics as might incidentally arise won’t require a high-performance filter for their removal.

John Dunn is an electronics consultant, and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

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