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Enterprise SSD accelerates AI server data transfer
Samsung’s PM1763 PCIe 6.0-based enterprise SSD features 9th-generation V-NAND flash memory and a new 4-nm controller. Optimized for AI and HPC servers, the drive is available in 4-TB, 8-TB, and 16-TB capacities. The 16-TB model delivers sequential read and write speeds of up to 28,400 MB/s and 21,900 MB/s, respectively—up to twice the performance of its predecessor, the PM1753.
According to the company, the PM1763 can transfer a 40-GB LLM in approximately 1.4 seconds, helping minimize data latency between processors and accelerators while improving overall AI processing efficiency. The SSD is optimized for liquid-cooled server environments through direct-to-chip cooling. This design enables sustained peak performance while improving power efficiency by up to 1.8 times compared to the previous generation.
To address security requirements for AI and virtualized infrastructure, the PM1763 supports post-quantum cryptography (PQC), the Security Protocol and Data Model (SPDM) 1.4, and Commercial National Security Algorithm (CNSA) 2.0. It also provides link encryption based on the TEE Device Interface Security Protocol (TDISP) to reinforce data protection across storage interfaces.
Samsung has now begun mass production of the PM1763 SSD.
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Stacked-die half-bridge boosts MOSFET power density
Using a vertically stacked-die design, AOS’s DFN6×5 AmpStack package integrates two MOSFETs configured as a high-side/low-side half-bridge. It increases power density and maximizes available PCB space compared to a solution using two discrete DFN5×6 MOSFETs. The package enables high-density power conversion applications ranging from megawatt AI factories to power tools.
The AOPL66801 80-V MOSFET showcases the new half-bridge package with an optimized switch-node clip connecting the high-side and low-side MOSFETs. This architecture minimizes parasitic inductance within the package. Compared to a standard discrete solution, it also reduces PCB parasitic inductance, minimizing phase-node voltage ringing and decreasing stress on the MOSFETs. Key specifications for the AOPL66801 include:
An integrated Kelvin sense pin maintains gate-voltage stability during high di/dt switching. The dedicated connection provides a more effective high-side gate-drive path, helping reduce switching losses. The device also supports a maximum junction temperature of 175 °C for increased thermal capability.
The AOPL66801 is available now in production quantities with a 16-week lead time. Pricing is $6.16 per unit in 1000-piece quantities.
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Hall-effect sensor measures 10-turn position
The Vishay 34 PHE absolute position sensor provides 10-turn linear or rotary displacement sensing with a 3600° range. Using non-contact Hall-effect technology, it delivers up to ±1% linearity (full stroke), 1° resolution, and a service life of more than 10 million cycles.
According to Vishay, the 34 PHE is priced 40% lower than previous-generation devices. It is designed for servo loop motion control systems requiring high accuracy and long-term stability in harsh environments. Typical applications include industrial motor and actuator displacement tracking, solar panel alignment systems, and flow control valve positioning.
The sensor features IP65 sealing and withstands vibration up to 20 g and shock up to 50 g. Integrated reverse-voltage and overvoltage protection (−14 VDC and +28 VDC) reduces the need for external protection circuitry. It supports single or dual analog ratiometric outputs or a digital PWM output. In dual-output mode, the two channels track position in opposite directions to enable basic fault detection. The 34 PHE reports its position immediately after power-up, even following a power loss, without requiring recalibration, homing, or initialization.
Samples and production quantities of the sensor are available now, with lead times of 14 weeks.
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IP enables 8K image and video post-processing
VeriSilicon’s CPP2000 Camera Post-Processing IP improves image quality for reliable vision performance in robotics, drones, and other mobile vision applications. It is designed for straightforward SoC integration and processes YUV images from image signal processors using a range of image enhancement techniques.
The IP supports image and video processing at up to 8K resolution, applying motion-compensated temporal filtering, advanced spatial noise reduction, chroma adjustment, dynamic contrast enhancement, and edge enhancement to improve noise suppression, sharpness, contrast, and overall detail fidelity.
The CPP2000 is implemented as a modular, streaming hardware pipeline in which each stage operates as a dedicated accelerator, enabling continuous real-time processing from input to output. Multiple hardware configuration options are available to address varying requirements for power, performance, area, and latency across applications.
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Hybrid capacitors target automotive power
Taiyo Yuden has introduced the HVX(-K) and HTX(-K) series of AEC-Q200-qualified conductive polymer hybrid aluminum electrolytic capacitors. The 46-device lineup is intended for noise suppression and power smoothing in power supply circuits for automotive control and safety functions such as power steering and ADAS.
The hybrid capacitors provide improved capacitance characteristics over the earlier HVX and HTX series. For instance, the 80-V RAHTX181M1RGP5005K offers a capacitance of 180 µF and a rated ripple current of 3900 mA RMS at 135°C. The devices are available in seven case sizes, with diameters of 6.3 mm to 12.5 mm and heights of 7.7 mm to 16.5 mm.
By combining a conductive polymer with an electrolyte solution, the hybrid capacitors achieve the low ESR of conductive polymers while retaining the self-healing properties of aluminum electrolytic capacitors, enhancing both performance and reliability.
The HVX (-K) and HTX (-K) series are now in production. Detailed information can be found here.
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Teck, Canada Growth Fund and Canada Critical Minerals Accelerator to support strategic metals production
PVA TePla and Fraunhofer IISB establish Joint Lab for aluminium nitride substrates
Solid state airflow sensor with linear 4-20mA output
A self-heated Darlington transistor pair makes a simple, sensitive, and sturdy airflow sensor. But first an annoying non-linearity needs unbending.
If you take a self-heated transistor in a TO-92 package and force it to hold a constant temperature differential above ambient, the power input required to keep it stuck to setpoint will be determined by its thermal impedance ZT relative to the air, as given by:
ZT = ZJ + 1/(SC + KT √AF )
where:
ZJ = junction-to-case thermal impedance = 44°C/W
SC = still-air case-to-ambient conductivity = 6.4 mW/°C
KT = “King’s Law” thermal diffusion constant = 0.75 mW/°C√fpm
AF = air flow in ft/min
Wow the engineering world with your unique design: Design Ideas Submission Guide
The AF term suggests the arrangement might be handy for air flow measurement, because of the way it makes ZT, and therefore power input for a given differential, a function of air speed. Figure 1 shows the resulting power vs AF relation a differential (Dt) = 31oC. Do note, however, the annoying non-linearity.
Figure 1 This graph shows the power dissipated vs air speed of a TO-92 held at a constant 31oC above ambient Pw = 31/ZT.
Figure 2 shows a practical thermostat circuit to achieve and maintain this delta-T while outputting a signal predictably related to Pw. It utilizes a Darlington sensor transistor pair (Q1 and Q2) to compensate for ambient temperature and convert the resulting nonlinear Pw curve into a linearized airflow readout. Its current mode output is compatible with the long cable runs often seen in airflow measurement applications.
Figure 2 This linearized Darlington anemometer circuit supports a 4-20mA current mode output. Adjust R10 to calibrate 4mA (zero fpm), R11 to calibrate 20mA (250fpm).
Here’s how it works.
Q1 serves as the self-heated sensor modeled in the Figure 1 math, with Q2 providing ambient temperature compensation. Opamp A2 runs a feedback loop that forces the Vbe differential between Q1 and Q2 (and thus the temperature differential between Q1 and ambient) to hold a constant 31oC. It does this (with the help of Darlington current gain) by forcing Q1’s current draw (I) through R3 to drive Q1’s power dissipation (Pw) to follow the fig.1 curve of heat-vs-air flow. The resulting voltage developed (IR3) is the basis of the air speed measurement.
Okay so far. But how does compensation for Figure 1’s nonlinearity happen? Well, happily the function of Q1’s Pw vs collector current I isn’t linear either. In fact Pw = 5vI – I2R3. That quadratic I2 term is the key. It creates the lovely linearizing curve shown in Figure 3.
Figure 3 This graph details Q1 power dissipation vs collector current. Pw = 5vI – I2R3.
The 2nd-order curvature of Figure 3 compensates for the bend in Figure 1. Although the match isn’t perfect, when converted to the 4-20mA by opamp A1, the realized output is a calibrated readout of air speed that differs from ideal by less than +/- 5% from 0 to 250fpm, as shown in Figure 4.
Figure 4 This graph’s data relates anemometer output vs airspeed: FPM = 15.6(Iout – 4mA) +/-10FPM.
Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974. They have included best Design Idea of the year in 1974 and 2001.
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- A groovy apparatus for calibrating miniature high sensitivity anemometers
The post Solid state airflow sensor with linear 4-20mA output appeared first on EDN.
Who needs a timing light? I turned an old one into a simple self-powered LED timing light.
 | I reused the housing of an old timing light and built a new LED timing light from scratch. It works for checking ignition timing and adjusting ignition advance on many motorcycles and even carbureted cars with a distributor. The circuit, build process, and testing are covered in the full video. If anyone is interested, the link is in the comments. [link] [comments] |
Infineon supplying CoolSiC MOSFETs 1200V and gate drivers to ADVANTICS
Understanding all costs involved in analog ASIC development
The costs of designing and producing an analog ASIC chip can be grouped into three main parts: human capital, software tools, and prototype fabrication. While all three are equally critical to success, it’s important to note that design tools and wafer foundries are ubiquitous. All semiconductor companies have equal access to them, and it’s rare that a problem with the performance of an analog ASIC comes from the tools used or the wafer foundry that produced it.
Human capital: The ultimate differentiator
If you’re considering an analog ASIC, specification development, circuit design, and physical layout are the most critical steps. These are the true differentiators between the “doers” and “pretenders” (for more on this, read my article “For a Successful Analog ASIC, First Weed Out the Pretenders”).
They require the highest level of analog design skills. I’m referring to teams of craftsmen that have done hundreds of complex precision analog chips that meet requirements others said were impossible. These individuals typically have 30 to 40+ years of experience and can command salaries exceeding $350K per year. They are scarce, they are expensive, and they are worth every penny.
If you remember one thing from the paper mentioned above, let it be this: human capital is the ultimate differentiator.
The feasibility study: De-risking the design
It all starts with a feasibility study conducted by the engineers who will be designing the chip. Figure 1 below shows the steps involved.
Figure 1 The feasibility study must be conducted by the engineers designing the chip. Source: Javelin ASIC Devices
The feasibility study is a risk aversion step intended to identify and quantify risks and establish a plan to mitigate them for a successful result. Additionally, it allows the design team to quantify the time required to do the design and assess a fixed cost to complete it.
Done properly, it can take up to two months to complete the study; more if significant invention is involved, less if the chip is an amalgamation of off-the-shelf existing silicon. These costs range from $20K to $70K and are always credited to the full development if a contract is executed. Since some simulation is required, costly software tools are involved early on.
Figure 2 Human capital and software tools unite in the design phase. Source: Javelin ASIC Devices
Design phase: From specification to architecture
Several things occur during the design phase. The preliminary specification becomes a working document and grows from a 4–6-page product definition paper to an in-depth datasheet that may well exceed 50 pages, becoming more detailed with minimum and maximum limits, definitions of registers, power requirements, and more.
The thoroughness of the datasheet is a measure of the craftmanship of the design team. The datasheet drives the wafer fabrication process selection that matches the requirements for voltage, current, noise, precision, cost, and more to the most optimal foundry and a specific process.
The architecture of the ASIC is defined in functional blocks and teams with decades of experience with those blocks (charge pumps, 24-bit and higher A/D converters, precision low-drift Vrefs, and chopper-stabilized amplifiers) are created and assigned. Whenever possible, programmability using registers is added to tighten Gaussian distributions and maximize yields.
Collaboration, reviews, and designer governance
Weekly calls with the customer’s engineers are scheduled to report on status progress and offer design alternatives that may improve performance, reduce chip size (cost), avoid environmental impacts (electrical noise and temperature variations), add functionality, and more. At the completion of each major block, a design review should be scheduled with the customer’s engineering team that dives deep into a transistor-level explanation of how each aspect of the block works. It includes schematics, simulation result targets compared against specification requirements, and an overview of any external components required.
Software design tools are acquired for the duration of the project. Quarterly calls with customer corporate management are established to review schedules and cash flows. Digital teams are assembled to manage logic, memory, and register requirements.
Test strategy: Third-party vs. custom systems
In parallel with the design of the ASIC itself is the design of the test system. Sometimes evaluating a precision analog ASIC can be as challenging as the chip itself. There are two schools of thought. One is to generate a test specification to be supplied to a third-party test house that fits the capabilities of their array of commercially available test systems.
These companies will review the specifications and recommend which brand of tester is best suited. They will charge a one-time fee for the development of any unique hardware and software program needed to interface your ASIC to their tester. Getting everything up and running can easily cost between $100K and $200K.
An alternative that Javelin uses is to develop a custom test system, specifically tailored for the ASIC. We build two identical systems—one for the wafer probe and one for the final test of the packaged chip. They can be collocated in any test house and interface with the required handlers, or they can be stand-alone.
We prefer this approach because it assures perfect correlation between the wafer probe and final testing. And surprisingly, it’s less expensive. This approach offers complete flexibility in moving testing from one location to another without incurring duplicated tooling costs.
Custom ASIC economics vs. commodity products
When a commodity analog semiconductor company develops a standard product intended to be sold to thousands of disparate customers, they absorb all development costs and amortize it into their unit pricing, hoping their marketing department has identified sufficient sales potential to recover the costs and still show a profit in the long term.
However, when a custom ASIC is involved, the story changes slightly. There is only one customer, and it’s responsible for paying for the complete development. In exchange, it gets exclusivity to the chip.
Exclusivity is important because the justification for paying development costs often includes integrating proprietary IP or creating new inventions to achieve performance advantages over competitors using off-the-shelf components. Other advantages include a significantly smaller size, lower power consumption, protection from product obsolescence, and much more.
Software tools: Powerful but expensive
Although the development costs associated with creating the new IC also include wafer fabrication and package assembly, I want to stay focused on human capital and software tools for a moment. There’s more to it than meets the eye. For those not familiar with chip development costs, the numbers can be intimidating.
While the semiconductor industry often focuses on the multi-billion-dollar capital expenditures of leading-edge digital nodes, the economics of analog IC development follow a distinctly different trajectory. Development does not involve huge capital equipment investments. The investment comes in the form of human capital and tool rental.
Over the past few decades, the tools for supporting analog chip design have improved dramatically, driven in part by the growth in analog applications in automobiles, consumer products, and sensor calibration and signal conditioning, in which precision and accuracy, along with quality and reliability, are of paramount importance. A few of the most popular tools used by analog designers include Cadence Virtuoso and Spectre, Synopsys Primetime, and Mentor Graphics Calibre.
Regardless of whom you select to do your analog ASIC, they will likely use these same tools, as they are available to everyone. However, they are expensive and these costs need to be accounted for. Prices aren’t published and NDAs prevent users from disclosing them, but estimates for a single, fully featured seat for analog/mixed-signal design (layout and simulation) range from $150k-$300k per year. A seat is typically one “open window” for one user, so you can see how the dollars add up quickly.
Prototype fabrication and mask costs
Most silicon fabricators offer multi-product wafers (MPW) for some or all of their processes. These are highly valuable tools for seeing silicon samples at a low cost. They afford the ability to locate and remove any errors prior to production.
On popular processes, they are run monthly, but on others they are run less so, maybe two, three, or six times a year. If you miss the window with an available tape-out, it could be a long wait. MPWs are not required, but when available, they are an important step in evaluating early silicon and debugging test systems well ahead of production.
Whether engaging an MPW or not, the final significant tooling expense is the production mask set. Prices vary from wafer fab to wafer fab and are dependent on the number of masks required to make the ASIC. Figure on spending $75K to $150K.
Figure 3 Test and assembly operations are a critical part of ASIC fabrication costs. Source: Javelin ASIC Devices
Experience matters: Mitigating risk in ASIC development
If an off-the-shelf new chip design runs into a problem, the semiconductor company has the option to simply delay introduction while their engineers sort things out. That is not an option for your ASIC. You are counting on it to be available on a specific date to support the launch of your new or next-generation product.
Don’t be fooled by companies claiming they have been in business for 20 or 30 years. That means very little. What’s important is the experience of the folks doing the work. How long has each engineer been designing analog ASICs?
Everyone makes mistakes, but mistakes are part of learning. You need teams that have made the mistakes decades ago and learned from them. Don’t let your project become a learning experience for novices. You deserve to see the resumes of the people responsible for your ASIC. Ask to see them and insist on speaking with the engineers themselves.
Which brings up another point: you deserve to have direct access to any engineer working on your ASIC. Don’t accept some project manager or marketing manager acting as a gate keeper to be the focal point for all communications between you and your supplier. They add no technical value and insert delays in communications, which more often than not are time critical.
Bob Frostholm is co-founder and CMO of Javelin ASIC Devices.
Related Content
- Analog ASICs Made Simple
- 7 Steps to a Successful Analog ASIC
- Demystifying Analog and Mixed-Signal ASICs
- 7 myths of analog and mixed-signal ASIC design
- A 12-point overview of the advantages of custom analog ASICs
The post Understanding all costs involved in analog ASIC development appeared first on EDN.
Wolfspeed files patent infringement lawsuit in US against Navitas
CXL Type 3: Tooling and boot path from power-on to usable memory
Part 1 of this min-series established why CXL Type 3 memory expanders matter for capacity-bound workloads and where expander memory sits in the latency–capacity pyramid relative to local DRAM. It also explained what must align across the stack before memory becomes usable—CPU and BIOS enablement, kernel CXL support, device firmware, RAS paths, and the NUMA topology that Linux exposes through cxl_pci. Next, it delved into why many CXL problems surface, such as placement or bandwidth imbalance rather than obvious enumeration failures.
This part builds on that foundation with the tools and timeline you need day-to-day to navigate system bring-up. You will learn which user-space utilities reveal what the OS actually sees on the CXL fabric, how to differentiate between “device present” to “memory consumable,” and how to walk the boot sequence from slot power and DRAM training through DVSEC discovery, CEDT read, CDAT delivery, ACPI handoff, and finally driver bind-framing each stage as a validation checkpoint with recognizable failure signatures.
Let’s get to work.
Kernel drivers establish whether a CXL Type 3 device is present, configured, and represented as memory, but validation engineers spend much of their time during bring-up reconciling what firmware advertised, what the driver registered, and how user-visible policy (NUMA placement, DAX/region modes, namespace layout) matches the intended deployment. That reconciliation is difficult from dmesg and kernel logs alone. Practical programs rely on a small set of user-space utilities that expose sysfs and kernel abstractions in forms suitable for automation and field triage.
Essential user-space tooling
cxl/libcxl (often shipped with ndctl sources as “CXL tools”)
The cxl command-line interface and libcxl library walk the CXL sysfs hierarchy—ports, endpoints, memdevs, and decoders—and print structured output, commonly JSON. This is the closest thing to a standard “show me what the OS thinks on the CXL fabric” tool; serial numbers, capacity hints, which PCI function hosts a memdev, and whether decode topology looks sane before debugging performance or NUMA. It’s usually the first stop after dmesg when firmware and driver disagree about what should be visible.
ndctl
ndctl provides user-space administration for the LIBNVDIMM/regions/namespaces model that Linux also uses for some persistent-memory-class bring-up paths. Depending on kernel and platform integration, CXL-attached memory may surface as a separate NUMA node or through PMEM-style abstractions. ndctl lists regions, creates or destroys namespaces, and clarifies whether capacity is in a state software can consume, not merely whether a PCI device exists.
daxctl
daxctl manages direct-access (DAX) devices and related system-RAM or devdax configuration knobs exposed by the kernel. Some deployments expose memory through DAX-oriented paths, especially when treating capacity like PMEM/DAX rather than only anonymous DRAM. daxctl helps verify mode, online/offline behavior, and whether the system matches workload expectations. Misconfiguration here often looks like “memory is there but unusable, wrong interface, or wrong policy.”
numactl and numastat
numactl controls NUMA placement policy; numastat reports per-node memory statistics. Expander memory frequently lands as a separate NUMA node or as far memory relative to a socket. These tools prove placement hypotheses during bring-up, bind threads and allocations, measure local versus remote behavior, and catch cases where OS defaults silently place hot pages on CXL. Many “CXL is slow” bugs are NUMA policy bugs, not link bugs.
acpica-tools
This suite provides a useful utility, acpidump, which extracts ACPI tables from the kernel and dumps the raw values of the specified ACPI table. While a user should not need this during regular bring-up, it can be very useful in sticky situations when the DDR memory enumerates but does not show up either as a NUMA node or as a PMEM device. In such cases, it might be useful to dump certain acpi tables and parse raw values via a debug script.
lspci and setpci (pciutils)
Since CXL Type 3 memory expanders attach over a PCIe/CXL link, pciutils belongs in every bring-up kit alongside CXL-specific tools. lspci lists PCI functions on the bus, reports vendor and device IDs, class codes, negotiated link speed and width, and—when invoked with verbose flags—the extended capability chains that expose CXL and DVSEC registers. It’s often the fastest way to confirm that the endpoint is visible at the transport layer, that link training reached the expected generation and lane count, and that the kernel bound the intended driver (for example cxl_pci).
setpci reads and writes configuration-space dwords for targeted experiments during debug—checking capability offsets, toggling test bits where platform policy allows, or verifying that firmware left key control fields in the expected state. Used together, lspci answers “what does the bus see?” (peek) and setpci supports “can we inspect or adjust a specific config field?” (poke) before diverting attention to higher-level CXL utilities or firmware logs.
Topology and observability helpers
lstopo/hwloc produce human-readable CPU–memory topology maps—useful to confirm how the OS labels CXL memory relative to sockets. lspci/setpci (pciutils) confirm the PCI/CXL function at the bus level when debugging binding (cxl_pci versus overrides) and link issues. A verbose lspci dump reveals device capabilities that Part 3 decodes in detail.
Another, currently open-source, tool for viewing the PCIe hierarchy is pcicrawler, which shows the PCIe topology similar to lspci but in a nicer format.
From power-on to usable memory
The end-to-end path for a CXL Type 3 memory expander runs from first application of host and slot power to the point the operating system can issue CXL.mem accesses to host-managed device memory (HDM). Exact timing and responsibility splits vary by CPU, root complex, memory expander ASIC, and BIOS, but the dependencies recur. In other words, power and clocks before reset release; DDR readiness before credible capacity reporting; configuration-space discovery before decode programming; and table exchange before stable OS topology.
Boot sequence is shown for a system with CXL memory expander. Source: Author
- Power, clocks, and ASIC bring-up
The sequence begins when host platform and slot power are applied. The expander ASIC must reach an internally consistent state: regulators settle, oscillators stabilize, PLLs lock, and on-chip reset completes so an embedded control processor can execute first-stage firmware. The host must provide a stable PCIe reference clock and manage PERST# deassertion per PCIe/CXL electrical requirements, so the endpoint is not expected to train before clocks and power are valid. During this phase, the device is not yet advertising complete HDM metadata.
- On-device DRAM: controller release, training, and SPD
The ASIC releases reset to the DDR controller and run DRAM initialization and training for attached DIMMs. Firmware discovers configuration and capacity through serial presence detect (SPD) reads. In parallel, the ASIC initializes high-speed SerDes and the PCIe/CXL controller. There is a critical interval where HDM must not be treated as authoritative.
Firmware clears or gates HDM metadata until DRAM discovery completes—conceptually mem_info_valid = 0. Only after capacity and layout are known does firmware program HDM-related fields in PCIe extended configuration space via CXL-designated vendor-specific extended capability (DVSEC) structures and assert mem_info_valid = 1.
- PCIe link training, DVSEC, and HDM registration
As link training toward the host begins, firmware populates HDM capability structures through DVSEC containers—HDM instance count, per-region sizing, and validity flags. Setting “memory info valid” is the device’s contract that subsequent host reads from HDM descriptors consistent with trained DRAM.
- PCIe/CXL link up and configuration-space discovery
When the physical link reaches DL_Up at negotiated width and speed, the host enumerates the endpoint as a PCI function, parsing capability lists to discover CXL entries, DVSEC registers, and HDM decoders.
- Decode programming and mem_enable
Platform firmware must program host-side address decoding, so HDM contributes to the system physical address map. A common milestone is establishing the system physical address window and asserting memory enable (mem_enable). When mem_enable is recognized, device firmware may finalize the coherent device attribute table (CDAT) for OS/firmware NUMA heuristics.
- CDAT delivery via DOE and mailbox exchange
CDAT is typically transported using data object exchange (DOE) over CXL.io. The CXL mailbox command interface supports diagnostics and device management. Treat DOE/CDAT success and mailbox responsiveness as separate health checks.
- Firmware table construction and OS handoff
Host firmware synthesizes ACPI tables, including CXL Early Discovery Table (CEDT), System Resource Affinity Table (SRAT), and Heterogeneous Memory Attribute Table (HMAT), exposing HDM ranges as distinct memory affinity domains—often NUMA nodes.
- OS driver binding
On Linux, cxl_pci binds to the PCI/CXL function, exposes memdev objects, and enables memory to be onlined. Once complete, the host can issue CXL.mem loads, stores, and DMA through the programmed decode window.
Read the boot flow as a chain of implied tests—power/clock/PERST, DDR training, valid HDM, stable link, decode/mem_enable ordering, CDAT/DOE liveness, ACPI coherence, driver bind, and memory online. Failures produce characteristic signatures at each stage.
Part 3 applies this framework to hands-on test and debug: lspci field interpretation, NUMA verification with numactl, memory-mode configuration with daxctl, and workload tools for bandwidth and stress validation.
Ameet Sanghavi works in post-silicon validation for PCIe and CXL at Nvidia with a focus on interface bring-up and validation on shipping products. He has worked on PCIe since 2005 (from PCIe 1.1 onward) and on CXL since 2020 (from CXL 1.1 onward).
Editor’s Note
Part 1 of this mini-series on CXL Type 3 memory technology explains why AI and data-intensive workloads are driving interest in memory expanders and how CXL Type 3 devices differ from local DIMMs even when they appear as ordinary RAM. Part 3 covers integration modes and when boot parameters apply.
The views and content of the article are author’s own and not affiliated to any of his current or previous employers.
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The post CXL Type 3: Tooling and boot path from power-on to usable memory appeared first on EDN.
Пілотне впровадження проєкту Erasmus+ «EcoMinds»
КПІ імені Ігоря Сікорського є активним учасником європейського проєкту Erasmus+ «EcoMinds» (Enhancing Environmental Data Collection through Machine Learning and Database Systems), до реалізації якого залучено п'ять факультетів університету. Проєкт поєднує інформаційні технології та екологію, готуючи майбутніх фахівців до розв'язання глобальних кліматичних і природоохоронних викликів.
Open source hardware and software watch pcb i made if anyone interested
 | submitted by /u/coolkid4232 [link] [comments] |
Making noise with a BANG, part 1: Concept and hardware
This noise generator has an adjustable bandwidth and a consistent amplitude no matter what bandwidth is selected.
When working on a recent Design Idea for an adjustable filter, I wanted to use an electrical noise source to generate an FFT spectrum graph on my oscilloscope. To set up the test, I reached for my signal generator, which I knew had a noise generator option. I hooked the signal generator to the filter input and the scope to the filter output and turned on the scope’s FFT display function. I then set the filter to 10 kHz and set the signal generator noise standard deviation to its maximum of 3.0 volts.
Wow the engineering world with your unique design: Design Ideas Submission Guide
The output of the filter was a minuscule signal. Here’s what I’d ignored – the signal generator outputs a white noise signal with a 3.0 v standard deviation, but its bandwidth is 25 MHz. When I reduced the bandwidth with the filter, the amplitude dropped. With a perfect brick wall filter, this would reduce the standard deviation by the square root of (10 kHz/25 MHz). So, the 3.0 v standard deviation becomes about 60 mV after filtering. This small signal can be easily corrupted by noise existing in a test setup.
This standard deviation reduction comes from the way white noise signals add. Basically, if a signal is uncorrelated white noise and you add it to a second uncorrelated white noise source of the same standard deviation, the combined signal’s standard deviation will increase by the square root of 2. Alternately, when you filter out half of the spectrum of a noise signal with a brick wall filter, the standard deviation will decrease by the square root of 2.
It occurred to me that a noise signal generator should compensate for this reduction if you want to use a narrower portion of its bandwidth. For example, if the project under test is a device for audio, maybe you only need a noise source spanning only up to 50 kHz. Or maybe you’re testing a signal chain’s response for a low-frequency vibration sensor; in this case maybe a 1 kHz span is enough. But in either example you will want the signal’s standard deviation to be large enough to get a clean FFT.
So, how would I create a testing device to give me a noise generator that has an adjustable bandwidth and a consistent amplitude no matter what bandwidth is selected? The first thought was the typical white noise generator created with reversed biased Zener diode or base-emitter transistor junction followed by an adjustable low-pass filter and then an amplifier with some form of automatic gain control (AGC). But then it occurred to me that a micro I’d used recently has a random number generator and a fairly fast DAC for output…hmm.
Let’s take a look at what I came up with (Figure 1). First the name – the concept for this project idea is a Bandwidth Adjustable Noise Generator, which gives rise to the device’s nondescript acronymic moniker of “BANG”. The BANG is a micro-based generator that allows you to set the bandwidth you desire using a touchscreen. It then generates a noise signal with the standard deviation digitally compensated for that bandwidth.
Figure 1 The BANG is a micro-based generator that allows you to set, on a touchscreen, the bandwidth you desire. It then generates a noise signal with the standard deviation digitally compensated for that bandwidth. The device also has a knob to manually adjust the generated signal.
The device also has a good old-fashioned knob to manually adjust the generated signal somewhat, so you can tweak it. Its output has a maximum output of around 3.1 v and is available as an AC signal (biased at 0 v) or a DC signal (biased at around 1.65 v). The bandwidth adjustment of the noise signal goes from 225 kHz to 500 Hz, and this adjustment is accomplished using an LCD and touchscreen.
The hardwareThe heart of the BANG is a Microchip Technology ATSAMD51 processor. The adjustable digital filter project mentioned earlier also used a ATSAMD51, which has a true random number generator (TRNG). It’s best to let the Microchip data sheet describe this feature:
The True Random Number Generator (TRNG) generates unpredictable random numbers that are not generated by an algorithm. It passes the American NIST Special Publication 800-22 and Diehard Random Tests Suites. The TRNG may be used as an entropy source for seeding an NIST approved DRNG (Deterministic RNG) as required by FIPS PUB 140-2 and 140-3.”
These 32-bit numbers sound perfect for constructing a noise signal source! Using the same processor as before also meant I could reuse a large portion of the LCD and touch screen code, IIR digital filter code, battery monitor code, and various other initialization and housekeeping pieces. Besides the micro, another major piece of the design is the touchscreen, which is an ILI9341 2.8″ 240×320 pixel TFT LCD with a SPI interface.
The other major electronic piece is the analog back end (ABE). One part of the ABE is a reconstruction filter (sometimes referred to as an anti-imaging filter) attached to a DAC on the micro. It essentially filters out-of-band high frequency content carried along with the digitally generated noise signal as it is sent out of the DAC. The filter is a 4-pole Sallen-Key low pass filter with a cutoff frequency of 250 kHz (I used TI’s Webbench filter design tool to calculate the component values). The ABE section also has a potentiometer-adjustable gain stage from around 0.25x to around 2.5x of the ADC signal. The last part of the ABE is a simple output buffer driving the AC and DC outputs. Figure 2 shows the complete schematic.
Figure 2 The heart of the BANG is a Microchip Technology ATSAMD51 processor.
There are a few odds-and-ends on the schematic that I haven’t mentioned yet. First, the micro format I used is an Adafruit Feather M4 Express Arduino board, powered via USB or, alternately, a 3.7 v lithium polymer battery. The Arduino board also contains a charger for the battery. Being able to power it from the battery may be more convenient in some situations, and better yet, it can provide ground isolation if desired in your setup.
The USB pin shown is actually a regulated 3.3 v source that is used to power the rest of the circuitry. You’ll also notice a voltage divider, connected to an ADC on the micro, used to measure the USB voltage for display purposes. The ON/OFF switch actually connects to the EN (enable) pin. The BANG is powered off when the EN pin is pulled to ground. A Vcc/2 reference circuit can also be seen and is used to provide a center voltage for the single-supply operated op-amps.
More to comeNext time, I’ll describe the BANG’s firmware, integration, and operating results. Until then, I welcome your thoughts in the comments on what I’ve discussed so far!
Note that the schematic, code, 3D print files, Arduino software, links related to various parts of the project, and additional notes and pictures on the project’s design and construction can be downloaded for free at the MakerWorld website.
Damian Bonicatto is a consulting engineer with decades of experience in embedded hardware, firmware, and system design. He holds over 30 patents.
Phoenix Bonicatto is a freelance writer.
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The post Making noise with a BANG, part 1: Concept and hardware appeared first on EDN.
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