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From specification to simulation: Modeling PPTC devices in QSPICE
Surface-mount polymer positive temperature coefficient (PPTC) devices are widely used resettable protection components in modern electronic systems. These devices are commonly selected when designers require automatic recovery after a fault, which makes them useful in consumer electronics, telecommunications equipment, industrial systems, and medical devices.
Despite their widespread use, detailed SPICE models for these components remain uncommon. Datasheets typically provide static electrical characteristics, but dynamic models that allow designers to simulate real operating conditions are rarely available.
Yet many practical operating scenarios can be reproduced effectively through simulation. Examples include overcurrent or short to ground events on a USB 5-V supply line, short circuit faults on a lithium-ion battery, or motor stall protection under varying ambient temperatures.
The value of such simulations is clear: they illustrate the consequences of complex overcurrent conditions or potential failure scenarios before hardware is built. In particular, modern simulation tools such as QSPICE make it possible to evaluate large parameter sets quickly, allowing designers to explore how protection devices behave under a wide range of electrical and thermal conditions.
However, modeling these devices accurately raises important questions. Designers must consider whether the model includes the large tolerances inherent to these components, whether ambient temperature influences the results, whether device aging after a trip event is represented, and how trip-time curves versus fault current are incorporated.
All these concerns are valid. If models are to be used effectively, these factors must be addressed so that simulations produce results that reflect real-world behavior.
PPTC SPICE model genesis and thermal fundamentals
From a functional perspective, a PPTC device can be approximated as a thermal mass with a baseline electrical resistance at ambient temperature. When a fault current flows through the device, resistive heating raises the internal temperature. Once the temperature reaches the trip temperature (Ttrip), the device undergoes a rapid increase in resistance. This sharply reduces the current and stabilizes the device at an elevated temperature.
The heat balance of the system can be described by the following equation:
In this equation:
- Cth represents thermal capacitance
- dT/dt represents rate of temperature change
- D represents thermal conductivity constant
- Tamb and T represent ambient and device temperature
- R(T) represents temperature-dependent resistance
- I represents fault current
Before tripping, the resistance can be approximated as a linear function of temperature using a temperature coefficient:
From equations (1) and (2), we derive and simplify:
In fact, here 𝑇𝑎𝑚𝑏 = T25 = 25°C
By integrating equation (3) from t = o to ttrip and from T = 25°C to T= Ttrip, we get:
When the theoretical curve derived from this model is plotted and compared with measured device data, differences become apparent, as shown in Figure 1.
Figure 1 The theoretical trip-time versus fault-current curve is compared with representative measured data. Source: Vishay
The simplified single thermal block model reveals clear limitations at both low and high fault currents. At high currents, the ideal slope of ln (trip time) versus ln (fault current) should be −2, because trip time is inversely proportional to dissipated power, which scales with the square of current.
In practice, the observed slope is significantly flatter. This indicates that additional physical mechanisms influence the thermal response at high current levels. At low fault currents, the theoretical curve rises more steeply than measured results. This discrepancy arises because a PPTC cannot be modeled as a single thermal mass dissipating heat through a single thermal resistance.
Additional factors include:
- Heat dissipation through solder joints and PCB copper
- Delayed thermal propagation in the polymer structure
- Resistance changes caused by device aging
Practical SPICE modeling of PPTC devices
Under lower current conditions, the thermal behavior of a PPTC device can be represented more accurately using a multi-stage thermal network. An example of this approach is shown in Figure 2, where a three-stage thermal Cauer network represents heat flow inside the device.
Figure 2 Here is an example of a three-stage thermal Cauer network representing heat flow within a PPTC device installed in an application circuit. Source: Vishay
In this model:
- Tpptc represents temperature of internal polymer material
- Telectrode represents temperature of device electrodes
- Tpcb represents temperature at PCB solder joint
- Tambient represents far-field ambient temperature
Each stage includes thermal resistance and thermal capacitance elements that model heat transfer between nodes.
The simulations described in this work were implemented in QSPICE, which provides powerful parameter-sweep capabilities. This allows multiple device and environmental parameters to be varied simultaneously, enabling thousands of simulations to be performed in a short time.
Once the thermal parameters are adjusted to match measured trip-time behavior, the simulated results closely reproduce measured data. The comparison between simulation and measurement is shown in Figure 3.
Figure 3 Simulated trip-time versus fault-current characteristics is compared with measured data. Source: Vishay
Remaining deviations are largely attributed to measurement conditions and inherent device tolerances. Nevertheless, the multi-stage thermal model provides a substantial improvement over the simplified single-block model.
Additional model features can also be incorporated, including:
- Resistance aging following a trip event
- Failure behavior when applied voltage exceeds rated limits
- Ambient temperature dependence
Influence of ambient temperature
Ambient temperature has a strong influence on PPTC device behavior. The simulation circuit used to investigate this behavior is shown in Figure 4:
Figure 4 An example application circuit is used to evaluate PPTC behavior under surge conditions at different ambient temperatures. Source: Vishay
Two successive voltage pulses are applied under varying temperature conditions. The resulting waveforms are shown in Figure 5.
Figure 5 Simulation results display device response to successive voltage pulses at different ambient temperatures. Source: Vishay
Here, several effects can be observed:
- Trip time varies with ambient temperature
- Device resistance increases following the first trip event
- Excessive voltage may force the device into a short circuit state
Because of this temperature dependence, datasheets typically provide thermal derating curves describing how allowable current varies with ambient temperature. An example of such a curve is shown in Figure 6.
Figure 6 A typical thermal derating curve illustrates how allowable hold current decreases as ambient temperature increases. Source: Vishay
The behavior behind this curve can also be reproduced through simulation. The circuit used for this analysis is shown in Figure 7, and the corresponding simulation results appear in Figure 8.
Figure 7 A simulation circuit is used to evaluate device behavior under varying load resistance and ambient temperature conditions. Source: Vishay
Figure 8 Simulation results display trip-time behavior as temperature and load conditions change. Source: Vishay
From these results, the variation of fault current as a function of ambient temperature can be extracted. The resulting simulated derating curve is shown in Figure 9.
Figure 9 The simulated thermal derating curve is derived from the SPICE model. Source: Vishay
Application simulations
Once realistic device models are available, they can be used to simulate complete application circuits.
USB power supply protection
A typical USB protection circuit is shown in Figure 10.
Figure 10 The application circuit illustrates a USB power supply protected by a PPTC device. Source: Vishay
Simulation results for plug-in disturbances and short circuit events are shown in Figure 11.
Figure 11 Simulation results show device response during plug-in events and short circuit disturbances. Source: Vishay
At 100 ms, a load short circuit is introduced. The PPTC device transitions from a low resistance state to a high resistance state, limiting the current.
Motor stall protection
An example motor protection circuit is shown in Figure 12.
Figure 12 The circuit example of a small electric motor is protected against stall conditions using a PPTC device. Source: Vishay
Simulation results demonstrating the stall event appear in Figure 13.
Figure 13 Simulation results show motor current increase and protection device trip during a stall event. Source: Vishay
When the motor stalls, I(Vspeed) drops to 0, and the current rises sharply. The protection device heats and transitions to a high resistance state, limiting current and preventing thermal damage.
Lithium-ion battery short circuit protection
The simulated battery protection circuit is shown in Figure 14, with results presented in Figure 15.
Figure 14 The simulation circuit represents a lithium-ion battery system with short circuit protection. Source: Vishay
Figure 15 Simulation results display surge current and resulting resistance increase after a load short circuit. Source: Vishay
At lower ambient temperatures, the device responds more slowly, allowing higher surge currents before tripping.
QSPICE modeling upside
The SPICE modeling approach described here demonstrates that realistic PPTC device behavior can be reproduced by fitting model parameters to datasheet characteristics and incorporating accurate thermal representations.
Using a simulation environment such as QSPICE enables designers to explore these behaviors efficiently through extensive parameter sweeps and transient analysis. The models can account for:
- Resistance tolerance
- Aging effects
- Ambient temperature dependence
- Overvoltage behavior
By incorporating these models into full application simulations, designers gain insights that cannot be obtained from datasheets alone. Nevertheless, simulation should always be complemented by laboratory validation before releasing a design into production.
Alain Stas is head of product marketing for non-linear resistors at Vishay.
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The post From specification to simulation: Modeling PPTC devices in QSPICE appeared first on EDN.
Вітаємо КПІшників — переможців Міжнародного конкурсу студентських наукових робіт «Black Sea Science 2026»
✅ Конкурс щороку проходить на базі Одеського національного технологічного університету під егідою Black Sea Universities Network та ISEKI-Food Association, об’єднуючи молодих дослідників із різних країн.
КПІ ім. Ігоря Сікорського та ENSTA Paris розширюють партнерство
🇺🇦🇫🇷 🤝 Співпраця між КПІ та ENSTA Paris — однією з провідних інженерних шкіл Франції — триває вже понад 10 років. Нині вона виходить на новий рівень завдяки підтримці програми Erasmus+ KA171 Європейської комісії та французького національного агентства Erasmus+.
❤️ Запрошуємо на онлайн лекцію “ШІ та академічна доброчесність: воля та свідомість”
Бібліотека КПІ запрошує дослідників КПІ ім. Ігоря Сікорського та усіх охочих долучитися до онлайн лекції “ШІ та академічна доброчесність: воля та свідомість”, що відбудеться в межах курсу відкритих лекцій “Академічна ДоброЧесність: правила гри чи справа честі”.
My custom 3 byte SRAM on a breadboard
 | submitted by /u/KrisMakesRandomStuff [link] [comments] |
Aeluma’s CEO Jonathan Klamkin to receive IPRM Award
Aeluma’s CEO Jonathan Klamkin to receive IPRM Award
GHz-harvested power for Gbps wireless link is a double win
A clever millimeter-wave lens enables a high-speed, backscatter-powered GHz-band link.
Wireless system designers are often asked to deliver on seemingly incompatible and contradictory goals such as supporting ultrahigh wireless data rates, and do so at ultralow power. Accomplishing this, even if possible, is a challenge which may require lots of technical “tricks” including advanced techniques, custom components, and more.
Now, a team at Georgia Institute of Technology (better known as Georgia Tech) has demonstrated a what they call a first-of-its-kind lens-enabled backscatter system capable of multi-gigabit data rates. At the same time, this backscatter-powered system operates using only a fraction of the power required by conventional wireless devices, therefore bringing high-speed connectivity to disbursed systems.
In general, due to power constraints, backscatter has typically been used only to send small amounts of data, most often in simple identification and sensing systems. However, the researchers say that backscatter doesn’t have to be slow and can operate at gigabit‑per‑second speeds while remaining ultra‑low power—with the right architecture. They foresee applications such as battery-free sensors embedded throughout smart cities and with digital infrastructure for a localized IoT arrangement.
Their lens-enabled backscatter system is capable of multi-gigabit data rates, reaching up to 4 gigabits per second (Gbps) (Figure 1). This dielectric lens focuses incoming millimeter-wave energy (such as from 5G systems) onto an array of tiny antenna elements, allowing both wireless energy capture and high‑speed backscatter communication within the same system.
Figure 1 A close‑up view of the device displays an array of tiny antenna elements positioned behind the lens, each modulating reflected wireless signals to enable high‑speed communication with minimal energy use. (Image source: Georgia Tech School of Electrical and Computer Engineering)
Signals at these frequencies are highly directional and sensitive to alignment; even a small misalignment can break the link. Their lens overcomes that constraint by enabling high gain and wide angular coverage simultaneously, without the need for active beam steering.
The system that can communicate over a ±55-degree field. In their tests, the researchers achieved data rates of up to 4 Gbps with sustained gigabit communication at distances of up to 20 meters, using high-order modulation schemes like those used in modern cellular networks. The system is extremely efficient and requires just 0.08 picojoules per bit. The link-budget analysis projects 1 Gbps back-scatter ranges up to 2.6 km under the 75 dBm effective Isotropic radiated power (EIRP) that is permitted in 5G millimeter-wave systems.
At the core of the millimeter-wave identification (mmID) is a broadband, cross-polarized antenna designed to operate across the full 26–30 GHz band. A broadband element is essential to sustain gigabit-level backscatter, since narrow- band operation would constrain throughput and increase distortion under high-order modulation. Cross-polarization is critical at mmWave, as a co-polarized backscatter would be masked by strong transmitter-receiving coupling from the reader.
To meet these requirements, they implemented a single-layer, capacitively coupled patch antenna designed in CST Microwave Studio and fabricated on Rogers 3003 (εr = 3:00, tan δ = 0:0013), with thickness of 0.254 mm (Figure 2).
Figure 2 a) Layout of the cross-polarized capacitive-coupled patch antenna with dimensions W = 2.85 mm, LS = 1.1 mm, and GC = 0.12 mm. b) Measured vs. Simulated S11 results of the broadband antenna. c) Layout of the FET-based mmWave modulator with dimensions R1 = 1.11 mm and R2 = 1.24 mm. d) Measured vs. Simulated S21 results of the mmWave modulator network. e) Layout of the pixel backscatter element, comprised of the broadband antenna and FET-based wireless mixer. (Image source: Nature Communications)
Gigabit backscatter at mmWave frequencies requires an antenna module that delivers both high gain and wide angular coverage. A dielectric lens provides an efficient solution, acting as a passive focusing element that concentrates incident energy onto the pixel. A key contributor to this long-range performance is the PTFE dielectric lens, which passively concentrates incident mm-wave energy onto the pixel element in a manner analogous to an optical lens. To extend the single pixel design into a practical mmID with wide angular coverage, a 25-element broadband cross-polarized pixel array was implemented, arranged in three concentric rings with a central element (Figure 3).
Figure 3 a) Proposed broadband cross-polarized mmID featuring 25 antenna elements with dimensions L1 = 26 mm, L2 = 52 mm, L3 = 78 mm, W = 90 mm, S = 13 mm, and R3 = 1.35 mm. b) Proposed PTFE lens with dimensions labeled D1 = 74 mm, D2 = 120 mm, and h = 25 mm. (Image source: Nature Communications)
The team performed extensive tests spanning a range of frequency bands, data formats, modulation types, and more, with detailed quantitative results summarized in various tables (Figure 4). They have shown that it is possible to extract GHz-range ambient-RF energy effectively using a printed lens-like antenna.
Figure 4 a) Experimental setup of the proposed lens-based mmID at incidence angles of 0∘ and 55∘ from the PoC reader. b) Block diagram of the PoC reader transmitting and receiving chain to interrogate the lens-based mmID and demodulate the gigabit per second data-rate backscatter. (Image source: Nature Communications)
The detailed project is a fascinating investigation and exploration into RF-based energy harvesting and ultralow-power systems design, without speed compromise. It is described in detail in their readable paper “Broadband multi-beam lens-assisted mmID enabling multi-gigabit backscatter data rates for next-generation wireless networks” published in Nature Communications.
What’s your view on the innovation and cleverness of this project? Is it as impressive as they maintain, or just a well-crafted and analyzed implementation of existing ideas? Is it yet another attention-getting energy-harvesting scheme with added gigahertz connectivity, or does it represent a genuine advance?
—Bill Schweber is a degreed senior EE who has written three textbooks, hundreds of technical articles, opinion columns, and product features. Prior to becoming an author and editor, he spent his entire hands-on career on the analog side by working on power supplies, sensors and signal conditioning, and wired and wireless communication links. His work experience includes many years at Analog Devices in applications and marketing, and he also developed significant mechanical-engineering insight while designing control electronics for large materials-testing systems.
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The post GHz-harvested power for Gbps wireless link is a double win appeared first on EDN.
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